Line data Source code
1 : /*
2 : * Copyright 2018 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #ifndef __DAL_CLK_MGR_INTERNAL_H__
27 : #define __DAL_CLK_MGR_INTERNAL_H__
28 :
29 : #include "clk_mgr.h"
30 : #include "dc.h"
31 :
32 : /*
33 : * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also
34 : * used in resource, perhaps this should be defined somewhere more common.
35 : */
36 : #include "resource.h"
37 :
38 :
39 : /* Starting DID for each range */
40 : enum dentist_base_divider_id {
41 : DENTIST_BASE_DID_1 = 0x08,
42 : DENTIST_BASE_DID_2 = 0x40,
43 : DENTIST_BASE_DID_3 = 0x60,
44 : DENTIST_BASE_DID_4 = 0x7e,
45 : DENTIST_MAX_DID = 0x7f
46 : };
47 :
48 : /* Starting point and step size for each divider range.*/
49 : enum dentist_divider_range {
50 : DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */
51 : DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */
52 : DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */
53 : DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
54 : DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
55 : DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
56 : DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
57 : DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */
58 : DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
59 : };
60 :
61 : /*
62 : ***************************************************************************************
63 : ****************** Clock Manager Private Macros and Defines ***************************
64 : ***************************************************************************************
65 : */
66 :
67 : /* Macros */
68 :
69 : #define TO_CLK_MGR_INTERNAL(clk_mgr)\
70 : container_of(clk_mgr, struct clk_mgr_internal, base)
71 :
72 : #define CTX \
73 : clk_mgr->base.ctx
74 :
75 : #define DC_LOGGER \
76 : clk_mgr->base.ctx->logger
77 :
78 :
79 :
80 :
81 : #define CLK_BASE(inst) \
82 : CLK_BASE_INNER(inst)
83 :
84 : #define CLK_SRI(reg_name, block, inst)\
85 : .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
86 : mm ## block ## _ ## inst ## _ ## reg_name
87 :
88 : #define CLK_COMMON_REG_LIST_DCE_BASE() \
89 : .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
90 : .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
91 :
92 : #if defined(CONFIG_DRM_AMD_DC_SI)
93 : #define CLK_COMMON_REG_LIST_DCE60_BASE() \
94 : SR(DENTIST_DISPCLK_CNTL)
95 : #endif
96 :
97 : #define CLK_COMMON_REG_LIST_DCN_BASE() \
98 : SR(DENTIST_DISPCLK_CNTL)
99 :
100 : #define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \
101 : .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \
102 : .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \
103 : .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67
104 :
105 : #define CLK_COMMON_REG_LIST_DCN_201() \
106 : SR(DENTIST_DISPCLK_CNTL), \
107 : CLK_SRI(CLK4_CLK_PLL_REQ, CLK4, 0), \
108 : CLK_SRI(CLK4_CLK2_CURRENT_CNT, CLK4, 0)
109 :
110 : #define CLK_REG_LIST_NV10() \
111 : SR(DENTIST_DISPCLK_CNTL), \
112 : CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
113 : CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
114 :
115 : #define CLK_REG_LIST_DCN3() \
116 : CLK_COMMON_REG_LIST_DCN_BASE(), \
117 : CLK_SRI(CLK0_CLK_PLL_REQ, CLK02, 0), \
118 : CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0)
119 :
120 : #define CLK_SF(reg_name, field_name, post_fix)\
121 : .field_name = reg_name ## __ ## field_name ## post_fix
122 :
123 : #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
124 : CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
125 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
126 :
127 : #if defined(CONFIG_DRM_AMD_DC_SI)
128 : #define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
129 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
130 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
131 : #endif
132 :
133 : #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
134 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
135 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
136 :
137 : #define CLK_MASK_SH_LIST_RV1(mask_sh) \
138 : CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
139 : CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\
140 : CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
141 : CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
142 :
143 : #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
144 : CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
145 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
146 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh)
147 :
148 : #define CLK_MASK_SH_LIST_NV10(mask_sh) \
149 : CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
150 : CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
151 : CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
152 :
153 : #define CLK_COMMON_MASK_SH_LIST_DCN201_BASE(mask_sh) \
154 : CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
155 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
156 : CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\
157 : CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh)
158 :
159 : #define CLK_REG_LIST_DCN32() \
160 : SR(DENTIST_DISPCLK_CNTL), \
161 : CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \
162 : CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \
163 : CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
164 : CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
165 : CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
166 : CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)
167 :
168 : #define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
169 : CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
170 : CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\
171 : CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh)
172 :
173 : #define CLK_REG_LIST_DCN321() \
174 : SR(DENTIST_DISPCLK_CNTL), \
175 : CLK_SR_DCN321(CLK0_CLK_PLL_REQ, CLK01, 0), \
176 : CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \
177 : CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \
178 : CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \
179 : CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \
180 : CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0)
181 :
182 : #define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \
183 : CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
184 : CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\
185 : CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh)
186 :
187 : #define CLK_REG_FIELD_LIST(type) \
188 : type DPREFCLK_SRC_SEL; \
189 : type DENTIST_DPREFCLK_WDIVIDER; \
190 : type DENTIST_DISPCLK_WDIVIDER; \
191 : type DENTIST_DISPCLK_CHG_DONE;
192 :
193 : /*
194 : ***************************************************************************************
195 : ****************** Clock Manager Private Structures ***********************************
196 : ***************************************************************************************
197 : */
198 : #define CLK20_REG_FIELD_LIST(type) \
199 : type DENTIST_DPPCLK_WDIVIDER; \
200 : type DENTIST_DPPCLK_CHG_DONE; \
201 : type FbMult_int; \
202 : type FbMult_frac;
203 :
204 : #define VBIOS_SMU_REG_FIELD_LIST(type) \
205 : type CONTENT;
206 :
207 : struct clk_mgr_shift {
208 : CLK_REG_FIELD_LIST(uint8_t)
209 : CLK20_REG_FIELD_LIST(uint8_t)
210 : VBIOS_SMU_REG_FIELD_LIST(uint32_t)
211 : };
212 :
213 : struct clk_mgr_mask {
214 : CLK_REG_FIELD_LIST(uint32_t)
215 : CLK20_REG_FIELD_LIST(uint32_t)
216 : VBIOS_SMU_REG_FIELD_LIST(uint32_t)
217 : };
218 :
219 : struct clk_mgr_registers {
220 : uint32_t DPREFCLK_CNTL;
221 : uint32_t DENTIST_DISPCLK_CNTL;
222 : uint32_t CLK4_CLK2_CURRENT_CNT;
223 : uint32_t CLK4_CLK_PLL_REQ;
224 :
225 : uint32_t CLK3_CLK2_DFS_CNTL;
226 : uint32_t CLK3_CLK_PLL_REQ;
227 :
228 : uint32_t CLK0_CLK2_DFS_CNTL;
229 : uint32_t CLK0_CLK_PLL_REQ;
230 :
231 : uint32_t CLK1_CLK_PLL_REQ;
232 : uint32_t CLK1_CLK0_DFS_CNTL;
233 : uint32_t CLK1_CLK1_DFS_CNTL;
234 : uint32_t CLK1_CLK2_DFS_CNTL;
235 : uint32_t CLK1_CLK3_DFS_CNTL;
236 : uint32_t CLK1_CLK4_DFS_CNTL;
237 :
238 : uint32_t CLK0_CLK0_DFS_CNTL;
239 : uint32_t CLK0_CLK1_DFS_CNTL;
240 : uint32_t CLK0_CLK3_DFS_CNTL;
241 : uint32_t CLK0_CLK4_DFS_CNTL;
242 :
243 : uint32_t MP1_SMN_C2PMSG_67;
244 : uint32_t MP1_SMN_C2PMSG_83;
245 : uint32_t MP1_SMN_C2PMSG_91;
246 : };
247 :
248 : enum clock_type {
249 : clock_type_dispclk = 1,
250 : clock_type_dcfclk,
251 : clock_type_socclk,
252 : clock_type_pixelclk,
253 : clock_type_phyclk,
254 : clock_type_dppclk,
255 : clock_type_fclk,
256 : clock_type_dcfdsclk,
257 : clock_type_dscclk,
258 : clock_type_uclk,
259 : clock_type_dramclk,
260 : };
261 :
262 :
263 : struct state_dependent_clocks {
264 : int display_clk_khz;
265 : int pixel_clk_khz;
266 : };
267 :
268 : struct clk_mgr_internal {
269 : struct clk_mgr base;
270 : int smu_ver;
271 : struct pp_smu_funcs *pp_smu;
272 : struct clk_mgr_internal_funcs *funcs;
273 :
274 : struct dccg *dccg;
275 :
276 : /*
277 : * For backwards compatbility with previous implementation
278 : * TODO: remove these after everything transitions to new pattern
279 : * Rationale is that clk registers change a lot across DCE versions
280 : * and a shared data structure doesn't really make sense.
281 : */
282 : const struct clk_mgr_registers *regs;
283 : const struct clk_mgr_shift *clk_mgr_shift;
284 : const struct clk_mgr_mask *clk_mgr_mask;
285 :
286 : struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
287 :
288 : /*TODO: figure out which of the below fields should be here vs in asic specific portion */
289 : /* Cache the status of DFS-bypass feature*/
290 : bool dfs_bypass_enabled;
291 : /* True if the DFS-bypass feature is enabled and active. */
292 : bool dfs_bypass_active;
293 :
294 : uint32_t dfs_ref_freq_khz;
295 : /*
296 : * Cache the display clock returned by VBIOS if DFS-bypass is enabled.
297 : * This is basically "Crystal Frequency In KHz" (XTALIN) frequency
298 : */
299 : int dfs_bypass_disp_clk;
300 :
301 : /**
302 : * @ss_on_dprefclk:
303 : *
304 : * True if spread spectrum is enabled on the DP ref clock.
305 : */
306 : bool ss_on_dprefclk;
307 :
308 : /**
309 : * @xgmi_enabled:
310 : *
311 : * True if xGMI is enabled. On VG20, both audio and display clocks need
312 : * to be adjusted with the WAFL link's SS info if xGMI is enabled.
313 : */
314 : bool xgmi_enabled;
315 :
316 : /**
317 : * @dprefclk_ss_percentage:
318 : *
319 : * DPREFCLK SS percentage (if down-spread enabled).
320 : *
321 : * Note that if XGMI is enabled, the SS info (percentage and divider)
322 : * from the WAFL link is used instead. This is decided during
323 : * dce_clk_mgr initialization.
324 : */
325 : int dprefclk_ss_percentage;
326 :
327 : /**
328 : * @dprefclk_ss_divider:
329 : *
330 : * DPREFCLK SS percentage Divider (100 or 1000).
331 : */
332 : int dprefclk_ss_divider;
333 :
334 : enum dm_pp_clocks_state max_clks_state;
335 : enum dm_pp_clocks_state cur_min_clks_state;
336 : bool periodic_retraining_disabled;
337 :
338 : unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
339 :
340 : bool smu_present;
341 : void *wm_range_table;
342 : long long wm_range_table_addr;
343 : };
344 :
345 : struct clk_mgr_internal_funcs {
346 : int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
347 : int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
348 : };
349 :
350 :
351 : /*
352 : ***************************************************************************************
353 : ****************** Clock Manager Level Helper functions *******************************
354 : ***************************************************************************************
355 : */
356 :
357 :
358 : static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
359 : {
360 0 : return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
361 : }
362 :
363 : static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
364 : {
365 0 : if (cur_support != calc_support) {
366 0 : if (calc_support && safe_to_lower)
367 : return true;
368 0 : else if (!calc_support && !safe_to_lower)
369 : return true;
370 : }
371 :
372 : return false;
373 : }
374 :
375 : static inline int khz_to_mhz_ceil(int khz)
376 : {
377 0 : return (khz + 999) / 1000;
378 : }
379 :
380 : int clk_mgr_helper_get_active_display_cnt(
381 : struct dc *dc,
382 : struct dc_state *context);
383 :
384 : int clk_mgr_helper_get_active_plane_cnt(
385 : struct dc *dc,
386 : struct dc_state *context);
387 :
388 :
389 :
390 : #endif //__DAL_CLK_MGR_INTERNAL_H__
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