Line data Source code
1 : /*
2 : * Copyright 2012-15 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dm_services.h"
27 :
28 : #include "include/logger_interface.h"
29 :
30 : #include "irq_service_dce110.h"
31 :
32 : #include "dce/dce_11_0_d.h"
33 : #include "dce/dce_11_0_sh_mask.h"
34 :
35 : #include "ivsrcid/ivsrcid_vislands30.h"
36 :
37 : #include "dc.h"
38 : #include "core_types.h"
39 : #define DC_LOGGER \
40 : irq_service->ctx->logger
41 :
42 0 : static bool hpd_ack(struct irq_service *irq_service,
43 : const struct irq_source_info *info)
44 : {
45 0 : uint32_t addr = info->status_reg;
46 0 : uint32_t value = dm_read_reg(irq_service->ctx, addr);
47 0 : uint32_t current_status = get_reg_field_value(value,
48 : DC_HPD_INT_STATUS,
49 : DC_HPD_SENSE_DELAYED);
50 :
51 0 : dal_irq_service_ack_generic(irq_service, info);
52 :
53 0 : value = dm_read_reg(irq_service->ctx, info->enable_reg);
54 :
55 0 : set_reg_field_value(value, current_status ? 0 : 1,
56 : DC_HPD_INT_CONTROL,
57 : DC_HPD_INT_POLARITY);
58 :
59 0 : dm_write_reg(irq_service->ctx, info->enable_reg, value);
60 :
61 0 : return true;
62 : }
63 :
64 : static const struct irq_source_info_funcs hpd_irq_info_funcs = {
65 : .set = NULL,
66 : .ack = hpd_ack
67 : };
68 :
69 : static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
70 : .set = NULL,
71 : .ack = NULL
72 : };
73 :
74 : static const struct irq_source_info_funcs pflip_irq_info_funcs = {
75 : .set = NULL,
76 : .ack = NULL
77 : };
78 :
79 : static const struct irq_source_info_funcs vblank_irq_info_funcs = {
80 : .set = dce110_vblank_set,
81 : .ack = NULL
82 : };
83 :
84 : static const struct irq_source_info_funcs vupdate_irq_info_funcs = {
85 : .set = NULL,
86 : .ack = NULL
87 : };
88 :
89 : #define hpd_int_entry(reg_num)\
90 : [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
91 : .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
92 : .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
93 : .enable_value = {\
94 : DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
95 : ~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
96 : },\
97 : .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
98 : .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
99 : .ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
100 : .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
101 : .funcs = &hpd_irq_info_funcs\
102 : }
103 :
104 : #define hpd_rx_int_entry(reg_num)\
105 : [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
106 : .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
107 : .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
108 : .enable_value = {\
109 : DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
110 : ~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
111 : .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
112 : .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
113 : .ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
114 : .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
115 : .funcs = &hpd_rx_irq_info_funcs\
116 : }
117 : #define pflip_int_entry(reg_num)\
118 : [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
119 : .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
120 : .enable_mask =\
121 : GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
122 : .enable_value = {\
123 : GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
124 : ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
125 : .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
126 : .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
127 : .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
128 : .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
129 : .funcs = &pflip_irq_info_funcs\
130 : }
131 :
132 : #define vupdate_int_entry(reg_num)\
133 : [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
134 : .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
135 : .enable_mask =\
136 : CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
137 : .enable_value = {\
138 : CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
139 : ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
140 : .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
141 : .ack_mask =\
142 : CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
143 : .ack_value =\
144 : CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
145 : .funcs = &vupdate_irq_info_funcs\
146 : }
147 :
148 : #define vblank_int_entry(reg_num)\
149 : [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
150 : .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
151 : .enable_mask =\
152 : CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
153 : .enable_value = {\
154 : CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
155 : ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
156 : .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
157 : .ack_mask =\
158 : CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
159 : .ack_value =\
160 : CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
161 : .funcs = &vblank_irq_info_funcs,\
162 : .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
163 : }
164 :
165 : #define dummy_irq_entry() \
166 : {\
167 : .funcs = &dummy_irq_info_funcs\
168 : }
169 :
170 : #define i2c_int_entry(reg_num) \
171 : [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
172 :
173 : #define dp_sink_int_entry(reg_num) \
174 : [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
175 :
176 : #define gpio_pad_int_entry(reg_num) \
177 : [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
178 :
179 : #define dc_underflow_int_entry(reg_num) \
180 : [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
181 :
182 0 : bool dal_irq_service_dummy_set(struct irq_service *irq_service,
183 : const struct irq_source_info *info,
184 : bool enable)
185 : {
186 0 : DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n",
187 : __func__, info->src_id, info->ext_id);
188 :
189 0 : return false;
190 : }
191 :
192 0 : bool dal_irq_service_dummy_ack(struct irq_service *irq_service,
193 : const struct irq_source_info *info)
194 : {
195 0 : DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n",
196 : __func__, info->src_id, info->ext_id);
197 :
198 0 : return false;
199 : }
200 :
201 :
202 0 : bool dce110_vblank_set(struct irq_service *irq_service,
203 : const struct irq_source_info *info,
204 : bool enable)
205 : {
206 0 : struct dc_context *dc_ctx = irq_service->ctx;
207 0 : struct dc *dc = irq_service->ctx->dc;
208 0 : enum dc_irq_source dal_irq_src =
209 0 : dc_interrupt_to_irq_source(irq_service->ctx->dc,
210 : info->src_id,
211 : info->ext_id);
212 0 : uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
213 :
214 0 : struct timing_generator *tg =
215 0 : dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
216 :
217 0 : if (enable) {
218 0 : if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
219 0 : DC_ERROR("Failed to get VBLANK!\n");
220 0 : return false;
221 : }
222 : }
223 :
224 0 : dal_irq_service_set_generic(irq_service, info, enable);
225 0 : return true;
226 : }
227 :
228 : static const struct irq_source_info_funcs dummy_irq_info_funcs = {
229 : .set = dal_irq_service_dummy_set,
230 : .ack = dal_irq_service_dummy_ack
231 : };
232 :
233 : static const struct irq_source_info
234 : irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
235 : [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
236 : hpd_int_entry(0),
237 : hpd_int_entry(1),
238 : hpd_int_entry(2),
239 : hpd_int_entry(3),
240 : hpd_int_entry(4),
241 : hpd_int_entry(5),
242 : hpd_rx_int_entry(0),
243 : hpd_rx_int_entry(1),
244 : hpd_rx_int_entry(2),
245 : hpd_rx_int_entry(3),
246 : hpd_rx_int_entry(4),
247 : hpd_rx_int_entry(5),
248 : i2c_int_entry(1),
249 : i2c_int_entry(2),
250 : i2c_int_entry(3),
251 : i2c_int_entry(4),
252 : i2c_int_entry(5),
253 : i2c_int_entry(6),
254 : dp_sink_int_entry(1),
255 : dp_sink_int_entry(2),
256 : dp_sink_int_entry(3),
257 : dp_sink_int_entry(4),
258 : dp_sink_int_entry(5),
259 : dp_sink_int_entry(6),
260 : [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
261 : pflip_int_entry(0),
262 : pflip_int_entry(1),
263 : pflip_int_entry(2),
264 : pflip_int_entry(3),
265 : pflip_int_entry(4),
266 : pflip_int_entry(5),
267 : [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
268 : gpio_pad_int_entry(0),
269 : gpio_pad_int_entry(1),
270 : gpio_pad_int_entry(2),
271 : gpio_pad_int_entry(3),
272 : gpio_pad_int_entry(4),
273 : gpio_pad_int_entry(5),
274 : gpio_pad_int_entry(6),
275 : gpio_pad_int_entry(7),
276 : gpio_pad_int_entry(8),
277 : gpio_pad_int_entry(9),
278 : gpio_pad_int_entry(10),
279 : gpio_pad_int_entry(11),
280 : gpio_pad_int_entry(12),
281 : gpio_pad_int_entry(13),
282 : gpio_pad_int_entry(14),
283 : gpio_pad_int_entry(15),
284 : gpio_pad_int_entry(16),
285 : gpio_pad_int_entry(17),
286 : gpio_pad_int_entry(18),
287 : gpio_pad_int_entry(19),
288 : gpio_pad_int_entry(20),
289 : gpio_pad_int_entry(21),
290 : gpio_pad_int_entry(22),
291 : gpio_pad_int_entry(23),
292 : gpio_pad_int_entry(24),
293 : gpio_pad_int_entry(25),
294 : gpio_pad_int_entry(26),
295 : gpio_pad_int_entry(27),
296 : gpio_pad_int_entry(28),
297 : gpio_pad_int_entry(29),
298 : gpio_pad_int_entry(30),
299 : dc_underflow_int_entry(1),
300 : dc_underflow_int_entry(2),
301 : dc_underflow_int_entry(3),
302 : dc_underflow_int_entry(4),
303 : dc_underflow_int_entry(5),
304 : dc_underflow_int_entry(6),
305 : [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
306 : [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
307 : vupdate_int_entry(0),
308 : vupdate_int_entry(1),
309 : vupdate_int_entry(2),
310 : vupdate_int_entry(3),
311 : vupdate_int_entry(4),
312 : vupdate_int_entry(5),
313 : vblank_int_entry(0),
314 : vblank_int_entry(1),
315 : vblank_int_entry(2),
316 : vblank_int_entry(3),
317 : vblank_int_entry(4),
318 : vblank_int_entry(5),
319 :
320 : };
321 :
322 0 : enum dc_irq_source to_dal_irq_source_dce110(
323 : struct irq_service *irq_service,
324 : uint32_t src_id,
325 : uint32_t ext_id)
326 : {
327 0 : switch (src_id) {
328 : case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
329 : return DC_IRQ_SOURCE_VBLANK1;
330 : case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0:
331 0 : return DC_IRQ_SOURCE_VBLANK2;
332 : case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0:
333 0 : return DC_IRQ_SOURCE_VBLANK3;
334 : case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0:
335 0 : return DC_IRQ_SOURCE_VBLANK4;
336 : case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0:
337 0 : return DC_IRQ_SOURCE_VBLANK5;
338 : case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0:
339 0 : return DC_IRQ_SOURCE_VBLANK6;
340 : case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
341 0 : return DC_IRQ_SOURCE_VUPDATE1;
342 : case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
343 0 : return DC_IRQ_SOURCE_VUPDATE2;
344 : case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
345 0 : return DC_IRQ_SOURCE_VUPDATE3;
346 : case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
347 0 : return DC_IRQ_SOURCE_VUPDATE4;
348 : case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
349 0 : return DC_IRQ_SOURCE_VUPDATE5;
350 : case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
351 0 : return DC_IRQ_SOURCE_VUPDATE6;
352 : case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
353 0 : return DC_IRQ_SOURCE_PFLIP1;
354 : case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
355 0 : return DC_IRQ_SOURCE_PFLIP2;
356 : case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
357 0 : return DC_IRQ_SOURCE_PFLIP3;
358 : case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
359 0 : return DC_IRQ_SOURCE_PFLIP4;
360 : case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
361 0 : return DC_IRQ_SOURCE_PFLIP5;
362 : case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
363 0 : return DC_IRQ_SOURCE_PFLIP6;
364 :
365 : case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
366 : /* generic src_id for all HPD and HPDRX interrupts */
367 : switch (ext_id) {
368 : case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
369 : return DC_IRQ_SOURCE_HPD1;
370 : case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
371 : return DC_IRQ_SOURCE_HPD2;
372 : case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
373 : return DC_IRQ_SOURCE_HPD3;
374 : case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
375 : return DC_IRQ_SOURCE_HPD4;
376 : case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
377 : return DC_IRQ_SOURCE_HPD5;
378 : case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
379 : return DC_IRQ_SOURCE_HPD6;
380 : case VISLANDS30_IV_EXTID_HPD_RX_A:
381 : return DC_IRQ_SOURCE_HPD1RX;
382 : case VISLANDS30_IV_EXTID_HPD_RX_B:
383 : return DC_IRQ_SOURCE_HPD2RX;
384 : case VISLANDS30_IV_EXTID_HPD_RX_C:
385 : return DC_IRQ_SOURCE_HPD3RX;
386 : case VISLANDS30_IV_EXTID_HPD_RX_D:
387 : return DC_IRQ_SOURCE_HPD4RX;
388 : case VISLANDS30_IV_EXTID_HPD_RX_E:
389 : return DC_IRQ_SOURCE_HPD5RX;
390 : case VISLANDS30_IV_EXTID_HPD_RX_F:
391 : return DC_IRQ_SOURCE_HPD6RX;
392 : default:
393 : return DC_IRQ_SOURCE_INVALID;
394 : }
395 : break;
396 :
397 : default:
398 0 : return DC_IRQ_SOURCE_INVALID;
399 : }
400 : }
401 :
402 : static const struct irq_service_funcs irq_service_funcs_dce110 = {
403 : .to_dal_irq_source = to_dal_irq_source_dce110
404 : };
405 :
406 : static void dce110_irq_construct(struct irq_service *irq_service,
407 : struct irq_service_init_data *init_data)
408 : {
409 0 : dal_irq_service_construct(irq_service, init_data);
410 :
411 0 : irq_service->info = irq_source_info_dce110;
412 0 : irq_service->funcs = &irq_service_funcs_dce110;
413 : }
414 :
415 : struct irq_service *
416 0 : dal_irq_service_dce110_create(struct irq_service_init_data *init_data)
417 : {
418 0 : struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
419 : GFP_KERNEL);
420 :
421 0 : if (!irq_service)
422 : return NULL;
423 :
424 0 : dce110_irq_construct(irq_service, init_data);
425 0 : return irq_service;
426 : }
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