Line data Source code
1 : /*
2 : * Copyright 2012-15 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dm_services.h"
27 :
28 : #include "include/logger_interface.h"
29 :
30 : #include "irq_service_dce120.h"
31 : #include "../dce110/irq_service_dce110.h"
32 :
33 : #include "dce/dce_12_0_offset.h"
34 : #include "dce/dce_12_0_sh_mask.h"
35 : #include "soc15_hw_ip.h"
36 : #include "vega10_ip_offset.h"
37 :
38 : #include "ivsrcid/ivsrcid_vislands30.h"
39 :
40 0 : static bool hpd_ack(
41 : struct irq_service *irq_service,
42 : const struct irq_source_info *info)
43 : {
44 0 : uint32_t addr = info->status_reg;
45 0 : uint32_t value = dm_read_reg(irq_service->ctx, addr);
46 0 : uint32_t current_status =
47 : get_reg_field_value(
48 : value,
49 : HPD0_DC_HPD_INT_STATUS,
50 : DC_HPD_SENSE_DELAYED);
51 :
52 0 : dal_irq_service_ack_generic(irq_service, info);
53 :
54 0 : value = dm_read_reg(irq_service->ctx, info->enable_reg);
55 :
56 0 : set_reg_field_value(
57 : value,
58 : current_status ? 0 : 1,
59 : HPD0_DC_HPD_INT_CONTROL,
60 : DC_HPD_INT_POLARITY);
61 :
62 0 : dm_write_reg(irq_service->ctx, info->enable_reg, value);
63 :
64 0 : return true;
65 : }
66 :
67 : static const struct irq_source_info_funcs hpd_irq_info_funcs = {
68 : .set = NULL,
69 : .ack = hpd_ack
70 : };
71 :
72 : static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
73 : .set = NULL,
74 : .ack = NULL
75 : };
76 :
77 : static const struct irq_source_info_funcs pflip_irq_info_funcs = {
78 : .set = NULL,
79 : .ack = NULL
80 : };
81 :
82 : static const struct irq_source_info_funcs vblank_irq_info_funcs = {
83 : .set = dce110_vblank_set,
84 : .ack = NULL
85 : };
86 :
87 : static const struct irq_source_info_funcs vupdate_irq_info_funcs = {
88 : .set = NULL,
89 : .ack = NULL
90 : };
91 :
92 : #define BASE_INNER(seg) \
93 : DCE_BASE__INST0_SEG ## seg
94 :
95 : #define BASE(seg) \
96 : BASE_INNER(seg)
97 :
98 : #define SRI(reg_name, block, id)\
99 : BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
100 : mm ## block ## id ## _ ## reg_name
101 :
102 :
103 : #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
104 : .enable_reg = SRI(reg1, block, reg_num),\
105 : .enable_mask = \
106 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
107 : .enable_value = {\
108 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
109 : ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
110 : },\
111 : .ack_reg = SRI(reg2, block, reg_num),\
112 : .ack_mask = \
113 : block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
114 : .ack_value = \
115 : block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
116 :
117 : #define hpd_int_entry(reg_num)\
118 : [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
119 : IRQ_REG_ENTRY(HPD, reg_num,\
120 : DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
121 : DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
122 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
123 : .funcs = &hpd_irq_info_funcs\
124 : }
125 :
126 : #define hpd_rx_int_entry(reg_num)\
127 : [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
128 : IRQ_REG_ENTRY(HPD, reg_num,\
129 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
130 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
131 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
132 : .funcs = &hpd_rx_irq_info_funcs\
133 : }
134 : #define pflip_int_entry(reg_num)\
135 : [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
136 : IRQ_REG_ENTRY(DCP, reg_num, \
137 : GRPH_INTERRUPT_CONTROL, GRPH_PFLIP_INT_MASK, \
138 : GRPH_INTERRUPT_STATUS, GRPH_PFLIP_INT_CLEAR),\
139 : .status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
140 : .funcs = &pflip_irq_info_funcs\
141 : }
142 :
143 : #define vupdate_int_entry(reg_num)\
144 : [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
145 : IRQ_REG_ENTRY(CRTC, reg_num,\
146 : CRTC_INTERRUPT_CONTROL, CRTC_V_UPDATE_INT_MSK,\
147 : CRTC_V_UPDATE_INT_STATUS, CRTC_V_UPDATE_INT_CLEAR),\
148 : .funcs = &vupdate_irq_info_funcs\
149 : }
150 :
151 : #define vblank_int_entry(reg_num)\
152 : [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
153 : IRQ_REG_ENTRY(CRTC, reg_num,\
154 : CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\
155 : CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\
156 : .funcs = &vblank_irq_info_funcs,\
157 : .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
158 : }
159 :
160 : #define dummy_irq_entry() \
161 : {\
162 : .funcs = &dummy_irq_info_funcs\
163 : }
164 :
165 : #define i2c_int_entry(reg_num) \
166 : [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
167 :
168 : #define dp_sink_int_entry(reg_num) \
169 : [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
170 :
171 : #define gpio_pad_int_entry(reg_num) \
172 : [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
173 :
174 : #define dc_underflow_int_entry(reg_num) \
175 : [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
176 :
177 : static const struct irq_source_info_funcs dummy_irq_info_funcs = {
178 : .set = dal_irq_service_dummy_set,
179 : .ack = dal_irq_service_dummy_ack
180 : };
181 :
182 : static const struct irq_source_info
183 : irq_source_info_dce120[DAL_IRQ_SOURCES_NUMBER] = {
184 : [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
185 : hpd_int_entry(0),
186 : hpd_int_entry(1),
187 : hpd_int_entry(2),
188 : hpd_int_entry(3),
189 : hpd_int_entry(4),
190 : hpd_int_entry(5),
191 : hpd_rx_int_entry(0),
192 : hpd_rx_int_entry(1),
193 : hpd_rx_int_entry(2),
194 : hpd_rx_int_entry(3),
195 : hpd_rx_int_entry(4),
196 : hpd_rx_int_entry(5),
197 : i2c_int_entry(1),
198 : i2c_int_entry(2),
199 : i2c_int_entry(3),
200 : i2c_int_entry(4),
201 : i2c_int_entry(5),
202 : i2c_int_entry(6),
203 : dp_sink_int_entry(1),
204 : dp_sink_int_entry(2),
205 : dp_sink_int_entry(3),
206 : dp_sink_int_entry(4),
207 : dp_sink_int_entry(5),
208 : dp_sink_int_entry(6),
209 : [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
210 : pflip_int_entry(0),
211 : pflip_int_entry(1),
212 : pflip_int_entry(2),
213 : pflip_int_entry(3),
214 : pflip_int_entry(4),
215 : pflip_int_entry(5),
216 : [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
217 : gpio_pad_int_entry(0),
218 : gpio_pad_int_entry(1),
219 : gpio_pad_int_entry(2),
220 : gpio_pad_int_entry(3),
221 : gpio_pad_int_entry(4),
222 : gpio_pad_int_entry(5),
223 : gpio_pad_int_entry(6),
224 : gpio_pad_int_entry(7),
225 : gpio_pad_int_entry(8),
226 : gpio_pad_int_entry(9),
227 : gpio_pad_int_entry(10),
228 : gpio_pad_int_entry(11),
229 : gpio_pad_int_entry(12),
230 : gpio_pad_int_entry(13),
231 : gpio_pad_int_entry(14),
232 : gpio_pad_int_entry(15),
233 : gpio_pad_int_entry(16),
234 : gpio_pad_int_entry(17),
235 : gpio_pad_int_entry(18),
236 : gpio_pad_int_entry(19),
237 : gpio_pad_int_entry(20),
238 : gpio_pad_int_entry(21),
239 : gpio_pad_int_entry(22),
240 : gpio_pad_int_entry(23),
241 : gpio_pad_int_entry(24),
242 : gpio_pad_int_entry(25),
243 : gpio_pad_int_entry(26),
244 : gpio_pad_int_entry(27),
245 : gpio_pad_int_entry(28),
246 : gpio_pad_int_entry(29),
247 : gpio_pad_int_entry(30),
248 : dc_underflow_int_entry(1),
249 : dc_underflow_int_entry(2),
250 : dc_underflow_int_entry(3),
251 : dc_underflow_int_entry(4),
252 : dc_underflow_int_entry(5),
253 : dc_underflow_int_entry(6),
254 : [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
255 : [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
256 : vupdate_int_entry(0),
257 : vupdate_int_entry(1),
258 : vupdate_int_entry(2),
259 : vupdate_int_entry(3),
260 : vupdate_int_entry(4),
261 : vupdate_int_entry(5),
262 : vblank_int_entry(0),
263 : vblank_int_entry(1),
264 : vblank_int_entry(2),
265 : vblank_int_entry(3),
266 : vblank_int_entry(4),
267 : vblank_int_entry(5),
268 : };
269 :
270 : static const struct irq_service_funcs irq_service_funcs_dce120 = {
271 : .to_dal_irq_source = to_dal_irq_source_dce110
272 : };
273 :
274 : static void dce120_irq_construct(
275 : struct irq_service *irq_service,
276 : struct irq_service_init_data *init_data)
277 : {
278 0 : dal_irq_service_construct(irq_service, init_data);
279 :
280 0 : irq_service->info = irq_source_info_dce120;
281 0 : irq_service->funcs = &irq_service_funcs_dce120;
282 : }
283 :
284 0 : struct irq_service *dal_irq_service_dce120_create(
285 : struct irq_service_init_data *init_data)
286 : {
287 0 : struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
288 : GFP_KERNEL);
289 :
290 0 : if (!irq_service)
291 : return NULL;
292 :
293 0 : dce120_irq_construct(irq_service, init_data);
294 0 : return irq_service;
295 : }
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