Line data Source code
1 : /*
2 : * Copyright 2012-15 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dm_services.h"
27 :
28 : #include "include/logger_interface.h"
29 :
30 : #include "../dce110/irq_service_dce110.h"
31 :
32 : #include "dcn/dcn_1_0_offset.h"
33 : #include "dcn/dcn_1_0_sh_mask.h"
34 : #include "soc15_hw_ip.h"
35 : #include "vega10_ip_offset.h"
36 :
37 : #include "irq_service_dcn10.h"
38 :
39 : #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
40 :
41 0 : static enum dc_irq_source to_dal_irq_source_dcn10(struct irq_service *irq_service,
42 : uint32_t src_id,
43 : uint32_t ext_id)
44 : {
45 0 : switch (src_id) {
46 : case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
47 : return DC_IRQ_SOURCE_VBLANK1;
48 : case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
49 0 : return DC_IRQ_SOURCE_VBLANK2;
50 : case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
51 0 : return DC_IRQ_SOURCE_VBLANK3;
52 : case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
53 0 : return DC_IRQ_SOURCE_VBLANK4;
54 : case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
55 0 : return DC_IRQ_SOURCE_VBLANK5;
56 : case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
57 0 : return DC_IRQ_SOURCE_VBLANK6;
58 : case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
59 0 : return DC_IRQ_SOURCE_DC1_VLINE0;
60 : case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
61 0 : return DC_IRQ_SOURCE_DC2_VLINE0;
62 : case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
63 0 : return DC_IRQ_SOURCE_DC3_VLINE0;
64 : case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
65 0 : return DC_IRQ_SOURCE_DC4_VLINE0;
66 : case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
67 0 : return DC_IRQ_SOURCE_DC5_VLINE0;
68 : case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
69 0 : return DC_IRQ_SOURCE_DC6_VLINE0;
70 : case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
71 0 : return DC_IRQ_SOURCE_VUPDATE1;
72 : case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
73 0 : return DC_IRQ_SOURCE_VUPDATE2;
74 : case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
75 0 : return DC_IRQ_SOURCE_VUPDATE3;
76 : case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
77 0 : return DC_IRQ_SOURCE_VUPDATE4;
78 : case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
79 0 : return DC_IRQ_SOURCE_VUPDATE5;
80 : case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
81 0 : return DC_IRQ_SOURCE_VUPDATE6;
82 : case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
83 0 : return DC_IRQ_SOURCE_PFLIP1;
84 : case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
85 0 : return DC_IRQ_SOURCE_PFLIP2;
86 : case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
87 0 : return DC_IRQ_SOURCE_PFLIP3;
88 : case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
89 0 : return DC_IRQ_SOURCE_PFLIP4;
90 : case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
91 0 : return DC_IRQ_SOURCE_PFLIP5;
92 : case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
93 0 : return DC_IRQ_SOURCE_PFLIP6;
94 :
95 : case DCN_1_0__SRCID__DC_HPD1_INT:
96 : /* generic src_id for all HPD and HPDRX interrupts */
97 : switch (ext_id) {
98 : case DCN_1_0__CTXID__DC_HPD1_INT:
99 : return DC_IRQ_SOURCE_HPD1;
100 : case DCN_1_0__CTXID__DC_HPD2_INT:
101 : return DC_IRQ_SOURCE_HPD2;
102 : case DCN_1_0__CTXID__DC_HPD3_INT:
103 : return DC_IRQ_SOURCE_HPD3;
104 : case DCN_1_0__CTXID__DC_HPD4_INT:
105 : return DC_IRQ_SOURCE_HPD4;
106 : case DCN_1_0__CTXID__DC_HPD5_INT:
107 : return DC_IRQ_SOURCE_HPD5;
108 : case DCN_1_0__CTXID__DC_HPD6_INT:
109 : return DC_IRQ_SOURCE_HPD6;
110 : case DCN_1_0__CTXID__DC_HPD1_RX_INT:
111 : return DC_IRQ_SOURCE_HPD1RX;
112 : case DCN_1_0__CTXID__DC_HPD2_RX_INT:
113 : return DC_IRQ_SOURCE_HPD2RX;
114 : case DCN_1_0__CTXID__DC_HPD3_RX_INT:
115 : return DC_IRQ_SOURCE_HPD3RX;
116 : case DCN_1_0__CTXID__DC_HPD4_RX_INT:
117 : return DC_IRQ_SOURCE_HPD4RX;
118 : case DCN_1_0__CTXID__DC_HPD5_RX_INT:
119 : return DC_IRQ_SOURCE_HPD5RX;
120 : case DCN_1_0__CTXID__DC_HPD6_RX_INT:
121 : return DC_IRQ_SOURCE_HPD6RX;
122 : default:
123 : return DC_IRQ_SOURCE_INVALID;
124 : }
125 : break;
126 :
127 : default:
128 0 : return DC_IRQ_SOURCE_INVALID;
129 : }
130 : }
131 :
132 0 : static bool hpd_ack(
133 : struct irq_service *irq_service,
134 : const struct irq_source_info *info)
135 : {
136 0 : uint32_t addr = info->status_reg;
137 0 : uint32_t value = dm_read_reg(irq_service->ctx, addr);
138 0 : uint32_t current_status =
139 : get_reg_field_value(
140 : value,
141 : HPD0_DC_HPD_INT_STATUS,
142 : DC_HPD_SENSE_DELAYED);
143 :
144 0 : dal_irq_service_ack_generic(irq_service, info);
145 :
146 0 : value = dm_read_reg(irq_service->ctx, info->enable_reg);
147 :
148 0 : set_reg_field_value(
149 : value,
150 : current_status ? 0 : 1,
151 : HPD0_DC_HPD_INT_CONTROL,
152 : DC_HPD_INT_POLARITY);
153 :
154 0 : dm_write_reg(irq_service->ctx, info->enable_reg, value);
155 :
156 0 : return true;
157 : }
158 :
159 : static const struct irq_source_info_funcs hpd_irq_info_funcs = {
160 : .set = NULL,
161 : .ack = hpd_ack
162 : };
163 :
164 : static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
165 : .set = NULL,
166 : .ack = NULL
167 : };
168 :
169 : static const struct irq_source_info_funcs pflip_irq_info_funcs = {
170 : .set = NULL,
171 : .ack = NULL
172 : };
173 :
174 : static const struct irq_source_info_funcs vblank_irq_info_funcs = {
175 : .set = NULL,
176 : .ack = NULL
177 : };
178 :
179 : static const struct irq_source_info_funcs vline0_irq_info_funcs = {
180 : .set = NULL,
181 : .ack = NULL
182 : };
183 :
184 : static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
185 : .set = NULL,
186 : .ack = NULL
187 : };
188 :
189 : #define BASE_INNER(seg) \
190 : DCE_BASE__INST0_SEG ## seg
191 :
192 : #define BASE(seg) \
193 : BASE_INNER(seg)
194 :
195 : #define SRI(reg_name, block, id)\
196 : BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
197 : mm ## block ## id ## _ ## reg_name
198 :
199 :
200 : #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
201 : .enable_reg = SRI(reg1, block, reg_num),\
202 : .enable_mask = \
203 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
204 : .enable_value = {\
205 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
206 : ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
207 : },\
208 : .ack_reg = SRI(reg2, block, reg_num),\
209 : .ack_mask = \
210 : block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
211 : .ack_value = \
212 : block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
213 :
214 : #define hpd_int_entry(reg_num)\
215 : [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
216 : IRQ_REG_ENTRY(HPD, reg_num,\
217 : DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
218 : DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
219 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
220 : .funcs = &hpd_irq_info_funcs\
221 : }
222 :
223 : #define hpd_rx_int_entry(reg_num)\
224 : [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
225 : IRQ_REG_ENTRY(HPD, reg_num,\
226 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
227 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
228 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
229 : .funcs = &hpd_rx_irq_info_funcs\
230 : }
231 : #define pflip_int_entry(reg_num)\
232 : [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
233 : IRQ_REG_ENTRY(HUBPREQ, reg_num,\
234 : DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
235 : DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
236 : .funcs = &pflip_irq_info_funcs\
237 : }
238 :
239 : /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
240 : * of DCE's DC_IRQ_SOURCE_VUPDATEx.
241 : */
242 : #define vupdate_no_lock_int_entry(reg_num)\
243 : [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
244 : IRQ_REG_ENTRY(OTG, reg_num,\
245 : OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
246 : OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
247 : .funcs = &vupdate_no_lock_irq_info_funcs\
248 : }
249 :
250 : #define vblank_int_entry(reg_num)\
251 : [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
252 : IRQ_REG_ENTRY(OTG, reg_num,\
253 : OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
254 : OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
255 : .funcs = &vblank_irq_info_funcs\
256 : }
257 :
258 : #define vline0_int_entry(reg_num)\
259 : [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
260 : IRQ_REG_ENTRY(OTG, reg_num,\
261 : OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
262 : OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
263 : .funcs = &vline0_irq_info_funcs\
264 : }
265 :
266 : #define dummy_irq_entry() \
267 : {\
268 : .funcs = &dummy_irq_info_funcs\
269 : }
270 :
271 : #define i2c_int_entry(reg_num) \
272 : [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
273 :
274 : #define dp_sink_int_entry(reg_num) \
275 : [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
276 :
277 : #define gpio_pad_int_entry(reg_num) \
278 : [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
279 :
280 : #define dc_underflow_int_entry(reg_num) \
281 : [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
282 :
283 : static const struct irq_source_info_funcs dummy_irq_info_funcs = {
284 : .set = dal_irq_service_dummy_set,
285 : .ack = dal_irq_service_dummy_ack
286 : };
287 :
288 : static const struct irq_source_info
289 : irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
290 : [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
291 : hpd_int_entry(0),
292 : hpd_int_entry(1),
293 : hpd_int_entry(2),
294 : hpd_int_entry(3),
295 : hpd_int_entry(4),
296 : hpd_int_entry(5),
297 : hpd_rx_int_entry(0),
298 : hpd_rx_int_entry(1),
299 : hpd_rx_int_entry(2),
300 : hpd_rx_int_entry(3),
301 : hpd_rx_int_entry(4),
302 : hpd_rx_int_entry(5),
303 : i2c_int_entry(1),
304 : i2c_int_entry(2),
305 : i2c_int_entry(3),
306 : i2c_int_entry(4),
307 : i2c_int_entry(5),
308 : i2c_int_entry(6),
309 : dp_sink_int_entry(1),
310 : dp_sink_int_entry(2),
311 : dp_sink_int_entry(3),
312 : dp_sink_int_entry(4),
313 : dp_sink_int_entry(5),
314 : dp_sink_int_entry(6),
315 : [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
316 : pflip_int_entry(0),
317 : pflip_int_entry(1),
318 : pflip_int_entry(2),
319 : pflip_int_entry(3),
320 : [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
321 : [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
322 : [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
323 : gpio_pad_int_entry(0),
324 : gpio_pad_int_entry(1),
325 : gpio_pad_int_entry(2),
326 : gpio_pad_int_entry(3),
327 : gpio_pad_int_entry(4),
328 : gpio_pad_int_entry(5),
329 : gpio_pad_int_entry(6),
330 : gpio_pad_int_entry(7),
331 : gpio_pad_int_entry(8),
332 : gpio_pad_int_entry(9),
333 : gpio_pad_int_entry(10),
334 : gpio_pad_int_entry(11),
335 : gpio_pad_int_entry(12),
336 : gpio_pad_int_entry(13),
337 : gpio_pad_int_entry(14),
338 : gpio_pad_int_entry(15),
339 : gpio_pad_int_entry(16),
340 : gpio_pad_int_entry(17),
341 : gpio_pad_int_entry(18),
342 : gpio_pad_int_entry(19),
343 : gpio_pad_int_entry(20),
344 : gpio_pad_int_entry(21),
345 : gpio_pad_int_entry(22),
346 : gpio_pad_int_entry(23),
347 : gpio_pad_int_entry(24),
348 : gpio_pad_int_entry(25),
349 : gpio_pad_int_entry(26),
350 : gpio_pad_int_entry(27),
351 : gpio_pad_int_entry(28),
352 : gpio_pad_int_entry(29),
353 : gpio_pad_int_entry(30),
354 : dc_underflow_int_entry(1),
355 : dc_underflow_int_entry(2),
356 : dc_underflow_int_entry(3),
357 : dc_underflow_int_entry(4),
358 : dc_underflow_int_entry(5),
359 : dc_underflow_int_entry(6),
360 : [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
361 : [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
362 : vupdate_no_lock_int_entry(0),
363 : vupdate_no_lock_int_entry(1),
364 : vupdate_no_lock_int_entry(2),
365 : vupdate_no_lock_int_entry(3),
366 : vupdate_no_lock_int_entry(4),
367 : vupdate_no_lock_int_entry(5),
368 : vblank_int_entry(0),
369 : vblank_int_entry(1),
370 : vblank_int_entry(2),
371 : vblank_int_entry(3),
372 : vblank_int_entry(4),
373 : vblank_int_entry(5),
374 : vline0_int_entry(0),
375 : vline0_int_entry(1),
376 : vline0_int_entry(2),
377 : vline0_int_entry(3),
378 : vline0_int_entry(4),
379 : vline0_int_entry(5),
380 : };
381 :
382 : static const struct irq_service_funcs irq_service_funcs_dcn10 = {
383 : .to_dal_irq_source = to_dal_irq_source_dcn10
384 : };
385 :
386 : static void dcn10_irq_construct(
387 : struct irq_service *irq_service,
388 : struct irq_service_init_data *init_data)
389 : {
390 0 : dal_irq_service_construct(irq_service, init_data);
391 :
392 0 : irq_service->info = irq_source_info_dcn10;
393 0 : irq_service->funcs = &irq_service_funcs_dcn10;
394 : }
395 :
396 0 : struct irq_service *dal_irq_service_dcn10_create(
397 : struct irq_service_init_data *init_data)
398 : {
399 0 : struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
400 : GFP_KERNEL);
401 :
402 0 : if (!irq_service)
403 : return NULL;
404 :
405 0 : dcn10_irq_construct(irq_service, init_data);
406 0 : return irq_service;
407 : }
|
