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1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dm_services.h"
27 :
28 : #include "irq_service_dcn302.h"
29 :
30 : #include "../dce110/irq_service_dce110.h"
31 :
32 : #include "dimgrey_cavefish_ip_offset.h"
33 : #include "dcn/dcn_3_0_0_offset.h"
34 : #include "dcn/dcn_3_0_0_sh_mask.h"
35 :
36 : #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
37 :
38 0 : static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id)
39 : {
40 0 : switch (src_id) {
41 : case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
42 : return DC_IRQ_SOURCE_VBLANK1;
43 : case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
44 0 : return DC_IRQ_SOURCE_VBLANK2;
45 : case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
46 0 : return DC_IRQ_SOURCE_VBLANK3;
47 : case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
48 0 : return DC_IRQ_SOURCE_VBLANK4;
49 : case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
50 0 : return DC_IRQ_SOURCE_VBLANK5;
51 : case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
52 0 : return DC_IRQ_SOURCE_VBLANK6;
53 : case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
54 0 : return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
55 : case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
56 0 : return DC_IRQ_SOURCE_DC1_VLINE0;
57 : case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
58 0 : return DC_IRQ_SOURCE_DC2_VLINE0;
59 : case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
60 0 : return DC_IRQ_SOURCE_DC3_VLINE0;
61 : case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
62 0 : return DC_IRQ_SOURCE_DC4_VLINE0;
63 : case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
64 0 : return DC_IRQ_SOURCE_DC5_VLINE0;
65 : case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
66 0 : return DC_IRQ_SOURCE_DC6_VLINE0;
67 : case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
68 0 : return DC_IRQ_SOURCE_PFLIP1;
69 : case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
70 0 : return DC_IRQ_SOURCE_PFLIP2;
71 : case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
72 0 : return DC_IRQ_SOURCE_PFLIP3;
73 : case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
74 0 : return DC_IRQ_SOURCE_PFLIP4;
75 : case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
76 0 : return DC_IRQ_SOURCE_PFLIP5;
77 : case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
78 0 : return DC_IRQ_SOURCE_PFLIP6;
79 : case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
80 0 : return DC_IRQ_SOURCE_VUPDATE1;
81 : case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
82 0 : return DC_IRQ_SOURCE_VUPDATE2;
83 : case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
84 0 : return DC_IRQ_SOURCE_VUPDATE3;
85 : case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
86 0 : return DC_IRQ_SOURCE_VUPDATE4;
87 : case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
88 0 : return DC_IRQ_SOURCE_VUPDATE5;
89 : case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
90 0 : return DC_IRQ_SOURCE_VUPDATE6;
91 :
92 : case DCN_1_0__SRCID__DC_HPD1_INT:
93 : /* generic src_id for all HPD and HPDRX interrupts */
94 : switch (ext_id) {
95 : case DCN_1_0__CTXID__DC_HPD1_INT:
96 : return DC_IRQ_SOURCE_HPD1;
97 : case DCN_1_0__CTXID__DC_HPD2_INT:
98 : return DC_IRQ_SOURCE_HPD2;
99 : case DCN_1_0__CTXID__DC_HPD3_INT:
100 : return DC_IRQ_SOURCE_HPD3;
101 : case DCN_1_0__CTXID__DC_HPD4_INT:
102 : return DC_IRQ_SOURCE_HPD4;
103 : case DCN_1_0__CTXID__DC_HPD5_INT:
104 : return DC_IRQ_SOURCE_HPD5;
105 : case DCN_1_0__CTXID__DC_HPD6_INT:
106 : return DC_IRQ_SOURCE_HPD6;
107 : case DCN_1_0__CTXID__DC_HPD1_RX_INT:
108 : return DC_IRQ_SOURCE_HPD1RX;
109 : case DCN_1_0__CTXID__DC_HPD2_RX_INT:
110 : return DC_IRQ_SOURCE_HPD2RX;
111 : case DCN_1_0__CTXID__DC_HPD3_RX_INT:
112 : return DC_IRQ_SOURCE_HPD3RX;
113 : case DCN_1_0__CTXID__DC_HPD4_RX_INT:
114 : return DC_IRQ_SOURCE_HPD4RX;
115 : case DCN_1_0__CTXID__DC_HPD5_RX_INT:
116 : return DC_IRQ_SOURCE_HPD5RX;
117 : case DCN_1_0__CTXID__DC_HPD6_RX_INT:
118 : return DC_IRQ_SOURCE_HPD6RX;
119 : default:
120 : return DC_IRQ_SOURCE_INVALID;
121 : }
122 : break;
123 :
124 : default:
125 0 : return DC_IRQ_SOURCE_INVALID;
126 : }
127 : }
128 :
129 0 : static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info)
130 : {
131 0 : uint32_t addr = info->status_reg;
132 0 : uint32_t value = dm_read_reg(irq_service->ctx, addr);
133 0 : uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);
134 :
135 0 : dal_irq_service_ack_generic(irq_service, info);
136 :
137 0 : value = dm_read_reg(irq_service->ctx, info->enable_reg);
138 :
139 0 : set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);
140 :
141 0 : dm_write_reg(irq_service->ctx, info->enable_reg, value);
142 :
143 0 : return true;
144 : }
145 :
146 : static const struct irq_source_info_funcs hpd_irq_info_funcs = {
147 : .set = NULL,
148 : .ack = hpd_ack
149 : };
150 :
151 : static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
152 : .set = NULL,
153 : .ack = NULL
154 : };
155 :
156 : static const struct irq_source_info_funcs pflip_irq_info_funcs = {
157 : .set = NULL,
158 : .ack = NULL
159 : };
160 :
161 : static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
162 : .set = NULL,
163 : .ack = NULL
164 : };
165 :
166 : static const struct irq_source_info_funcs vblank_irq_info_funcs = {
167 : .set = NULL,
168 : .ack = NULL
169 : };
170 :
171 : static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
172 : .set = NULL,
173 : .ack = NULL
174 : };
175 :
176 : static const struct irq_source_info_funcs vline0_irq_info_funcs = {
177 : .set = NULL,
178 : .ack = NULL
179 : };
180 :
181 : #undef BASE_INNER
182 : #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
183 :
184 : /* compile time expand base address. */
185 : #define BASE(seg) BASE_INNER(seg)
186 :
187 : #define SRI(reg_name, block, id)\
188 : BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
189 : mm ## block ## id ## _ ## reg_name
190 :
191 : #define SRI_DMUB(reg_name)\
192 : BASE(mm ## reg_name ## _BASE_IDX) + \
193 : mm ## reg_name
194 :
195 : #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
196 : .enable_reg = SRI(reg1, block, reg_num),\
197 : .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 : .enable_value = {\
199 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 : ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
201 : },\
202 : .ack_reg = SRI(reg2, block, reg_num),\
203 : .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 : .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205 :
206 : #define dmub_trace_int_entry()\
207 : [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
208 : IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
209 : DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
210 : .funcs = &dmub_trace_irq_info_funcs\
211 : }
212 :
213 : #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
214 : .enable_reg = SRI_DMUB(reg1),\
215 : .enable_mask = \
216 : reg1 ## __ ## mask1 ## _MASK,\
217 : .enable_value = {\
218 : reg1 ## __ ## mask1 ## _MASK,\
219 : ~reg1 ## __ ## mask1 ## _MASK \
220 : },\
221 : .ack_reg = SRI_DMUB(reg2),\
222 : .ack_mask = \
223 : reg2 ## __ ## mask2 ## _MASK,\
224 : .ack_value = \
225 : reg2 ## __ ## mask2 ## _MASK \
226 :
227 : #define hpd_int_entry(reg_num)\
228 : [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
229 : IRQ_REG_ENTRY(HPD, reg_num,\
230 : DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
231 : DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
232 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
233 : .funcs = &hpd_irq_info_funcs\
234 : }
235 :
236 : #define hpd_rx_int_entry(reg_num)\
237 : [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
238 : IRQ_REG_ENTRY(HPD, reg_num,\
239 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
240 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
241 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
242 : .funcs = &hpd_rx_irq_info_funcs\
243 : }
244 : #define pflip_int_entry(reg_num)\
245 : [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
246 : IRQ_REG_ENTRY(HUBPREQ, reg_num,\
247 : DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
248 : DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
249 : .funcs = &pflip_irq_info_funcs\
250 : }
251 :
252 : /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
253 : * of DCE's DC_IRQ_SOURCE_VUPDATEx.
254 : */
255 : #define vupdate_no_lock_int_entry(reg_num)\
256 : [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
257 : IRQ_REG_ENTRY(OTG, reg_num,\
258 : OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
259 : OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
260 : .funcs = &vupdate_no_lock_irq_info_funcs\
261 : }
262 :
263 : #define vblank_int_entry(reg_num)\
264 : [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
265 : IRQ_REG_ENTRY(OTG, reg_num,\
266 : OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
267 : OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
268 : .funcs = &vblank_irq_info_funcs\
269 : }
270 :
271 : #define vline0_int_entry(reg_num)\
272 : [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
273 : IRQ_REG_ENTRY(OTG, reg_num,\
274 : OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
275 : OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
276 : .funcs = &vline0_irq_info_funcs\
277 : }
278 :
279 : #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
280 :
281 : #define i2c_int_entry(reg_num) \
282 : [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
283 :
284 : #define dp_sink_int_entry(reg_num) \
285 : [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
286 :
287 : #define gpio_pad_int_entry(reg_num) \
288 : [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
289 :
290 : #define dc_underflow_int_entry(reg_num) \
291 : [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
292 :
293 : static const struct irq_source_info_funcs dummy_irq_info_funcs = {
294 : .set = dal_irq_service_dummy_set,
295 : .ack = dal_irq_service_dummy_ack
296 : };
297 :
298 : static const struct irq_source_info irq_source_info_dcn302[DAL_IRQ_SOURCES_NUMBER] = {
299 : [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
300 : hpd_int_entry(0),
301 : hpd_int_entry(1),
302 : hpd_int_entry(2),
303 : hpd_int_entry(3),
304 : hpd_int_entry(4),
305 : hpd_rx_int_entry(0),
306 : hpd_rx_int_entry(1),
307 : hpd_rx_int_entry(2),
308 : hpd_rx_int_entry(3),
309 : hpd_rx_int_entry(4),
310 : i2c_int_entry(1),
311 : i2c_int_entry(2),
312 : i2c_int_entry(3),
313 : i2c_int_entry(4),
314 : i2c_int_entry(5),
315 : dp_sink_int_entry(1),
316 : dp_sink_int_entry(2),
317 : dp_sink_int_entry(3),
318 : dp_sink_int_entry(4),
319 : dp_sink_int_entry(5),
320 : [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
321 : pflip_int_entry(0),
322 : pflip_int_entry(1),
323 : pflip_int_entry(2),
324 : pflip_int_entry(3),
325 : pflip_int_entry(4),
326 : [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
327 : gpio_pad_int_entry(0),
328 : gpio_pad_int_entry(1),
329 : gpio_pad_int_entry(2),
330 : gpio_pad_int_entry(3),
331 : gpio_pad_int_entry(4),
332 : gpio_pad_int_entry(5),
333 : gpio_pad_int_entry(6),
334 : gpio_pad_int_entry(7),
335 : gpio_pad_int_entry(8),
336 : gpio_pad_int_entry(9),
337 : gpio_pad_int_entry(10),
338 : gpio_pad_int_entry(11),
339 : gpio_pad_int_entry(12),
340 : gpio_pad_int_entry(13),
341 : gpio_pad_int_entry(14),
342 : gpio_pad_int_entry(15),
343 : gpio_pad_int_entry(16),
344 : gpio_pad_int_entry(17),
345 : gpio_pad_int_entry(18),
346 : gpio_pad_int_entry(19),
347 : gpio_pad_int_entry(20),
348 : gpio_pad_int_entry(21),
349 : gpio_pad_int_entry(22),
350 : gpio_pad_int_entry(23),
351 : gpio_pad_int_entry(24),
352 : gpio_pad_int_entry(25),
353 : gpio_pad_int_entry(26),
354 : gpio_pad_int_entry(27),
355 : gpio_pad_int_entry(28),
356 : gpio_pad_int_entry(29),
357 : gpio_pad_int_entry(30),
358 : dc_underflow_int_entry(1),
359 : dc_underflow_int_entry(2),
360 : dc_underflow_int_entry(3),
361 : dc_underflow_int_entry(4),
362 : dc_underflow_int_entry(5),
363 : [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
364 : [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
365 : vupdate_no_lock_int_entry(0),
366 : vupdate_no_lock_int_entry(1),
367 : vupdate_no_lock_int_entry(2),
368 : vupdate_no_lock_int_entry(3),
369 : vupdate_no_lock_int_entry(4),
370 : vblank_int_entry(0),
371 : vblank_int_entry(1),
372 : vblank_int_entry(2),
373 : vblank_int_entry(3),
374 : vblank_int_entry(4),
375 : vline0_int_entry(0),
376 : vline0_int_entry(1),
377 : vline0_int_entry(2),
378 : vline0_int_entry(3),
379 : vline0_int_entry(4),
380 : dmub_trace_int_entry(),
381 : };
382 :
383 : static const struct irq_service_funcs irq_service_funcs_dcn302 = {
384 : .to_dal_irq_source = to_dal_irq_source_dcn302
385 : };
386 :
387 : static void dcn302_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data)
388 : {
389 0 : dal_irq_service_construct(irq_service, init_data);
390 :
391 0 : irq_service->info = irq_source_info_dcn302;
392 0 : irq_service->funcs = &irq_service_funcs_dcn302;
393 : }
394 :
395 0 : struct irq_service *dal_irq_service_dcn302_create(struct irq_service_init_data *init_data)
396 : {
397 0 : struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL);
398 :
399 0 : if (!irq_service)
400 : return NULL;
401 :
402 0 : dcn302_irq_construct(irq_service, init_data);
403 0 : return irq_service;
404 : }
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