Line data Source code
1 : // SPDX-License-Identifier: MIT
2 : /*
3 : * Copyright 2022 Advanced Micro Devices, Inc.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: AMD
24 : *
25 : */
26 :
27 : #include "dm_services.h"
28 : #include "include/logger_interface.h"
29 : #include "../dce110/irq_service_dce110.h"
30 :
31 :
32 : #include "dcn/dcn_3_1_4_offset.h"
33 : #include "dcn/dcn_3_1_4_sh_mask.h"
34 :
35 : #include "irq_service_dcn314.h"
36 :
37 : #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
38 :
39 : #define DCN_BASE__INST0_SEG2 0x000034C0
40 :
41 0 : static enum dc_irq_source to_dal_irq_source_dcn314(
42 : struct irq_service *irq_service,
43 : uint32_t src_id,
44 : uint32_t ext_id)
45 : {
46 0 : switch (src_id) {
47 : case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
48 : return DC_IRQ_SOURCE_VBLANK1;
49 : case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
50 0 : return DC_IRQ_SOURCE_VBLANK2;
51 : case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
52 0 : return DC_IRQ_SOURCE_VBLANK3;
53 : case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
54 0 : return DC_IRQ_SOURCE_VBLANK4;
55 : case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
56 0 : return DC_IRQ_SOURCE_VBLANK5;
57 : case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
58 0 : return DC_IRQ_SOURCE_VBLANK6;
59 : case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
60 0 : return DC_IRQ_SOURCE_DC1_VLINE0;
61 : case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
62 0 : return DC_IRQ_SOURCE_DC2_VLINE0;
63 : case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
64 0 : return DC_IRQ_SOURCE_DC3_VLINE0;
65 : case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
66 0 : return DC_IRQ_SOURCE_DC4_VLINE0;
67 : case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
68 0 : return DC_IRQ_SOURCE_DC5_VLINE0;
69 : case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
70 0 : return DC_IRQ_SOURCE_DC6_VLINE0;
71 : case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
72 0 : return DC_IRQ_SOURCE_PFLIP1;
73 : case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
74 0 : return DC_IRQ_SOURCE_PFLIP2;
75 : case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
76 0 : return DC_IRQ_SOURCE_PFLIP3;
77 : case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
78 0 : return DC_IRQ_SOURCE_PFLIP4;
79 : case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
80 0 : return DC_IRQ_SOURCE_PFLIP5;
81 : case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
82 0 : return DC_IRQ_SOURCE_PFLIP6;
83 : case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
84 0 : return DC_IRQ_SOURCE_VUPDATE1;
85 : case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
86 0 : return DC_IRQ_SOURCE_VUPDATE2;
87 : case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
88 0 : return DC_IRQ_SOURCE_VUPDATE3;
89 : case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
90 0 : return DC_IRQ_SOURCE_VUPDATE4;
91 : case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
92 0 : return DC_IRQ_SOURCE_VUPDATE5;
93 : case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
94 0 : return DC_IRQ_SOURCE_VUPDATE6;
95 : case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
96 0 : return DC_IRQ_SOURCE_DMCUB_OUTBOX;
97 : case DCN_1_0__SRCID__DC_HPD1_INT:
98 : /* generic src_id for all HPD and HPDRX interrupts */
99 : switch (ext_id) {
100 : case DCN_1_0__CTXID__DC_HPD1_INT:
101 : return DC_IRQ_SOURCE_HPD1;
102 : case DCN_1_0__CTXID__DC_HPD2_INT:
103 : return DC_IRQ_SOURCE_HPD2;
104 : case DCN_1_0__CTXID__DC_HPD3_INT:
105 : return DC_IRQ_SOURCE_HPD3;
106 : case DCN_1_0__CTXID__DC_HPD4_INT:
107 : return DC_IRQ_SOURCE_HPD4;
108 : case DCN_1_0__CTXID__DC_HPD5_INT:
109 : return DC_IRQ_SOURCE_HPD5;
110 : case DCN_1_0__CTXID__DC_HPD6_INT:
111 : return DC_IRQ_SOURCE_HPD6;
112 : case DCN_1_0__CTXID__DC_HPD1_RX_INT:
113 : return DC_IRQ_SOURCE_HPD1RX;
114 : case DCN_1_0__CTXID__DC_HPD2_RX_INT:
115 : return DC_IRQ_SOURCE_HPD2RX;
116 : case DCN_1_0__CTXID__DC_HPD3_RX_INT:
117 : return DC_IRQ_SOURCE_HPD3RX;
118 : case DCN_1_0__CTXID__DC_HPD4_RX_INT:
119 : return DC_IRQ_SOURCE_HPD4RX;
120 : case DCN_1_0__CTXID__DC_HPD5_RX_INT:
121 : return DC_IRQ_SOURCE_HPD5RX;
122 : case DCN_1_0__CTXID__DC_HPD6_RX_INT:
123 : return DC_IRQ_SOURCE_HPD6RX;
124 : default:
125 : return DC_IRQ_SOURCE_INVALID;
126 : }
127 : break;
128 :
129 : default:
130 0 : return DC_IRQ_SOURCE_INVALID;
131 : }
132 : }
133 :
134 0 : static bool hpd_ack(
135 : struct irq_service *irq_service,
136 : const struct irq_source_info *info)
137 : {
138 0 : uint32_t addr = info->status_reg;
139 0 : uint32_t value = dm_read_reg(irq_service->ctx, addr);
140 0 : uint32_t current_status =
141 : get_reg_field_value(
142 : value,
143 : HPD0_DC_HPD_INT_STATUS,
144 : DC_HPD_SENSE_DELAYED);
145 :
146 0 : dal_irq_service_ack_generic(irq_service, info);
147 :
148 0 : value = dm_read_reg(irq_service->ctx, info->enable_reg);
149 :
150 0 : set_reg_field_value(
151 : value,
152 : current_status ? 0 : 1,
153 : HPD0_DC_HPD_INT_CONTROL,
154 : DC_HPD_INT_POLARITY);
155 :
156 0 : dm_write_reg(irq_service->ctx, info->enable_reg, value);
157 :
158 0 : return true;
159 : }
160 :
161 : static const struct irq_source_info_funcs hpd_irq_info_funcs = {
162 : .set = NULL,
163 : .ack = hpd_ack
164 : };
165 :
166 : static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
167 : .set = NULL,
168 : .ack = NULL
169 : };
170 :
171 : static const struct irq_source_info_funcs pflip_irq_info_funcs = {
172 : .set = NULL,
173 : .ack = NULL
174 : };
175 :
176 : static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
177 : .set = NULL,
178 : .ack = NULL
179 : };
180 :
181 : static const struct irq_source_info_funcs vblank_irq_info_funcs = {
182 : .set = NULL,
183 : .ack = NULL
184 : };
185 :
186 : static const struct irq_source_info_funcs outbox_irq_info_funcs = {
187 : .set = NULL,
188 : .ack = NULL
189 : };
190 :
191 : static const struct irq_source_info_funcs vline0_irq_info_funcs = {
192 : .set = NULL,
193 : .ack = NULL
194 : };
195 :
196 : #undef BASE_INNER
197 : #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
198 :
199 : /* compile time expand base address. */
200 : #define BASE(seg) \
201 : BASE_INNER(seg)
202 :
203 : #define SRI(reg_name, block, id)\
204 : (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
205 : reg ## block ## id ## _ ## reg_name)
206 :
207 : #define SRI_DMUB(reg_name)\
208 : (BASE(reg ## reg_name ## _BASE_IDX) + \
209 : reg ## reg_name)
210 :
211 : #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
212 : .enable_reg = SRI(reg1, block, reg_num),\
213 : .enable_mask = \
214 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 : .enable_value = {\
216 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
217 : ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
218 : },\
219 : .ack_reg = SRI(reg2, block, reg_num),\
220 : .ack_mask = \
221 : block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
222 : .ack_value = \
223 : block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
224 :
225 : #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
226 : .enable_reg = SRI_DMUB(reg1),\
227 : .enable_mask = \
228 : reg1 ## __ ## mask1 ## _MASK,\
229 : .enable_value = {\
230 : reg1 ## __ ## mask1 ## _MASK,\
231 : ~reg1 ## __ ## mask1 ## _MASK \
232 : },\
233 : .ack_reg = SRI_DMUB(reg2),\
234 : .ack_mask = \
235 : reg2 ## __ ## mask2 ## _MASK,\
236 : .ack_value = \
237 : reg2 ## __ ## mask2 ## _MASK \
238 :
239 : #define hpd_int_entry(reg_num)\
240 : [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
241 : IRQ_REG_ENTRY(HPD, reg_num,\
242 : DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
243 : DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
244 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
245 : .funcs = &hpd_irq_info_funcs\
246 : }
247 :
248 : #define hpd_rx_int_entry(reg_num)\
249 : [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
250 : IRQ_REG_ENTRY(HPD, reg_num,\
251 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
252 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
253 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
254 : .funcs = &hpd_rx_irq_info_funcs\
255 : }
256 : #define pflip_int_entry(reg_num)\
257 : [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
258 : IRQ_REG_ENTRY(HUBPREQ, reg_num,\
259 : DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
260 : DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
261 : .funcs = &pflip_irq_info_funcs\
262 : }
263 :
264 : /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
265 : * of DCE's DC_IRQ_SOURCE_VUPDATEx.
266 : */
267 : #define vupdate_no_lock_int_entry(reg_num)\
268 : [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
269 : IRQ_REG_ENTRY(OTG, reg_num,\
270 : OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
271 : OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
272 : .funcs = &vupdate_no_lock_irq_info_funcs\
273 : }
274 :
275 : #define vblank_int_entry(reg_num)\
276 : [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
277 : IRQ_REG_ENTRY(OTG, reg_num,\
278 : OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
279 : OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
280 : .funcs = &vblank_irq_info_funcs\
281 : }
282 :
283 : #define vline0_int_entry(reg_num)\
284 : [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
285 : IRQ_REG_ENTRY(OTG, reg_num,\
286 : OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
287 : OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
288 : .funcs = &vline0_irq_info_funcs\
289 : }
290 : #define dmub_outbox_int_entry()\
291 : [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
292 : IRQ_REG_ENTRY_DMUB(\
293 : DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
294 : DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
295 : .funcs = &outbox_irq_info_funcs\
296 : }
297 :
298 : #define dummy_irq_entry() \
299 : {\
300 : .funcs = &dummy_irq_info_funcs\
301 : }
302 :
303 : #define i2c_int_entry(reg_num) \
304 : [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
305 :
306 : #define dp_sink_int_entry(reg_num) \
307 : [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
308 :
309 : #define gpio_pad_int_entry(reg_num) \
310 : [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
311 :
312 : #define dc_underflow_int_entry(reg_num) \
313 : [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
314 :
315 : static const struct irq_source_info_funcs dummy_irq_info_funcs = {
316 : .set = dal_irq_service_dummy_set,
317 : .ack = dal_irq_service_dummy_ack
318 : };
319 :
320 : static const struct irq_source_info
321 : irq_source_info_dcn314[DAL_IRQ_SOURCES_NUMBER] = {
322 : [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
323 : hpd_int_entry(0),
324 : hpd_int_entry(1),
325 : hpd_int_entry(2),
326 : hpd_int_entry(3),
327 : hpd_int_entry(4),
328 : hpd_rx_int_entry(0),
329 : hpd_rx_int_entry(1),
330 : hpd_rx_int_entry(2),
331 : hpd_rx_int_entry(3),
332 : hpd_rx_int_entry(4),
333 : i2c_int_entry(1),
334 : i2c_int_entry(2),
335 : i2c_int_entry(3),
336 : i2c_int_entry(4),
337 : i2c_int_entry(5),
338 : i2c_int_entry(6),
339 : dp_sink_int_entry(1),
340 : dp_sink_int_entry(2),
341 : dp_sink_int_entry(3),
342 : dp_sink_int_entry(4),
343 : dp_sink_int_entry(5),
344 : dp_sink_int_entry(6),
345 : [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
346 : pflip_int_entry(0),
347 : pflip_int_entry(1),
348 : pflip_int_entry(2),
349 : pflip_int_entry(3),
350 : [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
351 : [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
352 : [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
353 : gpio_pad_int_entry(0),
354 : gpio_pad_int_entry(1),
355 : gpio_pad_int_entry(2),
356 : gpio_pad_int_entry(3),
357 : gpio_pad_int_entry(4),
358 : gpio_pad_int_entry(5),
359 : gpio_pad_int_entry(6),
360 : gpio_pad_int_entry(7),
361 : gpio_pad_int_entry(8),
362 : gpio_pad_int_entry(9),
363 : gpio_pad_int_entry(10),
364 : gpio_pad_int_entry(11),
365 : gpio_pad_int_entry(12),
366 : gpio_pad_int_entry(13),
367 : gpio_pad_int_entry(14),
368 : gpio_pad_int_entry(15),
369 : gpio_pad_int_entry(16),
370 : gpio_pad_int_entry(17),
371 : gpio_pad_int_entry(18),
372 : gpio_pad_int_entry(19),
373 : gpio_pad_int_entry(20),
374 : gpio_pad_int_entry(21),
375 : gpio_pad_int_entry(22),
376 : gpio_pad_int_entry(23),
377 : gpio_pad_int_entry(24),
378 : gpio_pad_int_entry(25),
379 : gpio_pad_int_entry(26),
380 : gpio_pad_int_entry(27),
381 : gpio_pad_int_entry(28),
382 : gpio_pad_int_entry(29),
383 : gpio_pad_int_entry(30),
384 : dc_underflow_int_entry(1),
385 : dc_underflow_int_entry(2),
386 : dc_underflow_int_entry(3),
387 : dc_underflow_int_entry(4),
388 : dc_underflow_int_entry(5),
389 : dc_underflow_int_entry(6),
390 : [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
391 : [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
392 : vupdate_no_lock_int_entry(0),
393 : vupdate_no_lock_int_entry(1),
394 : vupdate_no_lock_int_entry(2),
395 : vupdate_no_lock_int_entry(3),
396 : vblank_int_entry(0),
397 : vblank_int_entry(1),
398 : vblank_int_entry(2),
399 : vblank_int_entry(3),
400 : vline0_int_entry(0),
401 : vline0_int_entry(1),
402 : vline0_int_entry(2),
403 : vline0_int_entry(3),
404 : [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
405 : [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
406 : dmub_outbox_int_entry(),
407 : };
408 :
409 : static const struct irq_service_funcs irq_service_funcs_dcn314 = {
410 : .to_dal_irq_source = to_dal_irq_source_dcn314
411 : };
412 :
413 : static void dcn314_irq_construct(
414 : struct irq_service *irq_service,
415 : struct irq_service_init_data *init_data)
416 : {
417 0 : dal_irq_service_construct(irq_service, init_data);
418 :
419 0 : irq_service->info = irq_source_info_dcn314;
420 0 : irq_service->funcs = &irq_service_funcs_dcn314;
421 : }
422 :
423 0 : struct irq_service *dal_irq_service_dcn314_create(
424 : struct irq_service_init_data *init_data)
425 : {
426 0 : struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
427 : GFP_KERNEL);
428 :
429 0 : if (!irq_service)
430 : return NULL;
431 :
432 0 : dcn314_irq_construct(irq_service, init_data);
433 0 : return irq_service;
434 : }
|
