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1 : /*
2 : * Copyright 2022 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dm_services.h"
27 : #include "include/logger_interface.h"
28 : #include "../dce110/irq_service_dce110.h"
29 :
30 : #include "dcn/dcn_3_2_0_offset.h"
31 : #include "dcn/dcn_3_2_0_sh_mask.h"
32 :
33 : #include "irq_service_dcn32.h"
34 :
35 : #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
36 :
37 : #define DCN_BASE__INST0_SEG2 0x000034C0
38 :
39 0 : static enum dc_irq_source to_dal_irq_source_dcn32(
40 : struct irq_service *irq_service,
41 : uint32_t src_id,
42 : uint32_t ext_id)
43 : {
44 0 : switch (src_id) {
45 : case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
46 : return DC_IRQ_SOURCE_VBLANK1;
47 : case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
48 0 : return DC_IRQ_SOURCE_VBLANK2;
49 : case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
50 0 : return DC_IRQ_SOURCE_VBLANK3;
51 : case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
52 0 : return DC_IRQ_SOURCE_VBLANK4;
53 : case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
54 0 : return DC_IRQ_SOURCE_VBLANK5;
55 : case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
56 0 : return DC_IRQ_SOURCE_VBLANK6;
57 : case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
58 0 : return DC_IRQ_SOURCE_DC1_VLINE0;
59 : case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
60 0 : return DC_IRQ_SOURCE_DC2_VLINE0;
61 : case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
62 0 : return DC_IRQ_SOURCE_DC3_VLINE0;
63 : case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
64 0 : return DC_IRQ_SOURCE_DC4_VLINE0;
65 : case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
66 0 : return DC_IRQ_SOURCE_DC5_VLINE0;
67 : case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
68 0 : return DC_IRQ_SOURCE_DC6_VLINE0;
69 : case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
70 0 : return DC_IRQ_SOURCE_PFLIP1;
71 : case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
72 0 : return DC_IRQ_SOURCE_PFLIP2;
73 : case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
74 0 : return DC_IRQ_SOURCE_PFLIP3;
75 : case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
76 0 : return DC_IRQ_SOURCE_PFLIP4;
77 : case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
78 0 : return DC_IRQ_SOURCE_PFLIP5;
79 : case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
80 0 : return DC_IRQ_SOURCE_PFLIP6;
81 : case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
82 0 : return DC_IRQ_SOURCE_VUPDATE1;
83 : case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
84 0 : return DC_IRQ_SOURCE_VUPDATE2;
85 : case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
86 0 : return DC_IRQ_SOURCE_VUPDATE3;
87 : case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
88 0 : return DC_IRQ_SOURCE_VUPDATE4;
89 : case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
90 0 : return DC_IRQ_SOURCE_VUPDATE5;
91 : case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
92 0 : return DC_IRQ_SOURCE_VUPDATE6;
93 : case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
94 0 : return DC_IRQ_SOURCE_DMCUB_OUTBOX;
95 : case DCN_1_0__SRCID__DC_HPD1_INT:
96 : /* generic src_id for all HPD and HPDRX interrupts */
97 : switch (ext_id) {
98 : case DCN_1_0__CTXID__DC_HPD1_INT:
99 : return DC_IRQ_SOURCE_HPD1;
100 : case DCN_1_0__CTXID__DC_HPD2_INT:
101 : return DC_IRQ_SOURCE_HPD2;
102 : case DCN_1_0__CTXID__DC_HPD3_INT:
103 : return DC_IRQ_SOURCE_HPD3;
104 : case DCN_1_0__CTXID__DC_HPD4_INT:
105 : return DC_IRQ_SOURCE_HPD4;
106 : case DCN_1_0__CTXID__DC_HPD5_INT:
107 : return DC_IRQ_SOURCE_HPD5;
108 : case DCN_1_0__CTXID__DC_HPD6_INT:
109 : return DC_IRQ_SOURCE_HPD6;
110 : case DCN_1_0__CTXID__DC_HPD1_RX_INT:
111 : return DC_IRQ_SOURCE_HPD1RX;
112 : case DCN_1_0__CTXID__DC_HPD2_RX_INT:
113 : return DC_IRQ_SOURCE_HPD2RX;
114 : case DCN_1_0__CTXID__DC_HPD3_RX_INT:
115 : return DC_IRQ_SOURCE_HPD3RX;
116 : case DCN_1_0__CTXID__DC_HPD4_RX_INT:
117 : return DC_IRQ_SOURCE_HPD4RX;
118 : case DCN_1_0__CTXID__DC_HPD5_RX_INT:
119 : return DC_IRQ_SOURCE_HPD5RX;
120 : case DCN_1_0__CTXID__DC_HPD6_RX_INT:
121 : return DC_IRQ_SOURCE_HPD6RX;
122 : default:
123 : return DC_IRQ_SOURCE_INVALID;
124 : }
125 : break;
126 :
127 : default:
128 0 : return DC_IRQ_SOURCE_INVALID;
129 : }
130 : }
131 :
132 0 : static bool hpd_ack(
133 : struct irq_service *irq_service,
134 : const struct irq_source_info *info)
135 : {
136 0 : uint32_t addr = info->status_reg;
137 0 : uint32_t value = dm_read_reg(irq_service->ctx, addr);
138 0 : uint32_t current_status =
139 : get_reg_field_value(
140 : value,
141 : HPD0_DC_HPD_INT_STATUS,
142 : DC_HPD_SENSE_DELAYED);
143 :
144 0 : dal_irq_service_ack_generic(irq_service, info);
145 :
146 0 : value = dm_read_reg(irq_service->ctx, info->enable_reg);
147 :
148 0 : set_reg_field_value(
149 : value,
150 : current_status ? 0 : 1,
151 : HPD0_DC_HPD_INT_CONTROL,
152 : DC_HPD_INT_POLARITY);
153 :
154 0 : dm_write_reg(irq_service->ctx, info->enable_reg, value);
155 :
156 0 : return true;
157 : }
158 :
159 : static const struct irq_source_info_funcs hpd_irq_info_funcs = {
160 : .set = NULL,
161 : .ack = hpd_ack
162 : };
163 :
164 : static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
165 : .set = NULL,
166 : .ack = NULL
167 : };
168 :
169 : static const struct irq_source_info_funcs pflip_irq_info_funcs = {
170 : .set = NULL,
171 : .ack = NULL
172 : };
173 :
174 : static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
175 : .set = NULL,
176 : .ack = NULL
177 : };
178 :
179 : static const struct irq_source_info_funcs vblank_irq_info_funcs = {
180 : .set = NULL,
181 : .ack = NULL
182 : };
183 :
184 : static const struct irq_source_info_funcs outbox_irq_info_funcs = {
185 : .set = NULL,
186 : .ack = NULL
187 : };
188 :
189 : static const struct irq_source_info_funcs vline0_irq_info_funcs = {
190 : .set = NULL,
191 : .ack = NULL
192 : };
193 :
194 : #undef BASE_INNER
195 : #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
196 :
197 : /* compile time expand base address. */
198 : #define BASE(seg) \
199 : BASE_INNER(seg)
200 :
201 : #define SRI(reg_name, block, id)\
202 : BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
203 : reg ## block ## id ## _ ## reg_name
204 :
205 : #define SRI_DMUB(reg_name)\
206 : BASE(reg ## reg_name ## _BASE_IDX) + \
207 : reg ## reg_name
208 :
209 : #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
210 : .enable_reg = SRI(reg1, block, reg_num),\
211 : .enable_mask = \
212 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 : .enable_value = {\
214 : block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 : ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
216 : },\
217 : .ack_reg = SRI(reg2, block, reg_num),\
218 : .ack_mask = \
219 : block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
220 : .ack_value = \
221 : block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
222 :
223 : #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
224 : .enable_reg = SRI_DMUB(reg1),\
225 : .enable_mask = \
226 : reg1 ## __ ## mask1 ## _MASK,\
227 : .enable_value = {\
228 : reg1 ## __ ## mask1 ## _MASK,\
229 : ~reg1 ## __ ## mask1 ## _MASK \
230 : },\
231 : .ack_reg = SRI_DMUB(reg2),\
232 : .ack_mask = \
233 : reg2 ## __ ## mask2 ## _MASK,\
234 : .ack_value = \
235 : reg2 ## __ ## mask2 ## _MASK \
236 :
237 : #define hpd_int_entry(reg_num)\
238 : [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
239 : IRQ_REG_ENTRY(HPD, reg_num,\
240 : DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
241 : DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
242 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
243 : .funcs = &hpd_irq_info_funcs\
244 : }
245 :
246 : #define hpd_rx_int_entry(reg_num)\
247 : [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
248 : IRQ_REG_ENTRY(HPD, reg_num,\
249 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
250 : DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
251 : .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
252 : .funcs = &hpd_rx_irq_info_funcs\
253 : }
254 : #define pflip_int_entry(reg_num)\
255 : [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
256 : IRQ_REG_ENTRY(HUBPREQ, reg_num,\
257 : DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
258 : DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
259 : .funcs = &pflip_irq_info_funcs\
260 : }
261 :
262 : /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
263 : * of DCE's DC_IRQ_SOURCE_VUPDATEx.
264 : */
265 : #define vupdate_no_lock_int_entry(reg_num)\
266 : [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
267 : IRQ_REG_ENTRY(OTG, reg_num,\
268 : OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
269 : OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
270 : .funcs = &vupdate_no_lock_irq_info_funcs\
271 : }
272 :
273 : #define vblank_int_entry(reg_num)\
274 : [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
275 : IRQ_REG_ENTRY(OTG, reg_num,\
276 : OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
277 : OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
278 : .funcs = &vblank_irq_info_funcs\
279 : }
280 :
281 : #define vline0_int_entry(reg_num)\
282 : [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
283 : IRQ_REG_ENTRY(OTG, reg_num,\
284 : OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
285 : OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
286 : .funcs = &vline0_irq_info_funcs\
287 : }
288 : #define dmub_outbox_int_entry()\
289 : [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
290 : IRQ_REG_ENTRY_DMUB(\
291 : DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
292 : DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
293 : .funcs = &outbox_irq_info_funcs\
294 : }
295 :
296 : #define dummy_irq_entry() \
297 : {\
298 : .funcs = &dummy_irq_info_funcs\
299 : }
300 :
301 : #define i2c_int_entry(reg_num) \
302 : [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
303 :
304 : #define dp_sink_int_entry(reg_num) \
305 : [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
306 :
307 : #define gpio_pad_int_entry(reg_num) \
308 : [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
309 :
310 : #define dc_underflow_int_entry(reg_num) \
311 : [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
312 :
313 : static const struct irq_source_info_funcs dummy_irq_info_funcs = {
314 : .set = dal_irq_service_dummy_set,
315 : .ack = dal_irq_service_dummy_ack
316 : };
317 :
318 : static const struct irq_source_info
319 : irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {
320 : [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
321 : hpd_int_entry(0),
322 : hpd_int_entry(1),
323 : hpd_int_entry(2),
324 : hpd_int_entry(3),
325 : hpd_int_entry(4),
326 : hpd_rx_int_entry(0),
327 : hpd_rx_int_entry(1),
328 : hpd_rx_int_entry(2),
329 : hpd_rx_int_entry(3),
330 : hpd_rx_int_entry(4),
331 : i2c_int_entry(1),
332 : i2c_int_entry(2),
333 : i2c_int_entry(3),
334 : i2c_int_entry(4),
335 : i2c_int_entry(5),
336 : i2c_int_entry(6),
337 : dp_sink_int_entry(1),
338 : dp_sink_int_entry(2),
339 : dp_sink_int_entry(3),
340 : dp_sink_int_entry(4),
341 : dp_sink_int_entry(5),
342 : dp_sink_int_entry(6),
343 : [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
344 : pflip_int_entry(0),
345 : pflip_int_entry(1),
346 : pflip_int_entry(2),
347 : pflip_int_entry(3),
348 : [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
349 : [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
350 : [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
351 : gpio_pad_int_entry(0),
352 : gpio_pad_int_entry(1),
353 : gpio_pad_int_entry(2),
354 : gpio_pad_int_entry(3),
355 : gpio_pad_int_entry(4),
356 : gpio_pad_int_entry(5),
357 : gpio_pad_int_entry(6),
358 : gpio_pad_int_entry(7),
359 : gpio_pad_int_entry(8),
360 : gpio_pad_int_entry(9),
361 : gpio_pad_int_entry(10),
362 : gpio_pad_int_entry(11),
363 : gpio_pad_int_entry(12),
364 : gpio_pad_int_entry(13),
365 : gpio_pad_int_entry(14),
366 : gpio_pad_int_entry(15),
367 : gpio_pad_int_entry(16),
368 : gpio_pad_int_entry(17),
369 : gpio_pad_int_entry(18),
370 : gpio_pad_int_entry(19),
371 : gpio_pad_int_entry(20),
372 : gpio_pad_int_entry(21),
373 : gpio_pad_int_entry(22),
374 : gpio_pad_int_entry(23),
375 : gpio_pad_int_entry(24),
376 : gpio_pad_int_entry(25),
377 : gpio_pad_int_entry(26),
378 : gpio_pad_int_entry(27),
379 : gpio_pad_int_entry(28),
380 : gpio_pad_int_entry(29),
381 : gpio_pad_int_entry(30),
382 : dc_underflow_int_entry(1),
383 : dc_underflow_int_entry(2),
384 : dc_underflow_int_entry(3),
385 : dc_underflow_int_entry(4),
386 : dc_underflow_int_entry(5),
387 : dc_underflow_int_entry(6),
388 : [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
389 : [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
390 : vupdate_no_lock_int_entry(0),
391 : vupdate_no_lock_int_entry(1),
392 : vupdate_no_lock_int_entry(2),
393 : vupdate_no_lock_int_entry(3),
394 : vblank_int_entry(0),
395 : vblank_int_entry(1),
396 : vblank_int_entry(2),
397 : vblank_int_entry(3),
398 : vline0_int_entry(0),
399 : vline0_int_entry(1),
400 : vline0_int_entry(2),
401 : vline0_int_entry(3),
402 : [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
403 : [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
404 : dmub_outbox_int_entry(),
405 : };
406 :
407 : static const struct irq_service_funcs irq_service_funcs_dcn32 = {
408 : .to_dal_irq_source = to_dal_irq_source_dcn32
409 : };
410 :
411 : static void dcn32_irq_construct(
412 : struct irq_service *irq_service,
413 : struct irq_service_init_data *init_data)
414 : {
415 0 : dal_irq_service_construct(irq_service, init_data);
416 :
417 0 : irq_service->info = irq_source_info_dcn32;
418 0 : irq_service->funcs = &irq_service_funcs_dcn32;
419 : }
420 :
421 0 : struct irq_service *dal_irq_service_dcn32_create(
422 : struct irq_service_init_data *init_data)
423 : {
424 0 : struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
425 : GFP_KERNEL);
426 :
427 0 : if (!irq_service)
428 : return NULL;
429 :
430 0 : dcn32_irq_construct(irq_service, init_data);
431 0 : return irq_service;
432 : }
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