Line data Source code
1 : /*
2 : * Copyright 2022 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 : #include "link_hwss_dio.h"
26 : #include "core_types.h"
27 : #include "dc_link_dp.h"
28 : #include "link_enc_cfg.h"
29 :
30 0 : void set_dio_throttled_vcp_size(struct pipe_ctx *pipe_ctx,
31 : struct fixed31_32 throttled_vcp_size)
32 : {
33 0 : struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
34 :
35 0 : stream_encoder->funcs->set_throttled_vcp_size(
36 : stream_encoder,
37 : throttled_vcp_size);
38 0 : }
39 :
40 0 : void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx)
41 : {
42 0 : struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
43 0 : struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
44 :
45 0 : link_enc->funcs->connect_dig_be_to_fe(link_enc,
46 : pipe_ctx->stream_res.stream_enc->id, true);
47 0 : if (dc_is_dp_signal(pipe_ctx->stream->signal))
48 0 : dp_source_sequence_trace(pipe_ctx->stream->link,
49 : DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE);
50 0 : if (stream_enc->funcs->enable_fifo)
51 0 : stream_enc->funcs->enable_fifo(stream_enc);
52 0 : }
53 :
54 0 : void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx)
55 : {
56 0 : struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
57 0 : struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
58 :
59 0 : if (stream_enc && stream_enc->funcs->disable_fifo)
60 0 : stream_enc->funcs->disable_fifo(stream_enc);
61 :
62 0 : link_enc->funcs->connect_dig_be_to_fe(
63 : link_enc,
64 0 : pipe_ctx->stream_res.stream_enc->id,
65 : false);
66 0 : if (dc_is_dp_signal(pipe_ctx->stream->signal))
67 0 : dp_source_sequence_trace(pipe_ctx->stream->link,
68 : DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE);
69 :
70 0 : }
71 :
72 0 : void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx)
73 : {
74 0 : struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
75 0 : struct dc_stream_state *stream = pipe_ctx->stream;
76 0 : struct dc_link *link = stream->link;
77 :
78 0 : if (!dc_is_virtual_signal(stream->signal))
79 0 : stream_encoder->funcs->setup_stereo_sync(
80 : stream_encoder,
81 0 : pipe_ctx->stream_res.tg->inst,
82 0 : stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
83 :
84 0 : if (dc_is_dp_signal(stream->signal))
85 0 : stream_encoder->funcs->dp_set_stream_attribute(
86 : stream_encoder,
87 : &stream->timing,
88 : stream->output_color_space,
89 0 : stream->use_vsc_sdp_for_colorimetry,
90 0 : link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
91 0 : else if (dc_is_hdmi_tmds_signal(stream->signal))
92 0 : stream_encoder->funcs->hdmi_set_stream_attribute(
93 : stream_encoder,
94 : &stream->timing,
95 : stream->phy_pix_clk,
96 0 : pipe_ctx->stream_res.audio != NULL);
97 0 : else if (dc_is_dvi_signal(stream->signal))
98 0 : stream_encoder->funcs->dvi_set_stream_attribute(
99 : stream_encoder,
100 : &stream->timing,
101 : (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
102 : true : false);
103 0 : else if (dc_is_lvds_signal(stream->signal))
104 0 : stream_encoder->funcs->lvds_set_stream_attribute(
105 : stream_encoder,
106 : &stream->timing);
107 :
108 0 : if (dc_is_dp_signal(stream->signal))
109 0 : dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
110 0 : }
111 :
112 0 : void enable_dio_dp_link_output(struct dc_link *link,
113 : const struct link_resource *link_res,
114 : enum signal_type signal,
115 : enum clock_source_id clock_source,
116 : const struct dc_link_settings *link_settings)
117 : {
118 0 : struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
119 :
120 0 : if (dc_is_dp_sst_signal(signal))
121 0 : link_enc->funcs->enable_dp_output(
122 : link_enc,
123 : link_settings,
124 : clock_source);
125 : else
126 0 : link_enc->funcs->enable_dp_mst_output(
127 : link_enc,
128 : link_settings,
129 : clock_source);
130 0 : dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
131 0 : }
132 :
133 0 : void disable_dio_dp_link_output(struct dc_link *link,
134 : const struct link_resource *link_res,
135 : enum signal_type signal)
136 : {
137 0 : struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
138 :
139 0 : link_enc->funcs->disable_output(link_enc, signal);
140 0 : dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
141 0 : }
142 :
143 0 : void set_dio_dp_link_test_pattern(struct dc_link *link,
144 : const struct link_resource *link_res,
145 : struct encoder_set_dp_phy_pattern_param *tp_params)
146 : {
147 0 : struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
148 :
149 0 : link_enc->funcs->dp_set_phy_pattern(link_enc, tp_params);
150 0 : dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
151 0 : }
152 :
153 0 : void set_dio_dp_lane_settings(struct dc_link *link,
154 : const struct link_resource *link_res,
155 : const struct dc_link_settings *link_settings,
156 : const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
157 : {
158 0 : struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
159 :
160 0 : link_enc->funcs->dp_set_lane_settings(link_enc, link_settings, lane_settings);
161 0 : }
162 :
163 0 : static void update_dio_stream_allocation_table(struct dc_link *link,
164 : const struct link_resource *link_res,
165 : const struct link_mst_stream_allocation_table *table)
166 : {
167 0 : struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
168 :
169 0 : ASSERT(link_enc);
170 0 : link_enc->funcs->update_mst_stream_allocation_table(link_enc, table);
171 0 : }
172 :
173 : static const struct link_hwss dio_link_hwss = {
174 : .setup_stream_encoder = setup_dio_stream_encoder,
175 : .reset_stream_encoder = reset_dio_stream_encoder,
176 : .setup_stream_attribute = setup_dio_stream_attribute,
177 : .ext = {
178 : .set_throttled_vcp_size = set_dio_throttled_vcp_size,
179 : .enable_dp_link_output = enable_dio_dp_link_output,
180 : .disable_dp_link_output = disable_dio_dp_link_output,
181 : .set_dp_link_test_pattern = set_dio_dp_link_test_pattern,
182 : .set_dp_lane_settings = set_dio_dp_lane_settings,
183 : .update_stream_allocation_table = update_dio_stream_allocation_table,
184 : },
185 : };
186 :
187 0 : bool can_use_dio_link_hwss(const struct dc_link *link,
188 : const struct link_resource *link_res)
189 : {
190 0 : return link->link_enc != NULL;
191 : }
192 :
193 0 : const struct link_hwss *get_dio_link_hwss(void)
194 : {
195 0 : return &dio_link_hwss;
196 : }
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