Line data    Source code

       1             : /*
       2             :  * Copyright 2019 Advanced Micro Devices, Inc.
       3             :  *
       4             :  * Permission is hereby granted, free of charge, to any person obtaining a
       5             :  * copy of this software and associated documentation files (the "Software"),
       6             :  * to deal in the Software without restriction, including without limitation
       7             :  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
       8             :  * and/or sell copies of the Software, and to permit persons to whom the
       9             :  * Software is furnished to do so, subject to the following conditions:
      10             :  *
      11             :  * The above copyright notice and this permission notice shall be included in
      12             :  * all copies or substantial portions of the Software.
      13             :  *
      14             :  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
      15             :  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
      16             :  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
      17             :  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
      18             :  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
      19             :  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
      20             :  * OTHER DEALINGS IN THE SOFTWARE.
      21             :  *
      22             :  * Authors: AMD
      23             :  *
      24             :  */
      25             : 
      26             : #include "../dmub_srv.h"
      27             : #include "dmub_reg.h"
      28             : #include "dmub_dcn20.h"
      29             : 
      30             : #include "dcn/dcn_2_0_0_offset.h"
      31             : #include "dcn/dcn_2_0_0_sh_mask.h"
      32             : #include "soc15_hw_ip.h"
      33             : #include "vega10_ip_offset.h"
      34             : 
      35             : #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
      36             : #define CTX dmub
      37             : #define REGS dmub->regs
      38             : 
      39             : /* Registers. */
      40             : 
      41             : const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
      42             : #define DMUB_SR(reg) REG_OFFSET(reg),
      43             :         {
      44             :                 DMUB_COMMON_REGS()
      45             :                 DMCUB_INTERNAL_REGS()
      46             :         },
      47             : #undef DMUB_SR
      48             : 
      49             : #define DMUB_SF(reg, field) FD_MASK(reg, field),
      50             :         { DMUB_COMMON_FIELDS() },
      51             : #undef DMUB_SF
      52             : 
      53             : #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
      54             :         { DMUB_COMMON_FIELDS() },
      55             : #undef DMUB_SF
      56             : };
      57             : 
      58             : /* Shared functions. */
      59             : 
      60           0 : static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
      61             :                                           uint64_t *fb_base,
      62             :                                           uint64_t *fb_offset)
      63             : {
      64             :         uint32_t tmp;
      65             : 
      66           0 :         if (dmub->fb_base || dmub->fb_offset) {
      67           0 :                 *fb_base = dmub->fb_base;
      68           0 :                 *fb_offset = dmub->fb_offset;
      69           0 :                 return;
      70             :         }
      71             : 
      72           0 :         REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
      73           0 :         *fb_base = (uint64_t)tmp << 24;
      74             : 
      75           0 :         REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
      76           0 :         *fb_offset = (uint64_t)tmp << 24;
      77             : }
      78             : 
      79             : static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
      80             :                                              uint64_t fb_base,
      81             :                                              uint64_t fb_offset,
      82             :                                              union dmub_addr *addr_out)
      83             : {
      84           0 :         addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
      85             : }
      86             : 
      87           0 : bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
      88             : {
      89             :         /* Cached inbox is not supported in this fw version range */
      90           0 :         return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&
      91             :                  dmub->fw_version <= DMUB_FW_VERSION(1, 10, 0));
      92             : }
      93             : 
      94           0 : void dmub_dcn20_reset(struct dmub_srv *dmub)
      95             : {
      96             :         union dmub_gpint_data_register cmd;
      97           0 :         const uint32_t timeout = 30;
      98             :         uint32_t in_reset, scratch, i;
      99             : 
     100           0 :         REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset);
     101             : 
     102           0 :         if (in_reset == 0) {
     103           0 :                 cmd.bits.status = 1;
     104           0 :                 cmd.bits.command_code = DMUB_GPINT__STOP_FW;
     105           0 :                 cmd.bits.param = 0;
     106             : 
     107           0 :                 dmub->hw_funcs.set_gpint(dmub, cmd);
     108             : 
     109             :                 /**
     110             :                  * Timeout covers both the ACK and the wait
     111             :                  * for remaining work to finish.
     112             :                  *
     113             :                  * This is mostly bound by the PHY disable sequence.
     114             :                  * Each register check will be greater than 1us, so
     115             :                  * don't bother using udelay.
     116             :                  */
     117             : 
     118           0 :                 for (i = 0; i < timeout; ++i) {
     119           0 :                         if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
     120             :                                 break;
     121             :                 }
     122             : 
     123           0 :                 for (i = 0; i < timeout; ++i) {
     124           0 :                         scratch = dmub->hw_funcs.get_gpint_response(dmub);
     125           0 :                         if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
     126             :                                 break;
     127             :                 }
     128             : 
     129             :                 /* Clear the GPINT command manually so we don't reset again. */
     130           0 :                 cmd.all = 0;
     131           0 :                 dmub->hw_funcs.set_gpint(dmub, cmd);
     132             : 
     133             :                 /* Force reset in case we timed out, DMCUB is likely hung. */
     134             :         }
     135             : 
     136           0 :         REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
     137           0 :         REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
     138           0 :         REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
     139           0 :         REG_WRITE(DMCUB_INBOX1_RPTR, 0);
     140           0 :         REG_WRITE(DMCUB_INBOX1_WPTR, 0);
     141           0 :         REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
     142           0 :         REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
     143           0 :         REG_WRITE(DMCUB_SCRATCH0, 0);
     144           0 : }
     145             : 
     146           0 : void dmub_dcn20_reset_release(struct dmub_srv *dmub)
     147             : {
     148           0 :         REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
     149           0 :         REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
     150           0 :         REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
     151           0 :         REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
     152           0 : }
     153             : 
     154           0 : void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
     155             :                               const struct dmub_window *cw0,
     156             :                               const struct dmub_window *cw1)
     157             : {
     158             :         union dmub_addr offset;
     159             :         uint64_t fb_base, fb_offset;
     160             : 
     161           0 :         dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
     162             : 
     163           0 :         REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
     164           0 :         REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
     165             :                      DMCUB_MEM_WRITE_SPACE, 0x3);
     166             : 
     167           0 :         dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
     168             : 
     169           0 :         REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
     170           0 :         REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
     171           0 :         REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
     172           0 :         REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
     173             :                   DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
     174             :                   DMCUB_REGION3_CW0_ENABLE, 1);
     175             : 
     176           0 :         dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
     177             : 
     178           0 :         REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
     179           0 :         REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
     180           0 :         REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
     181           0 :         REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
     182             :                   DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
     183             :                   DMCUB_REGION3_CW1_ENABLE, 1);
     184             : 
     185           0 :         REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
     186             :                      0x20);
     187           0 : }
     188             : 
     189           0 : void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
     190             :                               const struct dmub_window *cw2,
     191             :                               const struct dmub_window *cw3,
     192             :                               const struct dmub_window *cw4,
     193             :                               const struct dmub_window *cw5,
     194             :                               const struct dmub_window *cw6)
     195             : {
     196             :         union dmub_addr offset;
     197             :         uint64_t fb_base, fb_offset;
     198             : 
     199           0 :         dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
     200             : 
     201           0 :         if (cw2->region.base != cw2->region.top) {
     202           0 :                 dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset,
     203             :                                           &offset);
     204             : 
     205           0 :                 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
     206           0 :                 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
     207           0 :                 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
     208           0 :                 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
     209             :                           DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
     210             :                           DMCUB_REGION3_CW2_ENABLE, 1);
     211             :         } else {
     212           0 :                 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
     213           0 :                 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
     214           0 :                 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
     215           0 :                 REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
     216             :         }
     217             : 
     218           0 :         dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
     219             : 
     220           0 :         REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
     221           0 :         REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
     222           0 :         REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
     223           0 :         REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
     224             :                   DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
     225             :                   DMCUB_REGION3_CW3_ENABLE, 1);
     226             : 
     227             :         /* TODO: Move this to CW4. */
     228           0 :         dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
     229             : 
     230             :         /* New firmware can support CW4. */
     231           0 :         if (dmub_dcn20_use_cached_inbox(dmub)) {
     232           0 :                 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
     233           0 :                 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
     234           0 :                 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
     235           0 :                 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
     236             :                           DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
     237             :                           DMCUB_REGION3_CW4_ENABLE, 1);
     238             :         } else {
     239           0 :                 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
     240           0 :                 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
     241           0 :                 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
     242             :                           DMCUB_REGION4_TOP_ADDRESS,
     243             :                           cw4->region.top - cw4->region.base - 1,
     244             :                           DMCUB_REGION4_ENABLE, 1);
     245             :         }
     246             : 
     247           0 :         dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
     248             : 
     249           0 :         REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
     250           0 :         REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
     251           0 :         REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
     252           0 :         REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
     253             :                   DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
     254             :                   DMCUB_REGION3_CW5_ENABLE, 1);
     255             : 
     256           0 :         REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
     257           0 :         REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
     258           0 :         REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
     259             :                   DMCUB_REGION5_TOP_ADDRESS,
     260             :                   cw5->region.top - cw5->region.base - 1,
     261             :                   DMCUB_REGION5_ENABLE, 1);
     262             : 
     263           0 :         dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
     264             : 
     265           0 :         REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
     266           0 :         REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
     267           0 :         REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
     268           0 :         REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
     269             :                   DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
     270             :                   DMCUB_REGION3_CW6_ENABLE, 1);
     271           0 : }
     272             : 
     273           0 : void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
     274             :                               const struct dmub_region *inbox1)
     275             : {
     276             :         /* New firmware can support CW4 for the inbox. */
     277           0 :         if (dmub_dcn20_use_cached_inbox(dmub))
     278           0 :                 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
     279             :         else
     280           0 :                 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
     281             : 
     282           0 :         REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
     283           0 : }
     284             : 
     285           0 : uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
     286             : {
     287           0 :         return REG_READ(DMCUB_INBOX1_RPTR);
     288             : }
     289             : 
     290           0 : void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
     291             : {
     292           0 :         REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
     293           0 : }
     294             : 
     295           0 : void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,
     296             :                               const struct dmub_region *outbox1)
     297             : {
     298             :         /* New firmware can support CW4 for the outbox. */
     299           0 :         if (dmub_dcn20_use_cached_inbox(dmub))
     300           0 :                 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
     301             :         else
     302           0 :                 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000);
     303             : 
     304           0 :         REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
     305           0 : }
     306             : 
     307           0 : uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)
     308             : {
     309             :         /**
     310             :          * outbox1 wptr register is accessed without locks (dal & dc)
     311             :          * and to be called only by dmub_srv_stat_get_notification()
     312             :          */
     313           0 :         return REG_READ(DMCUB_OUTBOX1_WPTR);
     314             : }
     315             : 
     316           0 : void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
     317             : {
     318             :         /**
     319             :          * outbox1 rptr register is accessed without locks (dal & dc)
     320             :          * and to be called only by dmub_srv_stat_get_notification()
     321             :          */
     322           0 :         REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
     323           0 : }
     324             : 
     325           0 : void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,
     326             :                               const struct dmub_region *outbox0)
     327             : {
     328           0 :         REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
     329             : 
     330           0 :         REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
     331           0 : }
     332             : 
     333           0 : uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)
     334             : {
     335           0 :         return REG_READ(DMCUB_OUTBOX0_WPTR);
     336             : }
     337             : 
     338           0 : void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
     339             : {
     340           0 :         REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
     341           0 : }
     342             : 
     343           0 : bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
     344             : {
     345             :         uint32_t is_hw_init;
     346             : 
     347           0 :         REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
     348             : 
     349           0 :         return is_hw_init != 0;
     350             : }
     351             : 
     352           0 : bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
     353             : {
     354           0 :         uint32_t supported = 0;
     355             : 
     356           0 :         REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
     357             : 
     358           0 :         return supported;
     359             : }
     360             : 
     361           0 : void dmub_dcn20_set_gpint(struct dmub_srv *dmub,
     362             :                           union dmub_gpint_data_register reg)
     363             : {
     364           0 :         REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
     365           0 : }
     366             : 
     367           0 : bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
     368             :                                union dmub_gpint_data_register reg)
     369             : {
     370             :         union dmub_gpint_data_register test;
     371             : 
     372           0 :         reg.bits.status = 0;
     373           0 :         test.all = REG_READ(DMCUB_GPINT_DATAIN1);
     374             : 
     375           0 :         return test.all == reg.all;
     376             : }
     377             : 
     378           0 : uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
     379             : {
     380           0 :         return REG_READ(DMCUB_SCRATCH7);
     381             : }
     382             : 
     383           0 : union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
     384             : {
     385             :         union dmub_fw_boot_status status;
     386             : 
     387           0 :         status.all = REG_READ(DMCUB_SCRATCH0);
     388           0 :         return status;
     389             : }
     390             : 
     391           0 : void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
     392             : {
     393           0 :         union dmub_fw_boot_options boot_options = {0};
     394             : 
     395           0 :         REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
     396           0 : }
     397             : 
     398           0 : void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
     399             : {
     400             :         union dmub_fw_boot_options boot_options;
     401           0 :         boot_options.all = REG_READ(DMCUB_SCRATCH14);
     402           0 :         boot_options.bits.skip_phy_init_panel_sequence = skip;
     403           0 :         REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
     404           0 : }
     405             : 
     406           0 : uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)
     407             : {
     408           0 :         return REG_READ(DMCUB_TIMER_CURRENT);
     409             : }
     410             : 
     411           0 : void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
     412             : {
     413             :         uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
     414             :         uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
     415             : 
     416           0 :         if (!dmub || !diag_data)
     417           0 :                 return;
     418             : 
     419           0 :         memset(diag_data, 0, sizeof(*diag_data));
     420             : 
     421           0 :         diag_data->dmcub_version = dmub->fw_version;
     422             : 
     423           0 :         diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
     424           0 :         diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
     425           0 :         diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
     426           0 :         diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
     427           0 :         diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
     428           0 :         diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
     429           0 :         diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
     430           0 :         diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
     431           0 :         diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
     432           0 :         diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
     433           0 :         diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
     434           0 :         diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
     435           0 :         diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
     436           0 :         diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
     437           0 :         diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
     438           0 :         diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
     439             : 
     440           0 :         diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
     441           0 :         diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
     442           0 :         diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
     443             : 
     444           0 :         diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
     445           0 :         diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
     446           0 :         diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
     447             : 
     448           0 :         diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
     449           0 :         diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
     450           0 :         diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
     451             : 
     452           0 :         REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
     453           0 :         diag_data->is_dmcub_enabled = is_dmub_enabled;
     454             : 
     455           0 :         REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
     456           0 :         diag_data->is_dmcub_soft_reset = is_soft_reset;
     457             : 
     458           0 :         REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
     459           0 :         diag_data->is_dmcub_secure_reset = is_sec_reset;
     460             : 
     461           0 :         REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
     462           0 :         diag_data->is_traceport_en  = is_traceport_enabled;
     463             : 
     464           0 :         REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
     465           0 :         diag_data->is_cw0_enabled = is_cw0_enabled;
     466             : 
     467           0 :         REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
     468           0 :         diag_data->is_cw6_enabled = is_cw6_enabled;
     469             : }