Line data Source code
1 : /*
2 : * Copyright 2019 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "../dmub_srv.h"
27 : #include "dmub_dcn20.h"
28 : #include "dmub_dcn21.h"
29 : #include "dmub_cmd.h"
30 : #include "dmub_dcn30.h"
31 : #include "dmub_dcn301.h"
32 : #include "dmub_dcn302.h"
33 : #include "dmub_dcn303.h"
34 : #include "dmub_dcn31.h"
35 : #include "dmub_dcn315.h"
36 : #include "dmub_dcn316.h"
37 : #include "dmub_dcn32.h"
38 : #include "os_types.h"
39 : /*
40 : * Note: the DMUB service is standalone. No additional headers should be
41 : * added below or above this line unless they reside within the DMUB
42 : * folder.
43 : */
44 :
45 : /* Alignment for framebuffer memory. */
46 : #define DMUB_FB_ALIGNMENT (1024 * 1024)
47 :
48 : /* Stack size. */
49 : #define DMUB_STACK_SIZE (128 * 1024)
50 :
51 : /* Context size. */
52 : #define DMUB_CONTEXT_SIZE (512 * 1024)
53 :
54 : /* Mailbox size : Ring buffers are required for both inbox and outbox */
55 : #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
56 :
57 : /* Default state size if meta is absent. */
58 : #define DMUB_FW_STATE_SIZE (64 * 1024)
59 :
60 : /* Default tracebuffer size if meta is absent. */
61 : #define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
62 :
63 :
64 : /* Default scratch mem size. */
65 : #define DMUB_SCRATCH_MEM_SIZE (256)
66 :
67 : /* Number of windows in use. */
68 : #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)
69 : /* Base addresses. */
70 :
71 : #define DMUB_CW0_BASE (0x60000000)
72 : #define DMUB_CW1_BASE (0x61000000)
73 : #define DMUB_CW3_BASE (0x63000000)
74 : #define DMUB_CW4_BASE (0x64000000)
75 : #define DMUB_CW5_BASE (0x65000000)
76 : #define DMUB_CW6_BASE (0x66000000)
77 :
78 : #define DMUB_REGION5_BASE (0xA0000000)
79 :
80 : static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
81 : {
82 0 : return (val + factor - 1) / factor * factor;
83 : }
84 :
85 0 : void dmub_flush_buffer_mem(const struct dmub_fb *fb)
86 : {
87 0 : const uint8_t *base = (const uint8_t *)fb->cpu_addr;
88 : uint8_t buf[64];
89 : uint32_t pos, end;
90 :
91 : /**
92 : * Read 64-byte chunks since we don't want to store a
93 : * large temporary buffer for this purpose.
94 : */
95 0 : end = fb->size / sizeof(buf) * sizeof(buf);
96 :
97 0 : for (pos = 0; pos < end; pos += sizeof(buf))
98 0 : dmub_memcpy(buf, base + pos, sizeof(buf));
99 :
100 : /* Read anything leftover into the buffer. */
101 0 : if (end < fb->size)
102 0 : dmub_memcpy(buf, base + pos, fb->size - end);
103 0 : }
104 :
105 : static const struct dmub_fw_meta_info *
106 : dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)
107 : {
108 : const union dmub_fw_meta *meta;
109 :
110 : if (!blob || !blob_size)
111 : return NULL;
112 :
113 0 : if (blob_size < sizeof(union dmub_fw_meta) + meta_offset)
114 : return NULL;
115 :
116 0 : meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset -
117 : sizeof(union dmub_fw_meta));
118 :
119 0 : if (meta->info.magic_value != DMUB_FW_META_MAGIC)
120 : return NULL;
121 :
122 0 : return &meta->info;
123 : }
124 :
125 : static const struct dmub_fw_meta_info *
126 0 : dmub_get_fw_meta_info(const struct dmub_srv_region_params *params)
127 : {
128 0 : const struct dmub_fw_meta_info *info = NULL;
129 :
130 0 : if (params->fw_bss_data && params->bss_data_size) {
131 : /* Legacy metadata region. */
132 0 : info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data,
133 : params->bss_data_size,
134 : DMUB_FW_META_OFFSET);
135 0 : } else if (params->fw_inst_const && params->inst_const_size) {
136 : /* Combined metadata region - can be aligned to 16-bytes. */
137 : uint32_t i;
138 :
139 0 : for (i = 0; i < 16; ++i) {
140 0 : info = dmub_get_fw_meta_info_from_blob(
141 : params->fw_inst_const, params->inst_const_size, i);
142 :
143 0 : if (info)
144 : break;
145 : }
146 : }
147 :
148 0 : return info;
149 : }
150 :
151 0 : static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
152 : {
153 0 : struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
154 :
155 : switch (asic) {
156 : case DMUB_ASIC_DCN20:
157 : case DMUB_ASIC_DCN21:
158 : case DMUB_ASIC_DCN30:
159 : case DMUB_ASIC_DCN301:
160 : case DMUB_ASIC_DCN302:
161 : case DMUB_ASIC_DCN303:
162 0 : dmub->regs = &dmub_srv_dcn20_regs;
163 :
164 0 : funcs->reset = dmub_dcn20_reset;
165 0 : funcs->reset_release = dmub_dcn20_reset_release;
166 0 : funcs->backdoor_load = dmub_dcn20_backdoor_load;
167 0 : funcs->setup_windows = dmub_dcn20_setup_windows;
168 0 : funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
169 0 : funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
170 0 : funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
171 0 : funcs->is_supported = dmub_dcn20_is_supported;
172 0 : funcs->is_hw_init = dmub_dcn20_is_hw_init;
173 0 : funcs->set_gpint = dmub_dcn20_set_gpint;
174 0 : funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
175 0 : funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
176 0 : funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
177 0 : funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
178 0 : funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
179 0 : funcs->get_current_time = dmub_dcn20_get_current_time;
180 :
181 : // Out mailbox register access functions for RN and above
182 0 : funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
183 0 : funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
184 0 : funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
185 :
186 : //outbox0 call stacks
187 0 : funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;
188 0 : funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
189 0 : funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
190 :
191 0 : funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
192 :
193 0 : if (asic == DMUB_ASIC_DCN21) {
194 0 : dmub->regs = &dmub_srv_dcn21_regs;
195 :
196 0 : funcs->is_phy_init = dmub_dcn21_is_phy_init;
197 : }
198 0 : if (asic == DMUB_ASIC_DCN30) {
199 0 : dmub->regs = &dmub_srv_dcn30_regs;
200 :
201 0 : funcs->backdoor_load = dmub_dcn30_backdoor_load;
202 0 : funcs->setup_windows = dmub_dcn30_setup_windows;
203 : }
204 0 : if (asic == DMUB_ASIC_DCN301) {
205 0 : dmub->regs = &dmub_srv_dcn301_regs;
206 :
207 0 : funcs->backdoor_load = dmub_dcn30_backdoor_load;
208 0 : funcs->setup_windows = dmub_dcn30_setup_windows;
209 : }
210 0 : if (asic == DMUB_ASIC_DCN302) {
211 0 : dmub->regs = &dmub_srv_dcn302_regs;
212 :
213 0 : funcs->backdoor_load = dmub_dcn30_backdoor_load;
214 0 : funcs->setup_windows = dmub_dcn30_setup_windows;
215 : }
216 0 : if (asic == DMUB_ASIC_DCN303) {
217 0 : dmub->regs = &dmub_srv_dcn303_regs;
218 :
219 0 : funcs->backdoor_load = dmub_dcn30_backdoor_load;
220 0 : funcs->setup_windows = dmub_dcn30_setup_windows;
221 : }
222 : break;
223 :
224 : case DMUB_ASIC_DCN31:
225 : case DMUB_ASIC_DCN31B:
226 : case DMUB_ASIC_DCN314:
227 : case DMUB_ASIC_DCN315:
228 : case DMUB_ASIC_DCN316:
229 0 : if (asic == DMUB_ASIC_DCN315)
230 0 : dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
231 0 : else if (asic == DMUB_ASIC_DCN316)
232 0 : dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
233 : else
234 0 : dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
235 0 : funcs->reset = dmub_dcn31_reset;
236 0 : funcs->reset_release = dmub_dcn31_reset_release;
237 0 : funcs->backdoor_load = dmub_dcn31_backdoor_load;
238 0 : funcs->setup_windows = dmub_dcn31_setup_windows;
239 0 : funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
240 0 : funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
241 0 : funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
242 0 : funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
243 0 : funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
244 0 : funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
245 0 : funcs->is_supported = dmub_dcn31_is_supported;
246 0 : funcs->is_hw_init = dmub_dcn31_is_hw_init;
247 0 : funcs->set_gpint = dmub_dcn31_set_gpint;
248 0 : funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
249 0 : funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
250 0 : funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
251 0 : funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
252 0 : funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
253 0 : funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
254 : //outbox0 call stacks
255 0 : funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
256 0 : funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
257 0 : funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
258 :
259 0 : funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
260 0 : funcs->should_detect = dmub_dcn31_should_detect;
261 0 : funcs->get_current_time = dmub_dcn31_get_current_time;
262 :
263 0 : break;
264 :
265 : case DMUB_ASIC_DCN32:
266 : case DMUB_ASIC_DCN321:
267 0 : dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
268 0 : funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
269 0 : funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
270 0 : funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
271 0 : funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
272 0 : funcs->reset = dmub_dcn32_reset;
273 0 : funcs->reset_release = dmub_dcn32_reset_release;
274 0 : funcs->backdoor_load = dmub_dcn32_backdoor_load;
275 0 : funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
276 0 : funcs->setup_windows = dmub_dcn32_setup_windows;
277 0 : funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
278 0 : funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
279 0 : funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
280 0 : funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
281 0 : funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
282 0 : funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
283 0 : funcs->is_supported = dmub_dcn32_is_supported;
284 0 : funcs->is_hw_init = dmub_dcn32_is_hw_init;
285 0 : funcs->set_gpint = dmub_dcn32_set_gpint;
286 0 : funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
287 0 : funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
288 0 : funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
289 0 : funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
290 0 : funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
291 0 : funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
292 :
293 : /* outbox0 call stacks */
294 0 : funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
295 0 : funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
296 0 : funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
297 0 : funcs->get_current_time = dmub_dcn32_get_current_time;
298 0 : funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
299 :
300 0 : break;
301 :
302 : default:
303 : return false;
304 : }
305 :
306 : return true;
307 : }
308 :
309 0 : enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
310 : const struct dmub_srv_create_params *params)
311 : {
312 0 : enum dmub_status status = DMUB_STATUS_OK;
313 :
314 0 : dmub_memset(dmub, 0, sizeof(*dmub));
315 :
316 0 : dmub->funcs = params->funcs;
317 0 : dmub->user_ctx = params->user_ctx;
318 0 : dmub->asic = params->asic;
319 0 : dmub->fw_version = params->fw_version;
320 0 : dmub->is_virtual = params->is_virtual;
321 :
322 : /* Setup asic dependent hardware funcs. */
323 0 : if (!dmub_srv_hw_setup(dmub, params->asic)) {
324 : status = DMUB_STATUS_INVALID;
325 : goto cleanup;
326 : }
327 :
328 : /* Override (some) hardware funcs based on user params. */
329 0 : if (params->hw_funcs) {
330 0 : if (params->hw_funcs->emul_get_inbox1_rptr)
331 0 : dmub->hw_funcs.emul_get_inbox1_rptr =
332 : params->hw_funcs->emul_get_inbox1_rptr;
333 :
334 0 : if (params->hw_funcs->emul_set_inbox1_wptr)
335 0 : dmub->hw_funcs.emul_set_inbox1_wptr =
336 : params->hw_funcs->emul_set_inbox1_wptr;
337 :
338 0 : if (params->hw_funcs->is_supported)
339 0 : dmub->hw_funcs.is_supported =
340 : params->hw_funcs->is_supported;
341 : }
342 :
343 : /* Sanity checks for required hw func pointers. */
344 0 : if (!dmub->hw_funcs.get_inbox1_rptr ||
345 0 : !dmub->hw_funcs.set_inbox1_wptr) {
346 0 : status = DMUB_STATUS_INVALID;
347 0 : goto cleanup;
348 : }
349 :
350 : cleanup:
351 0 : if (status == DMUB_STATUS_OK)
352 0 : dmub->sw_init = true;
353 : else
354 : dmub_srv_destroy(dmub);
355 :
356 0 : return status;
357 : }
358 :
359 0 : void dmub_srv_destroy(struct dmub_srv *dmub)
360 : {
361 0 : dmub_memset(dmub, 0, sizeof(*dmub));
362 0 : }
363 :
364 : enum dmub_status
365 0 : dmub_srv_calc_region_info(struct dmub_srv *dmub,
366 : const struct dmub_srv_region_params *params,
367 : struct dmub_srv_region_info *out)
368 : {
369 0 : struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
370 0 : struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
371 0 : struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
372 0 : struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
373 0 : struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
374 0 : struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
375 0 : struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
376 0 : struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM];
377 : const struct dmub_fw_meta_info *fw_info;
378 0 : uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
379 0 : uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
380 0 : uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE;
381 :
382 0 : if (!dmub->sw_init)
383 : return DMUB_STATUS_INVALID;
384 :
385 0 : memset(out, 0, sizeof(*out));
386 :
387 0 : out->num_regions = DMUB_NUM_WINDOWS;
388 :
389 0 : inst->base = 0x0;
390 0 : inst->top = inst->base + params->inst_const_size;
391 :
392 0 : data->base = dmub_align(inst->top, 256);
393 0 : data->top = data->base + params->bss_data_size;
394 :
395 : /*
396 : * All cache windows below should be aligned to the size
397 : * of the DMCUB cache line, 64 bytes.
398 : */
399 :
400 0 : stack->base = dmub_align(data->top, 256);
401 0 : stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
402 :
403 0 : bios->base = dmub_align(stack->top, 256);
404 0 : bios->top = bios->base + params->vbios_size;
405 :
406 0 : mail->base = dmub_align(bios->top, 256);
407 0 : mail->top = mail->base + DMUB_MAILBOX_SIZE;
408 :
409 0 : fw_info = dmub_get_fw_meta_info(params);
410 :
411 0 : if (fw_info) {
412 0 : fw_state_size = fw_info->fw_region_size;
413 0 : trace_buffer_size = fw_info->trace_buffer_size;
414 :
415 : /**
416 : * If DM didn't fill in a version, then fill it in based on
417 : * the firmware meta now that we have it.
418 : *
419 : * TODO: Make it easier for driver to extract this out to
420 : * pass during creation.
421 : */
422 0 : if (dmub->fw_version == 0)
423 0 : dmub->fw_version = fw_info->fw_version;
424 : }
425 :
426 0 : trace_buff->base = dmub_align(mail->top, 256);
427 0 : trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
428 :
429 0 : fw_state->base = dmub_align(trace_buff->top, 256);
430 0 : fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
431 :
432 0 : scratch_mem->base = dmub_align(fw_state->top, 256);
433 0 : scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64);
434 :
435 0 : out->fb_size = dmub_align(scratch_mem->top, 4096);
436 :
437 0 : return DMUB_STATUS_OK;
438 : }
439 :
440 0 : enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
441 : const struct dmub_srv_fb_params *params,
442 : struct dmub_srv_fb_info *out)
443 : {
444 : uint8_t *cpu_base;
445 : uint64_t gpu_base;
446 : uint32_t i;
447 :
448 0 : if (!dmub->sw_init)
449 : return DMUB_STATUS_INVALID;
450 :
451 0 : memset(out, 0, sizeof(*out));
452 :
453 0 : if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
454 : return DMUB_STATUS_INVALID;
455 :
456 0 : cpu_base = (uint8_t *)params->cpu_addr;
457 0 : gpu_base = params->gpu_addr;
458 :
459 0 : for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
460 0 : const struct dmub_region *reg =
461 0 : ¶ms->region_info->regions[i];
462 :
463 0 : out->fb[i].cpu_addr = cpu_base + reg->base;
464 0 : out->fb[i].gpu_addr = gpu_base + reg->base;
465 0 : out->fb[i].size = reg->top - reg->base;
466 : }
467 :
468 0 : out->num_fb = DMUB_NUM_WINDOWS;
469 :
470 0 : return DMUB_STATUS_OK;
471 : }
472 :
473 0 : enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
474 : bool *is_supported)
475 : {
476 0 : *is_supported = false;
477 :
478 0 : if (!dmub->sw_init)
479 : return DMUB_STATUS_INVALID;
480 :
481 0 : if (dmub->hw_funcs.is_supported)
482 0 : *is_supported = dmub->hw_funcs.is_supported(dmub);
483 :
484 : return DMUB_STATUS_OK;
485 : }
486 :
487 0 : enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
488 : {
489 0 : *is_hw_init = false;
490 :
491 0 : if (!dmub->sw_init)
492 : return DMUB_STATUS_INVALID;
493 :
494 0 : if (!dmub->hw_init)
495 : return DMUB_STATUS_OK;
496 :
497 0 : if (dmub->hw_funcs.is_hw_init)
498 0 : *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
499 :
500 : return DMUB_STATUS_OK;
501 : }
502 :
503 0 : enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
504 : const struct dmub_srv_hw_params *params)
505 : {
506 0 : struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
507 0 : struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
508 0 : struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
509 0 : struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
510 0 : struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
511 0 : struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
512 0 : struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
513 0 : struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
514 :
515 : struct dmub_rb_init_params rb_params, outbox0_rb_params;
516 : struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
517 : struct dmub_region inbox1, outbox1, outbox0;
518 :
519 0 : if (!dmub->sw_init)
520 : return DMUB_STATUS_INVALID;
521 :
522 0 : if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
523 0 : !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
524 0 : ASSERT(0);
525 : return DMUB_STATUS_INVALID;
526 : }
527 :
528 0 : dmub->fb_base = params->fb_base;
529 0 : dmub->fb_offset = params->fb_offset;
530 0 : dmub->psp_version = params->psp_version;
531 :
532 0 : if (dmub->hw_funcs.reset)
533 0 : dmub->hw_funcs.reset(dmub);
534 :
535 0 : cw0.offset.quad_part = inst_fb->gpu_addr;
536 0 : cw0.region.base = DMUB_CW0_BASE;
537 0 : cw0.region.top = cw0.region.base + inst_fb->size - 1;
538 :
539 0 : cw1.offset.quad_part = stack_fb->gpu_addr;
540 0 : cw1.region.base = DMUB_CW1_BASE;
541 0 : cw1.region.top = cw1.region.base + stack_fb->size - 1;
542 :
543 0 : if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
544 0 : dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
545 :
546 0 : if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
547 : /**
548 : * Read back all the instruction memory so we don't hang the
549 : * DMCUB when backdoor loading if the write from x86 hasn't been
550 : * flushed yet. This only occurs in backdoor loading.
551 : */
552 0 : dmub_flush_buffer_mem(inst_fb);
553 :
554 0 : if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
555 0 : dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
556 : else
557 0 : dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
558 : }
559 :
560 0 : cw2.offset.quad_part = data_fb->gpu_addr;
561 0 : cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
562 0 : cw2.region.top = cw2.region.base + data_fb->size;
563 :
564 0 : cw3.offset.quad_part = bios_fb->gpu_addr;
565 0 : cw3.region.base = DMUB_CW3_BASE;
566 0 : cw3.region.top = cw3.region.base + bios_fb->size;
567 :
568 0 : cw4.offset.quad_part = mail_fb->gpu_addr;
569 0 : cw4.region.base = DMUB_CW4_BASE;
570 0 : cw4.region.top = cw4.region.base + mail_fb->size;
571 :
572 : /**
573 : * Doubled the mailbox region to accomodate inbox and outbox.
574 : * Note: Currently, currently total mailbox size is 16KB. It is split
575 : * equally into 8KB between inbox and outbox. If this config is
576 : * changed, then uncached base address configuration of outbox1
577 : * has to be updated in funcs->setup_out_mailbox.
578 : */
579 0 : inbox1.base = cw4.region.base;
580 0 : inbox1.top = cw4.region.base + DMUB_RB_SIZE;
581 0 : outbox1.base = inbox1.top;
582 0 : outbox1.top = cw4.region.top;
583 :
584 0 : cw5.offset.quad_part = tracebuff_fb->gpu_addr;
585 0 : cw5.region.base = DMUB_CW5_BASE;
586 0 : cw5.region.top = cw5.region.base + tracebuff_fb->size;
587 :
588 0 : outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
589 0 : outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
590 :
591 0 : cw6.offset.quad_part = fw_state_fb->gpu_addr;
592 0 : cw6.region.base = DMUB_CW6_BASE;
593 0 : cw6.region.top = cw6.region.base + fw_state_fb->size;
594 :
595 0 : dmub->fw_state = fw_state_fb->cpu_addr;
596 :
597 0 : dmub->scratch_mem_fb = *scratch_mem_fb;
598 :
599 0 : if (dmub->hw_funcs.setup_windows)
600 0 : dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
601 :
602 0 : if (dmub->hw_funcs.setup_outbox0)
603 0 : dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
604 :
605 0 : if (dmub->hw_funcs.setup_mailbox)
606 0 : dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
607 0 : if (dmub->hw_funcs.setup_out_mailbox)
608 0 : dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
609 :
610 0 : dmub_memset(&rb_params, 0, sizeof(rb_params));
611 0 : rb_params.ctx = dmub;
612 0 : rb_params.base_address = mail_fb->cpu_addr;
613 0 : rb_params.capacity = DMUB_RB_SIZE;
614 0 : dmub_rb_init(&dmub->inbox1_rb, &rb_params);
615 :
616 : // Initialize outbox1 ring buffer
617 : rb_params.ctx = dmub;
618 0 : rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
619 : rb_params.capacity = DMUB_RB_SIZE;
620 0 : dmub_rb_init(&dmub->outbox1_rb, &rb_params);
621 :
622 0 : dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
623 0 : outbox0_rb_params.ctx = dmub;
624 0 : outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
625 0 : outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
626 0 : dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
627 :
628 : /* Report to DMUB what features are supported by current driver */
629 0 : if (dmub->hw_funcs.enable_dmub_boot_options)
630 0 : dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
631 :
632 0 : if (dmub->hw_funcs.skip_dmub_panel_power_sequence)
633 0 : dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
634 0 : params->skip_panel_power_sequence);
635 :
636 0 : if (dmub->hw_funcs.reset_release)
637 0 : dmub->hw_funcs.reset_release(dmub);
638 :
639 0 : dmub->hw_init = true;
640 :
641 0 : return DMUB_STATUS_OK;
642 : }
643 :
644 0 : enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
645 : {
646 0 : if (!dmub->sw_init)
647 : return DMUB_STATUS_INVALID;
648 :
649 0 : if (dmub->hw_funcs.reset)
650 0 : dmub->hw_funcs.reset(dmub);
651 :
652 0 : dmub->hw_init = false;
653 :
654 0 : return DMUB_STATUS_OK;
655 : }
656 :
657 0 : enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
658 : const union dmub_rb_cmd *cmd)
659 : {
660 0 : if (!dmub->hw_init)
661 : return DMUB_STATUS_INVALID;
662 :
663 0 : if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
664 : return DMUB_STATUS_OK;
665 :
666 0 : return DMUB_STATUS_QUEUE_FULL;
667 : }
668 :
669 0 : enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
670 : {
671 : struct dmub_rb flush_rb;
672 :
673 0 : if (!dmub->hw_init)
674 : return DMUB_STATUS_INVALID;
675 :
676 : /**
677 : * Read back all the queued commands to ensure that they've
678 : * been flushed to framebuffer memory. Otherwise DMCUB might
679 : * read back stale, fully invalid or partially invalid data.
680 : */
681 0 : flush_rb = dmub->inbox1_rb;
682 0 : flush_rb.rptr = dmub->inbox1_last_wptr;
683 0 : dmub_rb_flush_pending(&flush_rb);
684 :
685 0 : dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
686 :
687 0 : dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
688 :
689 0 : return DMUB_STATUS_OK;
690 : }
691 :
692 0 : enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
693 : uint32_t timeout_us)
694 : {
695 : uint32_t i;
696 :
697 0 : if (!dmub->hw_init)
698 : return DMUB_STATUS_INVALID;
699 :
700 0 : for (i = 0; i <= timeout_us; i += 100) {
701 0 : union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
702 :
703 0 : if (status.bits.dal_fw && status.bits.mailbox_rdy)
704 0 : return DMUB_STATUS_OK;
705 :
706 0 : udelay(100);
707 : }
708 :
709 : return DMUB_STATUS_TIMEOUT;
710 : }
711 :
712 0 : enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
713 : uint32_t timeout_us)
714 : {
715 0 : uint32_t i = 0;
716 :
717 0 : if (!dmub->hw_init)
718 : return DMUB_STATUS_INVALID;
719 :
720 0 : if (!dmub->hw_funcs.is_phy_init)
721 : return DMUB_STATUS_OK;
722 :
723 0 : for (i = 0; i <= timeout_us; i += 10) {
724 0 : if (dmub->hw_funcs.is_phy_init(dmub))
725 : return DMUB_STATUS_OK;
726 :
727 0 : udelay(10);
728 : }
729 :
730 : return DMUB_STATUS_TIMEOUT;
731 : }
732 :
733 0 : enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
734 : uint32_t timeout_us)
735 : {
736 : uint32_t i, rptr;
737 :
738 0 : if (!dmub->hw_init)
739 : return DMUB_STATUS_INVALID;
740 :
741 0 : for (i = 0; i <= timeout_us; ++i) {
742 0 : rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
743 :
744 0 : if (rptr > dmub->inbox1_rb.capacity)
745 : return DMUB_STATUS_HW_FAILURE;
746 :
747 0 : dmub->inbox1_rb.rptr = rptr;
748 :
749 0 : if (dmub_rb_empty(&dmub->inbox1_rb))
750 : return DMUB_STATUS_OK;
751 :
752 0 : udelay(1);
753 : }
754 :
755 : return DMUB_STATUS_TIMEOUT;
756 : }
757 :
758 : enum dmub_status
759 0 : dmub_srv_send_gpint_command(struct dmub_srv *dmub,
760 : enum dmub_gpint_command command_code,
761 : uint16_t param, uint32_t timeout_us)
762 : {
763 : union dmub_gpint_data_register reg;
764 : uint32_t i;
765 :
766 0 : if (!dmub->sw_init)
767 : return DMUB_STATUS_INVALID;
768 :
769 0 : if (!dmub->hw_funcs.set_gpint)
770 : return DMUB_STATUS_INVALID;
771 :
772 0 : if (!dmub->hw_funcs.is_gpint_acked)
773 : return DMUB_STATUS_INVALID;
774 :
775 0 : reg.bits.status = 1;
776 0 : reg.bits.command_code = command_code;
777 0 : reg.bits.param = param;
778 :
779 0 : dmub->hw_funcs.set_gpint(dmub, reg);
780 :
781 0 : for (i = 0; i < timeout_us; ++i) {
782 0 : udelay(1);
783 :
784 0 : if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
785 : return DMUB_STATUS_OK;
786 : }
787 :
788 : return DMUB_STATUS_TIMEOUT;
789 : }
790 :
791 0 : enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
792 : uint32_t *response)
793 : {
794 0 : *response = 0;
795 :
796 0 : if (!dmub->sw_init)
797 : return DMUB_STATUS_INVALID;
798 :
799 0 : if (!dmub->hw_funcs.get_gpint_response)
800 : return DMUB_STATUS_INVALID;
801 :
802 0 : *response = dmub->hw_funcs.get_gpint_response(dmub);
803 :
804 0 : return DMUB_STATUS_OK;
805 : }
806 :
807 0 : enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
808 : uint32_t *dataout)
809 : {
810 0 : *dataout = 0;
811 :
812 0 : if (!dmub->sw_init)
813 : return DMUB_STATUS_INVALID;
814 :
815 0 : if (!dmub->hw_funcs.get_gpint_dataout)
816 : return DMUB_STATUS_INVALID;
817 :
818 0 : *dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
819 :
820 0 : return DMUB_STATUS_OK;
821 : }
822 :
823 0 : enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
824 : union dmub_fw_boot_status *status)
825 : {
826 0 : status->all = 0;
827 :
828 0 : if (!dmub->sw_init)
829 : return DMUB_STATUS_INVALID;
830 :
831 0 : if (dmub->hw_funcs.get_fw_status)
832 0 : *status = dmub->hw_funcs.get_fw_status(dmub);
833 :
834 : return DMUB_STATUS_OK;
835 : }
836 :
837 0 : enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
838 : union dmub_rb_cmd *cmd)
839 : {
840 0 : enum dmub_status status = DMUB_STATUS_OK;
841 :
842 : // Queue command
843 0 : status = dmub_srv_cmd_queue(dmub, cmd);
844 :
845 0 : if (status != DMUB_STATUS_OK)
846 : return status;
847 :
848 : // Execute command
849 0 : status = dmub_srv_cmd_execute(dmub);
850 :
851 0 : if (status != DMUB_STATUS_OK)
852 : return status;
853 :
854 : // Wait for DMUB to process command
855 0 : status = dmub_srv_wait_for_idle(dmub, 100000);
856 :
857 0 : if (status != DMUB_STATUS_OK)
858 : return status;
859 :
860 : // Copy data back from ring buffer into command
861 0 : dmub_rb_get_return_data(&dmub->inbox1_rb, cmd);
862 :
863 0 : return status;
864 : }
865 :
866 : static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
867 : void *entry)
868 : {
869 0 : const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
870 0 : uint64_t *dst = (uint64_t *)entry;
871 : uint8_t i;
872 : uint8_t loop_count;
873 :
874 0 : if (rb->rptr == rb->wrpt)
875 : return false;
876 :
877 : loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t);
878 : // copying data
879 0 : for (i = 0; i < loop_count; i++)
880 0 : *dst++ = *src++;
881 :
882 0 : rb->rptr += sizeof(struct dmcub_trace_buf_entry);
883 :
884 0 : rb->rptr %= rb->capacity;
885 :
886 : return true;
887 : }
888 :
889 0 : bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
890 : {
891 0 : dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub);
892 :
893 0 : return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
894 : }
895 :
896 0 : bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
897 : {
898 0 : if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
899 : return false;
900 0 : dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
901 0 : return true;
902 : }
903 :
904 0 : bool dmub_srv_should_detect(struct dmub_srv *dmub)
905 : {
906 0 : if (!dmub->hw_init || !dmub->hw_funcs.should_detect)
907 : return false;
908 :
909 0 : return dmub->hw_funcs.should_detect(dmub);
910 : }
911 :
912 0 : enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
913 : {
914 0 : if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
915 : return DMUB_STATUS_INVALID;
916 :
917 0 : dmub->hw_funcs.clear_inbox0_ack_register(dmub);
918 0 : return DMUB_STATUS_OK;
919 : }
920 :
921 0 : enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)
922 : {
923 0 : uint32_t i = 0;
924 0 : uint32_t ack = 0;
925 :
926 0 : if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register)
927 : return DMUB_STATUS_INVALID;
928 :
929 0 : for (i = 0; i <= timeout_us; i++) {
930 0 : ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
931 0 : if (ack)
932 : return DMUB_STATUS_OK;
933 : }
934 : return DMUB_STATUS_TIMEOUT;
935 : }
936 :
937 0 : enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
938 : union dmub_inbox0_data_register data)
939 : {
940 0 : if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
941 : return DMUB_STATUS_INVALID;
942 :
943 0 : dmub->hw_funcs.send_inbox0_cmd(dmub, data);
944 0 : return DMUB_STATUS_OK;
945 : }
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