Line data Source code
1 : /*
2 : * Copyright 2016 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include <linux/module.h>
24 : #include <linux/pci.h>
25 : #include <linux/slab.h>
26 : #include <linux/fb.h>
27 :
28 : #include "vega10_processpptables.h"
29 : #include "ppatomfwctrl.h"
30 : #include "atomfirmware.h"
31 : #include "pp_debug.h"
32 : #include "cgs_common.h"
33 : #include "vega10_pptable.h"
34 :
35 : #define NUM_DSPCLK_LEVELS 8
36 : #define VEGA10_ENGINECLOCK_HARDMAX 198000
37 :
38 : static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
39 : enum phm_platform_caps cap)
40 : {
41 0 : if (enable)
42 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
43 : else
44 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
45 : }
46 :
47 0 : static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
48 : {
49 0 : int index = GetIndexIntoMasterDataTable(powerplayinfo);
50 :
51 : u16 size;
52 : u8 frev, crev;
53 0 : const void *table_address = hwmgr->soft_pp_table;
54 :
55 0 : if (!table_address) {
56 0 : table_address = (ATOM_Vega10_POWERPLAYTABLE *)
57 0 : smu_atom_get_data_table(hwmgr->adev, index,
58 : &size, &frev, &crev);
59 :
60 0 : hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
61 0 : hwmgr->soft_pp_table_size = size;
62 : }
63 :
64 0 : return table_address;
65 : }
66 :
67 0 : static int check_powerplay_tables(
68 : struct pp_hwmgr *hwmgr,
69 : const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
70 : {
71 : const ATOM_Vega10_State_Array *state_arrays;
72 :
73 0 : state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) +
74 0 : le16_to_cpu(powerplay_table->usStateArrayOffset));
75 :
76 0 : PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
77 : ATOM_Vega10_TABLE_REVISION_VEGA10),
78 : "Unsupported PPTable format!", return -1);
79 0 : PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
80 : "State table is not set!", return -1);
81 0 : PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
82 : "Invalid PowerPlay Table!", return -1);
83 0 : PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
84 : "Invalid PowerPlay Table!", return -1);
85 :
86 : return 0;
87 : }
88 :
89 0 : static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
90 : {
91 0 : set_hw_cap(
92 : hwmgr,
93 0 : 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY),
94 : PHM_PlatformCaps_PowerPlaySupport);
95 :
96 0 : set_hw_cap(
97 : hwmgr,
98 0 : 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
99 : PHM_PlatformCaps_BiosPowerSourceControl);
100 :
101 0 : set_hw_cap(
102 : hwmgr,
103 0 : 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC),
104 : PHM_PlatformCaps_AutomaticDCTransition);
105 :
106 0 : set_hw_cap(
107 : hwmgr,
108 0 : 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),
109 : PHM_PlatformCaps_BACO);
110 :
111 0 : set_hw_cap(
112 : hwmgr,
113 0 : 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
114 : PHM_PlatformCaps_CombinePCCWithThermalSignal);
115 :
116 0 : return 0;
117 : }
118 :
119 0 : static int init_thermal_controller(
120 : struct pp_hwmgr *hwmgr,
121 : const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
122 : {
123 : const ATOM_Vega10_Thermal_Controller *thermal_controller;
124 : const Vega10_PPTable_Generic_SubTable_Header *header;
125 : const ATOM_Vega10_Fan_Table *fan_table_v1;
126 : const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
127 : const ATOM_Vega10_Fan_Table_V3 *fan_table_v3;
128 :
129 0 : thermal_controller = (ATOM_Vega10_Thermal_Controller *)
130 0 : (((unsigned long)powerplay_table) +
131 0 : le16_to_cpu(powerplay_table->usThermalControllerOffset));
132 :
133 0 : PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
134 : "Thermal controller table not set!", return -EINVAL);
135 :
136 0 : hwmgr->thermal_controller.ucType = thermal_controller->ucType;
137 0 : hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
138 0 : hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
139 :
140 0 : hwmgr->thermal_controller.fanInfo.bNoFan =
141 0 : (0 != (thermal_controller->ucFanParameters &
142 : ATOM_VEGA10_PP_FANPARAMETERS_NOFAN));
143 :
144 0 : hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
145 0 : thermal_controller->ucFanParameters &
146 : ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
147 :
148 0 : hwmgr->thermal_controller.fanInfo.ulMinRPM =
149 0 : thermal_controller->ucFanMinRPM * 100UL;
150 0 : hwmgr->thermal_controller.fanInfo.ulMaxRPM =
151 0 : thermal_controller->ucFanMaxRPM * 100UL;
152 :
153 : hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
154 0 : = 100000;
155 :
156 0 : set_hw_cap(
157 : hwmgr,
158 : ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
159 : PHM_PlatformCaps_ThermalController);
160 :
161 0 : if (!powerplay_table->usFanTableOffset)
162 : return 0;
163 :
164 0 : header = (const Vega10_PPTable_Generic_SubTable_Header *)
165 0 : (((unsigned long)powerplay_table) +
166 0 : le16_to_cpu(powerplay_table->usFanTableOffset));
167 :
168 0 : if (header->ucRevId == 10) {
169 0 : fan_table_v1 = (ATOM_Vega10_Fan_Table *)header;
170 :
171 0 : PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
172 : "Invalid Input Fan Table!", return -EINVAL);
173 :
174 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
175 : PHM_PlatformCaps_MicrocodeFanControl);
176 :
177 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
178 0 : le16_to_cpu(fan_table_v1->usFanOutputSensitivity);
179 0 : hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
180 0 : le16_to_cpu(fan_table_v1->usFanRPMMax);
181 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
182 0 : le16_to_cpu(fan_table_v1->usThrottlingRPM);
183 0 : hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
184 0 : le16_to_cpu(fan_table_v1->usFanAcousticLimit);
185 0 : hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
186 0 : le16_to_cpu(fan_table_v1->usTargetTemperature);
187 0 : hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
188 0 : le16_to_cpu(fan_table_v1->usMinimumPWMLimit);
189 0 : hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
190 0 : le16_to_cpu(fan_table_v1->usTargetGfxClk);
191 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
192 0 : le16_to_cpu(fan_table_v1->usFanGainEdge);
193 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
194 0 : le16_to_cpu(fan_table_v1->usFanGainHotspot);
195 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
196 0 : le16_to_cpu(fan_table_v1->usFanGainLiquid);
197 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
198 0 : le16_to_cpu(fan_table_v1->usFanGainVrVddc);
199 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
200 0 : le16_to_cpu(fan_table_v1->usFanGainVrMvdd);
201 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
202 0 : le16_to_cpu(fan_table_v1->usFanGainPlx);
203 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
204 0 : le16_to_cpu(fan_table_v1->usFanGainHbm);
205 :
206 0 : hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
207 0 : fan_table_v1->ucEnableZeroRPM;
208 0 : hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
209 0 : le16_to_cpu(fan_table_v1->usFanStopTemperature);
210 0 : hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
211 0 : le16_to_cpu(fan_table_v1->usFanStartTemperature);
212 0 : } else if (header->ucRevId == 0xb) {
213 0 : fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header;
214 :
215 0 : hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
216 0 : fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
217 0 : hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL;
218 0 : hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL;
219 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
220 : PHM_PlatformCaps_MicrocodeFanControl);
221 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
222 0 : le16_to_cpu(fan_table_v2->usFanOutputSensitivity);
223 0 : hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
224 0 : fan_table_v2->ucFanMaxRPM * 100UL;
225 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
226 0 : le16_to_cpu(fan_table_v2->usThrottlingRPM);
227 0 : hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
228 0 : le16_to_cpu(fan_table_v2->usFanAcousticLimitRpm);
229 0 : hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
230 0 : le16_to_cpu(fan_table_v2->usTargetTemperature);
231 0 : hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
232 0 : le16_to_cpu(fan_table_v2->usMinimumPWMLimit);
233 0 : hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
234 0 : le16_to_cpu(fan_table_v2->usTargetGfxClk);
235 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
236 0 : le16_to_cpu(fan_table_v2->usFanGainEdge);
237 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
238 0 : le16_to_cpu(fan_table_v2->usFanGainHotspot);
239 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
240 0 : le16_to_cpu(fan_table_v2->usFanGainLiquid);
241 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
242 0 : le16_to_cpu(fan_table_v2->usFanGainVrVddc);
243 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
244 0 : le16_to_cpu(fan_table_v2->usFanGainVrMvdd);
245 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
246 0 : le16_to_cpu(fan_table_v2->usFanGainPlx);
247 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
248 0 : le16_to_cpu(fan_table_v2->usFanGainHbm);
249 :
250 0 : hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
251 0 : fan_table_v2->ucEnableZeroRPM;
252 0 : hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
253 0 : le16_to_cpu(fan_table_v2->usFanStopTemperature);
254 0 : hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
255 0 : le16_to_cpu(fan_table_v2->usFanStartTemperature);
256 0 : } else if (header->ucRevId > 0xb) {
257 0 : fan_table_v3 = (ATOM_Vega10_Fan_Table_V3 *)header;
258 :
259 0 : hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
260 0 : fan_table_v3->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
261 0 : hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v3->ucFanMinRPM * 100UL;
262 0 : hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v3->ucFanMaxRPM * 100UL;
263 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
264 : PHM_PlatformCaps_MicrocodeFanControl);
265 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
266 0 : le16_to_cpu(fan_table_v3->usFanOutputSensitivity);
267 0 : hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
268 0 : fan_table_v3->ucFanMaxRPM * 100UL;
269 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
270 0 : le16_to_cpu(fan_table_v3->usThrottlingRPM);
271 0 : hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
272 0 : le16_to_cpu(fan_table_v3->usFanAcousticLimitRpm);
273 0 : hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
274 0 : le16_to_cpu(fan_table_v3->usTargetTemperature);
275 0 : hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
276 0 : le16_to_cpu(fan_table_v3->usMinimumPWMLimit);
277 0 : hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
278 0 : le16_to_cpu(fan_table_v3->usTargetGfxClk);
279 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
280 0 : le16_to_cpu(fan_table_v3->usFanGainEdge);
281 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
282 0 : le16_to_cpu(fan_table_v3->usFanGainHotspot);
283 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
284 0 : le16_to_cpu(fan_table_v3->usFanGainLiquid);
285 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
286 0 : le16_to_cpu(fan_table_v3->usFanGainVrVddc);
287 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
288 0 : le16_to_cpu(fan_table_v3->usFanGainVrMvdd);
289 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
290 0 : le16_to_cpu(fan_table_v3->usFanGainPlx);
291 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
292 0 : le16_to_cpu(fan_table_v3->usFanGainHbm);
293 :
294 0 : hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
295 0 : fan_table_v3->ucEnableZeroRPM;
296 0 : hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
297 0 : le16_to_cpu(fan_table_v3->usFanStopTemperature);
298 0 : hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
299 0 : le16_to_cpu(fan_table_v3->usFanStartTemperature);
300 0 : hwmgr->thermal_controller.advanceFanControlParameters.usMGpuThrottlingRPMLimit =
301 0 : le16_to_cpu(fan_table_v3->usMGpuThrottlingRPM);
302 : }
303 :
304 : return 0;
305 : }
306 :
307 0 : static int init_over_drive_limits(
308 : struct pp_hwmgr *hwmgr,
309 : const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
310 : {
311 0 : const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
312 : (const ATOM_Vega10_GFXCLK_Dependency_Table *)
313 0 : (((unsigned long) powerplay_table) +
314 0 : le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
315 0 : bool is_acg_enabled = false;
316 : ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
317 :
318 0 : if (gfxclk_dep_table->ucRevId == 1) {
319 0 : patom_record_v2 =
320 : (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
321 0 : is_acg_enabled =
322 0 : (bool)patom_record_v2[gfxclk_dep_table->ucNumEntries-1].ucACGEnable;
323 : }
324 :
325 0 : if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX &&
326 : !is_acg_enabled)
327 0 : hwmgr->platform_descriptor.overdriveLimit.engineClock =
328 : VEGA10_ENGINECLOCK_HARDMAX;
329 : else
330 0 : hwmgr->platform_descriptor.overdriveLimit.engineClock =
331 : le32_to_cpu(powerplay_table->ulMaxODEngineClock);
332 0 : hwmgr->platform_descriptor.overdriveLimit.memoryClock =
333 0 : le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
334 :
335 0 : hwmgr->platform_descriptor.minOverdriveVDDC = 0;
336 0 : hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
337 0 : hwmgr->platform_descriptor.overdriveVDDCStep = 0;
338 :
339 0 : return 0;
340 : }
341 :
342 0 : static int get_mm_clock_voltage_table(
343 : struct pp_hwmgr *hwmgr,
344 : phm_ppt_v1_mm_clock_voltage_dependency_table **vega10_mm_table,
345 : const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table)
346 : {
347 : uint32_t i;
348 : const ATOM_Vega10_MM_Dependency_Record *mm_dependency_record;
349 : phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
350 :
351 0 : PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),
352 : "Invalid PowerPlay Table!", return -1);
353 :
354 0 : mm_table = kzalloc(struct_size(mm_table, entries, mm_dependency_table->ucNumEntries),
355 : GFP_KERNEL);
356 0 : if (!mm_table)
357 : return -ENOMEM;
358 :
359 0 : mm_table->count = mm_dependency_table->ucNumEntries;
360 :
361 0 : for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
362 0 : mm_dependency_record = &mm_dependency_table->entries[i];
363 0 : mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd;
364 0 : mm_table->entries[i].samclock =
365 0 : le32_to_cpu(mm_dependency_record->ulPSPClk);
366 0 : mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk);
367 0 : mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk);
368 0 : mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk);
369 : }
370 :
371 0 : *vega10_mm_table = mm_table;
372 :
373 : return 0;
374 : }
375 :
376 0 : static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
377 : {
378 0 : switch(line){
379 : case Vega10_I2CLineID_DDC1:
380 0 : *scl = Vega10_I2C_DDC1CLK;
381 0 : *sda = Vega10_I2C_DDC1DATA;
382 0 : break;
383 : case Vega10_I2CLineID_DDC2:
384 0 : *scl = Vega10_I2C_DDC2CLK;
385 0 : *sda = Vega10_I2C_DDC2DATA;
386 0 : break;
387 : case Vega10_I2CLineID_DDC3:
388 0 : *scl = Vega10_I2C_DDC3CLK;
389 0 : *sda = Vega10_I2C_DDC3DATA;
390 0 : break;
391 : case Vega10_I2CLineID_DDC4:
392 0 : *scl = Vega10_I2C_DDC4CLK;
393 0 : *sda = Vega10_I2C_DDC4DATA;
394 0 : break;
395 : case Vega10_I2CLineID_DDC5:
396 0 : *scl = Vega10_I2C_DDC5CLK;
397 0 : *sda = Vega10_I2C_DDC5DATA;
398 0 : break;
399 : case Vega10_I2CLineID_DDC6:
400 0 : *scl = Vega10_I2C_DDC6CLK;
401 0 : *sda = Vega10_I2C_DDC6DATA;
402 0 : break;
403 : case Vega10_I2CLineID_SCLSDA:
404 0 : *scl = Vega10_I2C_SCL;
405 0 : *sda = Vega10_I2C_SDA;
406 0 : break;
407 : case Vega10_I2CLineID_DDCVGA:
408 0 : *scl = Vega10_I2C_DDCVGACLK;
409 0 : *sda = Vega10_I2C_DDCVGADATA;
410 0 : break;
411 : default:
412 0 : *scl = 0;
413 0 : *sda = 0;
414 0 : break;
415 : }
416 0 : }
417 :
418 0 : static int get_tdp_table(
419 : struct pp_hwmgr *hwmgr,
420 : struct phm_tdp_table **info_tdp_table,
421 : const Vega10_PPTable_Generic_SubTable_Header *table)
422 : {
423 : uint32_t table_size;
424 : struct phm_tdp_table *tdp_table;
425 : uint8_t scl;
426 : uint8_t sda;
427 : const ATOM_Vega10_PowerTune_Table *power_tune_table;
428 : const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2;
429 : const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3;
430 :
431 0 : table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table);
432 :
433 0 : tdp_table = kzalloc(table_size, GFP_KERNEL);
434 :
435 0 : if (!tdp_table)
436 : return -ENOMEM;
437 :
438 0 : if (table->ucRevId == 5) {
439 0 : power_tune_table = (ATOM_Vega10_PowerTune_Table *)table;
440 0 : tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit);
441 0 : tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit);
442 0 : tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit);
443 0 : tdp_table->usSoftwareShutdownTemp =
444 0 : le16_to_cpu(power_tune_table->usSoftwareShutdownTemp);
445 0 : tdp_table->usTemperatureLimitTedge =
446 0 : le16_to_cpu(power_tune_table->usTemperatureLimitTedge);
447 0 : tdp_table->usTemperatureLimitHotspot =
448 0 : le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot);
449 0 : tdp_table->usTemperatureLimitLiquid1 =
450 0 : le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1);
451 0 : tdp_table->usTemperatureLimitLiquid2 =
452 0 : le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2);
453 0 : tdp_table->usTemperatureLimitHBM =
454 0 : le16_to_cpu(power_tune_table->usTemperatureLimitHBM);
455 0 : tdp_table->usTemperatureLimitVrVddc =
456 0 : le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc);
457 0 : tdp_table->usTemperatureLimitVrMvdd =
458 0 : le16_to_cpu(power_tune_table->usTemperatureLimitVrMem);
459 0 : tdp_table->usTemperatureLimitPlx =
460 0 : le16_to_cpu(power_tune_table->usTemperatureLimitPlx);
461 0 : tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address;
462 0 : tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address;
463 0 : tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL;
464 0 : tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA;
465 0 : tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address;
466 0 : tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL;
467 0 : tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA;
468 0 : tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address;
469 0 : tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL;
470 0 : tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA;
471 0 : hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance);
472 0 : } else if (table->ucRevId == 6) {
473 0 : power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table;
474 0 : tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit);
475 0 : tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit);
476 0 : tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v2->usEdcLimit);
477 0 : tdp_table->usSoftwareShutdownTemp =
478 0 : le16_to_cpu(power_tune_table_v2->usSoftwareShutdownTemp);
479 0 : tdp_table->usTemperatureLimitTedge =
480 0 : le16_to_cpu(power_tune_table_v2->usTemperatureLimitTedge);
481 0 : tdp_table->usTemperatureLimitHotspot =
482 0 : le16_to_cpu(power_tune_table_v2->usTemperatureLimitHotSpot);
483 0 : tdp_table->usTemperatureLimitLiquid1 =
484 0 : le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid1);
485 0 : tdp_table->usTemperatureLimitLiquid2 =
486 0 : le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid2);
487 0 : tdp_table->usTemperatureLimitHBM =
488 0 : le16_to_cpu(power_tune_table_v2->usTemperatureLimitHBM);
489 0 : tdp_table->usTemperatureLimitVrVddc =
490 0 : le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrSoc);
491 0 : tdp_table->usTemperatureLimitVrMvdd =
492 0 : le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrMem);
493 0 : tdp_table->usTemperatureLimitPlx =
494 0 : le16_to_cpu(power_tune_table_v2->usTemperatureLimitPlx);
495 0 : tdp_table->ucLiquid1_I2C_address = power_tune_table_v2->ucLiquid1_I2C_address;
496 0 : tdp_table->ucLiquid2_I2C_address = power_tune_table_v2->ucLiquid2_I2C_address;
497 :
498 0 : get_scl_sda_value(power_tune_table_v2->ucLiquid_I2C_Line, &scl, &sda);
499 :
500 0 : tdp_table->ucLiquid_I2C_Line = scl;
501 0 : tdp_table->ucLiquid_I2C_LineSDA = sda;
502 :
503 0 : tdp_table->ucVr_I2C_address = power_tune_table_v2->ucVr_I2C_address;
504 :
505 0 : get_scl_sda_value(power_tune_table_v2->ucVr_I2C_Line, &scl, &sda);
506 :
507 0 : tdp_table->ucVr_I2C_Line = scl;
508 0 : tdp_table->ucVr_I2C_LineSDA = sda;
509 0 : tdp_table->ucPlx_I2C_address = power_tune_table_v2->ucPlx_I2C_address;
510 :
511 0 : get_scl_sda_value(power_tune_table_v2->ucPlx_I2C_Line, &scl, &sda);
512 :
513 0 : tdp_table->ucPlx_I2C_Line = scl;
514 0 : tdp_table->ucPlx_I2C_LineSDA = sda;
515 :
516 0 : hwmgr->platform_descriptor.LoadLineSlope =
517 0 : le16_to_cpu(power_tune_table_v2->usLoadLineResistance);
518 : } else {
519 0 : power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table;
520 0 : tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v3->usSocketPowerLimit);
521 0 : tdp_table->usTDC = le16_to_cpu(power_tune_table_v3->usTdcLimit);
522 0 : tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v3->usEdcLimit);
523 0 : tdp_table->usSoftwareShutdownTemp = le16_to_cpu(power_tune_table_v3->usSoftwareShutdownTemp);
524 0 : tdp_table->usTemperatureLimitTedge = le16_to_cpu(power_tune_table_v3->usTemperatureLimitTedge);
525 0 : tdp_table->usTemperatureLimitHotspot = le16_to_cpu(power_tune_table_v3->usTemperatureLimitHotSpot);
526 0 : tdp_table->usTemperatureLimitLiquid1 = le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid1);
527 0 : tdp_table->usTemperatureLimitLiquid2 = le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid2);
528 0 : tdp_table->usTemperatureLimitHBM = le16_to_cpu(power_tune_table_v3->usTemperatureLimitHBM);
529 0 : tdp_table->usTemperatureLimitVrVddc = le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrSoc);
530 0 : tdp_table->usTemperatureLimitVrMvdd = le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrMem);
531 0 : tdp_table->usTemperatureLimitPlx = le16_to_cpu(power_tune_table_v3->usTemperatureLimitPlx);
532 0 : tdp_table->ucLiquid1_I2C_address = power_tune_table_v3->ucLiquid1_I2C_address;
533 0 : tdp_table->ucLiquid2_I2C_address = power_tune_table_v3->ucLiquid2_I2C_address;
534 0 : tdp_table->usBoostStartTemperature = le16_to_cpu(power_tune_table_v3->usBoostStartTemperature);
535 0 : tdp_table->usBoostStopTemperature = le16_to_cpu(power_tune_table_v3->usBoostStopTemperature);
536 0 : tdp_table->ulBoostClock = le32_to_cpu(power_tune_table_v3->ulBoostClock);
537 :
538 0 : get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda);
539 :
540 0 : tdp_table->ucLiquid_I2C_Line = scl;
541 0 : tdp_table->ucLiquid_I2C_LineSDA = sda;
542 :
543 0 : tdp_table->ucVr_I2C_address = power_tune_table_v3->ucVr_I2C_address;
544 :
545 0 : get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda);
546 :
547 0 : tdp_table->ucVr_I2C_Line = scl;
548 0 : tdp_table->ucVr_I2C_LineSDA = sda;
549 :
550 0 : tdp_table->ucPlx_I2C_address = power_tune_table_v3->ucPlx_I2C_address;
551 :
552 0 : get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda);
553 :
554 0 : tdp_table->ucPlx_I2C_Line = scl;
555 0 : tdp_table->ucPlx_I2C_LineSDA = sda;
556 :
557 0 : hwmgr->platform_descriptor.LoadLineSlope =
558 0 : le16_to_cpu(power_tune_table_v3->usLoadLineResistance);
559 : }
560 :
561 0 : *info_tdp_table = tdp_table;
562 :
563 : return 0;
564 : }
565 :
566 0 : static int get_socclk_voltage_dependency_table(
567 : struct pp_hwmgr *hwmgr,
568 : phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_clk_dep_table,
569 : const ATOM_Vega10_SOCCLK_Dependency_Table *clk_dep_table)
570 : {
571 : uint32_t i;
572 : phm_ppt_v1_clock_voltage_dependency_table *clk_table;
573 :
574 0 : PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,
575 : "Invalid PowerPlay Table!", return -1);
576 :
577 0 : clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
578 : GFP_KERNEL);
579 0 : if (!clk_table)
580 : return -ENOMEM;
581 :
582 0 : clk_table->count = (uint32_t)clk_dep_table->ucNumEntries;
583 :
584 0 : for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
585 0 : clk_table->entries[i].vddInd =
586 0 : clk_dep_table->entries[i].ucVddInd;
587 0 : clk_table->entries[i].clk =
588 0 : le32_to_cpu(clk_dep_table->entries[i].ulClk);
589 : }
590 :
591 0 : *pp_vega10_clk_dep_table = clk_table;
592 :
593 : return 0;
594 : }
595 :
596 0 : static int get_mclk_voltage_dependency_table(
597 : struct pp_hwmgr *hwmgr,
598 : phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_mclk_dep_table,
599 : const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table)
600 : {
601 : uint32_t i;
602 : phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
603 :
604 0 : PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,
605 : "Invalid PowerPlay Table!", return -1);
606 :
607 0 : mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries),
608 : GFP_KERNEL);
609 0 : if (!mclk_table)
610 : return -ENOMEM;
611 :
612 0 : mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
613 :
614 0 : for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
615 0 : mclk_table->entries[i].vddInd =
616 0 : mclk_dep_table->entries[i].ucVddInd;
617 0 : mclk_table->entries[i].vddciInd =
618 0 : mclk_dep_table->entries[i].ucVddciInd;
619 0 : mclk_table->entries[i].mvddInd =
620 0 : mclk_dep_table->entries[i].ucVddMemInd;
621 0 : mclk_table->entries[i].clk =
622 0 : le32_to_cpu(mclk_dep_table->entries[i].ulMemClk);
623 : }
624 :
625 0 : *pp_vega10_mclk_dep_table = mclk_table;
626 :
627 : return 0;
628 : }
629 :
630 0 : static int get_gfxclk_voltage_dependency_table(
631 : struct pp_hwmgr *hwmgr,
632 : struct phm_ppt_v1_clock_voltage_dependency_table
633 : **pp_vega10_clk_dep_table,
634 : const ATOM_Vega10_GFXCLK_Dependency_Table *clk_dep_table)
635 : {
636 : uint32_t i;
637 : struct phm_ppt_v1_clock_voltage_dependency_table
638 : *clk_table;
639 : ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
640 :
641 0 : PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
642 : "Invalid PowerPlay Table!", return -1);
643 :
644 0 : clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
645 : GFP_KERNEL);
646 0 : if (!clk_table)
647 : return -ENOMEM;
648 :
649 0 : clk_table->count = clk_dep_table->ucNumEntries;
650 :
651 0 : if (clk_dep_table->ucRevId == 0) {
652 0 : for (i = 0; i < clk_table->count; i++) {
653 0 : clk_table->entries[i].vddInd =
654 0 : clk_dep_table->entries[i].ucVddInd;
655 0 : clk_table->entries[i].clk =
656 0 : le32_to_cpu(clk_dep_table->entries[i].ulClk);
657 0 : clk_table->entries[i].cks_enable =
658 0 : (((le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x8000)
659 0 : >> 15) == 0) ? 1 : 0;
660 0 : clk_table->entries[i].cks_voffset =
661 0 : le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x7F;
662 0 : clk_table->entries[i].sclk_offset =
663 0 : le16_to_cpu(clk_dep_table->entries[i].usAVFSOffset);
664 : }
665 0 : } else if (clk_dep_table->ucRevId == 1) {
666 0 : patom_record_v2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)clk_dep_table->entries;
667 0 : for (i = 0; i < clk_table->count; i++) {
668 0 : clk_table->entries[i].vddInd =
669 0 : patom_record_v2->ucVddInd;
670 0 : clk_table->entries[i].clk =
671 0 : le32_to_cpu(patom_record_v2->ulClk);
672 0 : clk_table->entries[i].cks_enable =
673 0 : (((le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x8000)
674 0 : >> 15) == 0) ? 1 : 0;
675 0 : clk_table->entries[i].cks_voffset =
676 0 : le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x7F;
677 0 : clk_table->entries[i].sclk_offset =
678 0 : le16_to_cpu(patom_record_v2->usAVFSOffset);
679 0 : patom_record_v2++;
680 : }
681 : } else {
682 0 : kfree(clk_table);
683 0 : PP_ASSERT_WITH_CODE(false,
684 : "Unsupported GFXClockDependencyTable Revision!",
685 : return -EINVAL);
686 : }
687 :
688 0 : *pp_vega10_clk_dep_table = clk_table;
689 :
690 : return 0;
691 : }
692 :
693 0 : static int get_pix_clk_voltage_dependency_table(
694 : struct pp_hwmgr *hwmgr,
695 : struct phm_ppt_v1_clock_voltage_dependency_table
696 : **pp_vega10_clk_dep_table,
697 : const ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table)
698 : {
699 : uint32_t i;
700 : struct phm_ppt_v1_clock_voltage_dependency_table
701 : *clk_table;
702 :
703 0 : PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
704 : "Invalid PowerPlay Table!", return -1);
705 :
706 0 : clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
707 : GFP_KERNEL);
708 0 : if (!clk_table)
709 : return -ENOMEM;
710 :
711 0 : clk_table->count = clk_dep_table->ucNumEntries;
712 :
713 0 : for (i = 0; i < clk_table->count; i++) {
714 0 : clk_table->entries[i].vddInd =
715 0 : clk_dep_table->entries[i].ucVddInd;
716 0 : clk_table->entries[i].clk =
717 0 : le32_to_cpu(clk_dep_table->entries[i].ulClk);
718 : }
719 :
720 0 : *pp_vega10_clk_dep_table = clk_table;
721 :
722 : return 0;
723 : }
724 :
725 0 : static int get_dcefclk_voltage_dependency_table(
726 : struct pp_hwmgr *hwmgr,
727 : struct phm_ppt_v1_clock_voltage_dependency_table
728 : **pp_vega10_clk_dep_table,
729 : const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table)
730 : {
731 : uint32_t i;
732 : uint8_t num_entries;
733 : struct phm_ppt_v1_clock_voltage_dependency_table
734 : *clk_table;
735 : uint32_t dev_id;
736 : uint32_t rev_id;
737 0 : struct amdgpu_device *adev = hwmgr->adev;
738 :
739 0 : PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
740 : "Invalid PowerPlay Table!", return -1);
741 :
742 : /*
743 : * workaround needed to add another DPM level for pioneer cards
744 : * as VBIOS is locked down.
745 : * This DPM level was added to support 3DPM monitors @ 4K120Hz
746 : *
747 : */
748 0 : dev_id = adev->pdev->device;
749 0 : rev_id = adev->pdev->revision;
750 :
751 0 : if (dev_id == 0x6863 && rev_id == 0 &&
752 0 : clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)
753 0 : num_entries = clk_dep_table->ucNumEntries + 1 > NUM_DSPCLK_LEVELS ?
754 0 : NUM_DSPCLK_LEVELS : clk_dep_table->ucNumEntries + 1;
755 : else
756 : num_entries = clk_dep_table->ucNumEntries;
757 :
758 :
759 0 : clk_table = kzalloc(struct_size(clk_table, entries, num_entries),
760 : GFP_KERNEL);
761 0 : if (!clk_table)
762 : return -ENOMEM;
763 :
764 0 : clk_table->count = (uint32_t)num_entries;
765 :
766 0 : for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
767 0 : clk_table->entries[i].vddInd =
768 0 : clk_dep_table->entries[i].ucVddInd;
769 0 : clk_table->entries[i].clk =
770 0 : le32_to_cpu(clk_dep_table->entries[i].ulClk);
771 : }
772 :
773 0 : if (i < num_entries) {
774 0 : clk_table->entries[i].vddInd = clk_dep_table->entries[i-1].ucVddInd;
775 0 : clk_table->entries[i].clk = 90000;
776 : }
777 :
778 0 : *pp_vega10_clk_dep_table = clk_table;
779 :
780 : return 0;
781 : }
782 :
783 0 : static int get_pcie_table(struct pp_hwmgr *hwmgr,
784 : struct phm_ppt_v1_pcie_table **vega10_pcie_table,
785 : const Vega10_PPTable_Generic_SubTable_Header *table)
786 : {
787 : uint32_t i, pcie_count;
788 : struct phm_ppt_v1_pcie_table *pcie_table;
789 0 : struct phm_ppt_v2_information *table_info =
790 : (struct phm_ppt_v2_information *)(hwmgr->pptable);
791 0 : const ATOM_Vega10_PCIE_Table *atom_pcie_table =
792 : (ATOM_Vega10_PCIE_Table *)table;
793 :
794 0 : PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries,
795 : "Invalid PowerPlay Table!",
796 : return 0);
797 :
798 0 : pcie_table = kzalloc(struct_size(pcie_table, entries, atom_pcie_table->ucNumEntries),
799 : GFP_KERNEL);
800 0 : if (!pcie_table)
801 : return -ENOMEM;
802 :
803 0 : pcie_count = table_info->vdd_dep_on_sclk->count;
804 0 : if (atom_pcie_table->ucNumEntries <= pcie_count)
805 : pcie_count = atom_pcie_table->ucNumEntries;
806 : else
807 0 : pr_info("Number of Pcie Entries exceed the number of"
808 : " GFXCLK Dpm Levels!"
809 : " Disregarding the excess entries...\n");
810 :
811 0 : pcie_table->count = pcie_count;
812 :
813 0 : for (i = 0; i < pcie_count; i++) {
814 0 : pcie_table->entries[i].gen_speed =
815 0 : atom_pcie_table->entries[i].ucPCIEGenSpeed;
816 0 : pcie_table->entries[i].lane_width =
817 0 : atom_pcie_table->entries[i].ucPCIELaneWidth;
818 0 : pcie_table->entries[i].pcie_sclk =
819 0 : atom_pcie_table->entries[i].ulLCLK;
820 : }
821 :
822 0 : *vega10_pcie_table = pcie_table;
823 :
824 : return 0;
825 : }
826 :
827 0 : static int get_hard_limits(
828 : struct pp_hwmgr *hwmgr,
829 : struct phm_clock_and_voltage_limits *limits,
830 : const ATOM_Vega10_Hard_Limit_Table *limit_table)
831 : {
832 0 : PP_ASSERT_WITH_CODE(limit_table->ucNumEntries,
833 : "Invalid PowerPlay Table!", return -1);
834 :
835 : /* currently we always take entries[0] parameters */
836 0 : limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit);
837 0 : limits->mclk = le32_to_cpu(limit_table->entries[0].ulMCLKLimit);
838 0 : limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit);
839 0 : limits->vddc = le16_to_cpu(limit_table->entries[0].usVddcLimit);
840 0 : limits->vddci = le16_to_cpu(limit_table->entries[0].usVddciLimit);
841 0 : limits->vddmem = le16_to_cpu(limit_table->entries[0].usVddMemLimit);
842 :
843 : return 0;
844 : }
845 :
846 0 : static int get_valid_clk(
847 : struct pp_hwmgr *hwmgr,
848 : struct phm_clock_array **clk_table,
849 : const phm_ppt_v1_clock_voltage_dependency_table *clk_volt_pp_table)
850 : {
851 : uint32_t i;
852 : struct phm_clock_array *table;
853 :
854 0 : PP_ASSERT_WITH_CODE(clk_volt_pp_table->count,
855 : "Invalid PowerPlay Table!", return -1);
856 :
857 0 : table = kzalloc(struct_size(table, values, clk_volt_pp_table->count),
858 : GFP_KERNEL);
859 0 : if (!table)
860 : return -ENOMEM;
861 :
862 0 : table->count = (uint32_t)clk_volt_pp_table->count;
863 :
864 0 : for (i = 0; i < table->count; i++)
865 0 : table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;
866 :
867 0 : *clk_table = table;
868 :
869 : return 0;
870 : }
871 :
872 0 : static int init_powerplay_extended_tables(
873 : struct pp_hwmgr *hwmgr,
874 : const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
875 : {
876 0 : int result = 0;
877 0 : struct phm_ppt_v2_information *pp_table_info =
878 : (struct phm_ppt_v2_information *)(hwmgr->pptable);
879 :
880 0 : const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table =
881 : (const ATOM_Vega10_MM_Dependency_Table *)
882 0 : (((unsigned long) powerplay_table) +
883 0 : le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
884 0 : const Vega10_PPTable_Generic_SubTable_Header *power_tune_table =
885 : (const Vega10_PPTable_Generic_SubTable_Header *)
886 0 : (((unsigned long) powerplay_table) +
887 0 : le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
888 0 : const ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
889 : (const ATOM_Vega10_SOCCLK_Dependency_Table *)
890 0 : (((unsigned long) powerplay_table) +
891 0 : le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
892 0 : const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
893 : (const ATOM_Vega10_GFXCLK_Dependency_Table *)
894 0 : (((unsigned long) powerplay_table) +
895 0 : le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
896 0 : const ATOM_Vega10_DCEFCLK_Dependency_Table *dcefclk_dep_table =
897 : (const ATOM_Vega10_DCEFCLK_Dependency_Table *)
898 0 : (((unsigned long) powerplay_table) +
899 0 : le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset));
900 0 : const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
901 : (const ATOM_Vega10_MCLK_Dependency_Table *)
902 0 : (((unsigned long) powerplay_table) +
903 0 : le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
904 0 : const ATOM_Vega10_Hard_Limit_Table *hard_limits =
905 : (const ATOM_Vega10_Hard_Limit_Table *)
906 0 : (((unsigned long) powerplay_table) +
907 0 : le16_to_cpu(powerplay_table->usHardLimitTableOffset));
908 0 : const Vega10_PPTable_Generic_SubTable_Header *pcie_table =
909 : (const Vega10_PPTable_Generic_SubTable_Header *)
910 0 : (((unsigned long) powerplay_table) +
911 0 : le16_to_cpu(powerplay_table->usPCIETableOffset));
912 0 : const ATOM_Vega10_PIXCLK_Dependency_Table *pixclk_dep_table =
913 : (const ATOM_Vega10_PIXCLK_Dependency_Table *)
914 0 : (((unsigned long) powerplay_table) +
915 0 : le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset));
916 0 : const ATOM_Vega10_PHYCLK_Dependency_Table *phyclk_dep_table =
917 : (const ATOM_Vega10_PHYCLK_Dependency_Table *)
918 0 : (((unsigned long) powerplay_table) +
919 0 : le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset));
920 0 : const ATOM_Vega10_DISPCLK_Dependency_Table *dispclk_dep_table =
921 : (const ATOM_Vega10_DISPCLK_Dependency_Table *)
922 0 : (((unsigned long) powerplay_table) +
923 0 : le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset));
924 :
925 0 : pp_table_info->vdd_dep_on_socclk = NULL;
926 0 : pp_table_info->vdd_dep_on_sclk = NULL;
927 0 : pp_table_info->vdd_dep_on_mclk = NULL;
928 0 : pp_table_info->vdd_dep_on_dcefclk = NULL;
929 0 : pp_table_info->mm_dep_table = NULL;
930 0 : pp_table_info->tdp_table = NULL;
931 0 : pp_table_info->vdd_dep_on_pixclk = NULL;
932 0 : pp_table_info->vdd_dep_on_phyclk = NULL;
933 0 : pp_table_info->vdd_dep_on_dispclk = NULL;
934 :
935 0 : if (powerplay_table->usMMDependencyTableOffset)
936 0 : result = get_mm_clock_voltage_table(hwmgr,
937 0 : &pp_table_info->mm_dep_table,
938 : mm_dependency_table);
939 :
940 0 : if (!result && powerplay_table->usPowerTuneTableOffset)
941 0 : result = get_tdp_table(hwmgr,
942 : &pp_table_info->tdp_table,
943 : power_tune_table);
944 :
945 0 : if (!result && powerplay_table->usSocclkDependencyTableOffset)
946 0 : result = get_socclk_voltage_dependency_table(hwmgr,
947 0 : &pp_table_info->vdd_dep_on_socclk,
948 : socclk_dep_table);
949 :
950 0 : if (!result && powerplay_table->usGfxclkDependencyTableOffset)
951 0 : result = get_gfxclk_voltage_dependency_table(hwmgr,
952 : &pp_table_info->vdd_dep_on_sclk,
953 : gfxclk_dep_table);
954 :
955 0 : if (!result && powerplay_table->usPixclkDependencyTableOffset)
956 0 : result = get_pix_clk_voltage_dependency_table(hwmgr,
957 : &pp_table_info->vdd_dep_on_pixclk,
958 : (const ATOM_Vega10_PIXCLK_Dependency_Table*)
959 : pixclk_dep_table);
960 :
961 0 : if (!result && powerplay_table->usPhyClkDependencyTableOffset)
962 0 : result = get_pix_clk_voltage_dependency_table(hwmgr,
963 : &pp_table_info->vdd_dep_on_phyclk,
964 : (const ATOM_Vega10_PIXCLK_Dependency_Table *)
965 : phyclk_dep_table);
966 :
967 0 : if (!result && powerplay_table->usDispClkDependencyTableOffset)
968 0 : result = get_pix_clk_voltage_dependency_table(hwmgr,
969 : &pp_table_info->vdd_dep_on_dispclk,
970 : (const ATOM_Vega10_PIXCLK_Dependency_Table *)
971 : dispclk_dep_table);
972 :
973 0 : if (!result && powerplay_table->usDcefclkDependencyTableOffset)
974 0 : result = get_dcefclk_voltage_dependency_table(hwmgr,
975 : &pp_table_info->vdd_dep_on_dcefclk,
976 : dcefclk_dep_table);
977 :
978 0 : if (!result && powerplay_table->usMclkDependencyTableOffset)
979 0 : result = get_mclk_voltage_dependency_table(hwmgr,
980 0 : &pp_table_info->vdd_dep_on_mclk,
981 : mclk_dep_table);
982 :
983 0 : if (!result && powerplay_table->usPCIETableOffset)
984 0 : result = get_pcie_table(hwmgr,
985 : &pp_table_info->pcie_table,
986 : pcie_table);
987 :
988 0 : if (!result && powerplay_table->usHardLimitTableOffset)
989 0 : result = get_hard_limits(hwmgr,
990 : &pp_table_info->max_clock_voltage_on_dc,
991 : hard_limits);
992 :
993 0 : hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
994 0 : pp_table_info->max_clock_voltage_on_dc.sclk;
995 0 : hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
996 0 : pp_table_info->max_clock_voltage_on_dc.mclk;
997 0 : hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
998 0 : pp_table_info->max_clock_voltage_on_dc.vddc;
999 0 : hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
1000 0 : pp_table_info->max_clock_voltage_on_dc.vddci;
1001 :
1002 0 : if (!result &&
1003 0 : pp_table_info->vdd_dep_on_socclk &&
1004 0 : pp_table_info->vdd_dep_on_socclk->count)
1005 0 : result = get_valid_clk(hwmgr,
1006 : &pp_table_info->valid_socclk_values,
1007 : pp_table_info->vdd_dep_on_socclk);
1008 :
1009 0 : if (!result &&
1010 0 : pp_table_info->vdd_dep_on_sclk &&
1011 0 : pp_table_info->vdd_dep_on_sclk->count)
1012 0 : result = get_valid_clk(hwmgr,
1013 : &pp_table_info->valid_sclk_values,
1014 : pp_table_info->vdd_dep_on_sclk);
1015 :
1016 0 : if (!result &&
1017 0 : pp_table_info->vdd_dep_on_dcefclk &&
1018 0 : pp_table_info->vdd_dep_on_dcefclk->count)
1019 0 : result = get_valid_clk(hwmgr,
1020 : &pp_table_info->valid_dcefclk_values,
1021 : pp_table_info->vdd_dep_on_dcefclk);
1022 :
1023 0 : if (!result &&
1024 0 : pp_table_info->vdd_dep_on_mclk &&
1025 0 : pp_table_info->vdd_dep_on_mclk->count)
1026 0 : result = get_valid_clk(hwmgr,
1027 : &pp_table_info->valid_mclk_values,
1028 : pp_table_info->vdd_dep_on_mclk);
1029 :
1030 0 : return result;
1031 : }
1032 :
1033 0 : static int get_vddc_lookup_table(
1034 : struct pp_hwmgr *hwmgr,
1035 : phm_ppt_v1_voltage_lookup_table **lookup_table,
1036 : const ATOM_Vega10_Voltage_Lookup_Table *vddc_lookup_pp_tables,
1037 : uint32_t max_levels)
1038 : {
1039 : uint32_t i;
1040 : phm_ppt_v1_voltage_lookup_table *table;
1041 :
1042 0 : PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0),
1043 : "Invalid SOC_VDDD Lookup Table!", return 1);
1044 :
1045 0 : table = kzalloc(struct_size(table, entries, max_levels), GFP_KERNEL);
1046 0 : if (!table)
1047 : return -ENOMEM;
1048 :
1049 0 : table->count = vddc_lookup_pp_tables->ucNumEntries;
1050 :
1051 0 : for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++)
1052 0 : table->entries[i].us_vdd =
1053 0 : le16_to_cpu(vddc_lookup_pp_tables->entries[i].usVdd);
1054 :
1055 0 : *lookup_table = table;
1056 :
1057 : return 0;
1058 : }
1059 :
1060 0 : static int init_dpm_2_parameters(
1061 : struct pp_hwmgr *hwmgr,
1062 : const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
1063 : {
1064 0 : int result = 0;
1065 0 : struct phm_ppt_v2_information *pp_table_info =
1066 : (struct phm_ppt_v2_information *)(hwmgr->pptable);
1067 0 : uint32_t disable_power_control = 0;
1068 :
1069 0 : pp_table_info->us_ulv_voltage_offset =
1070 0 : le16_to_cpu(powerplay_table->usUlvVoltageOffset);
1071 :
1072 0 : pp_table_info->us_ulv_smnclk_did =
1073 0 : le16_to_cpu(powerplay_table->usUlvSmnclkDid);
1074 0 : pp_table_info->us_ulv_mp1clk_did =
1075 0 : le16_to_cpu(powerplay_table->usUlvMp1clkDid);
1076 0 : pp_table_info->us_ulv_gfxclk_bypass =
1077 0 : le16_to_cpu(powerplay_table->usUlvGfxclkBypass);
1078 0 : pp_table_info->us_gfxclk_slew_rate =
1079 0 : le16_to_cpu(powerplay_table->usGfxclkSlewRate);
1080 0 : pp_table_info->uc_gfx_dpm_voltage_mode =
1081 0 : le16_to_cpu(powerplay_table->ucGfxVoltageMode);
1082 0 : pp_table_info->uc_soc_dpm_voltage_mode =
1083 0 : le16_to_cpu(powerplay_table->ucSocVoltageMode);
1084 0 : pp_table_info->uc_uclk_dpm_voltage_mode =
1085 0 : le16_to_cpu(powerplay_table->ucUclkVoltageMode);
1086 0 : pp_table_info->uc_uvd_dpm_voltage_mode =
1087 0 : le16_to_cpu(powerplay_table->ucUvdVoltageMode);
1088 0 : pp_table_info->uc_vce_dpm_voltage_mode =
1089 0 : le16_to_cpu(powerplay_table->ucVceVoltageMode);
1090 0 : pp_table_info->uc_mp0_dpm_voltage_mode =
1091 0 : le16_to_cpu(powerplay_table->ucMp0VoltageMode);
1092 0 : pp_table_info->uc_dcef_dpm_voltage_mode =
1093 0 : le16_to_cpu(powerplay_table->ucDcefVoltageMode);
1094 :
1095 0 : pp_table_info->ppm_parameter_table = NULL;
1096 0 : pp_table_info->vddc_lookup_table = NULL;
1097 0 : pp_table_info->vddmem_lookup_table = NULL;
1098 0 : pp_table_info->vddci_lookup_table = NULL;
1099 :
1100 : /* TDP limits */
1101 0 : hwmgr->platform_descriptor.TDPODLimit =
1102 0 : le16_to_cpu(powerplay_table->usPowerControlLimit);
1103 0 : hwmgr->platform_descriptor.TDPAdjustment = 0;
1104 0 : hwmgr->platform_descriptor.VidAdjustment = 0;
1105 0 : hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
1106 0 : hwmgr->platform_descriptor.VidMinLimit = 0;
1107 0 : hwmgr->platform_descriptor.VidMaxLimit = 1500000;
1108 0 : hwmgr->platform_descriptor.VidStep = 6250;
1109 :
1110 0 : disable_power_control = 0;
1111 : if (!disable_power_control) {
1112 : /* enable TDP overdrive (PowerControl) feature as well if supported */
1113 0 : if (hwmgr->platform_descriptor.TDPODLimit)
1114 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1115 : PHM_PlatformCaps_PowerControl);
1116 : }
1117 :
1118 0 : if (powerplay_table->usVddcLookupTableOffset) {
1119 0 : const ATOM_Vega10_Voltage_Lookup_Table *vddc_table =
1120 : (ATOM_Vega10_Voltage_Lookup_Table *)
1121 0 : (((unsigned long)powerplay_table) +
1122 0 : le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
1123 0 : result = get_vddc_lookup_table(hwmgr,
1124 0 : &pp_table_info->vddc_lookup_table, vddc_table, 8);
1125 : }
1126 :
1127 0 : if (powerplay_table->usVddmemLookupTableOffset) {
1128 0 : const ATOM_Vega10_Voltage_Lookup_Table *vdd_mem_table =
1129 : (ATOM_Vega10_Voltage_Lookup_Table *)
1130 0 : (((unsigned long)powerplay_table) +
1131 0 : le16_to_cpu(powerplay_table->usVddmemLookupTableOffset));
1132 0 : result = get_vddc_lookup_table(hwmgr,
1133 0 : &pp_table_info->vddmem_lookup_table, vdd_mem_table, 4);
1134 : }
1135 :
1136 0 : if (powerplay_table->usVddciLookupTableOffset) {
1137 0 : const ATOM_Vega10_Voltage_Lookup_Table *vddci_table =
1138 : (ATOM_Vega10_Voltage_Lookup_Table *)
1139 0 : (((unsigned long)powerplay_table) +
1140 0 : le16_to_cpu(powerplay_table->usVddciLookupTableOffset));
1141 0 : result = get_vddc_lookup_table(hwmgr,
1142 0 : &pp_table_info->vddci_lookup_table, vddci_table, 4);
1143 : }
1144 :
1145 0 : return result;
1146 : }
1147 :
1148 0 : static int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
1149 : {
1150 0 : int result = 0;
1151 : const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1152 :
1153 0 : hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
1154 :
1155 0 : PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
1156 : "Failed to allocate hwmgr->pptable!", return -ENOMEM);
1157 :
1158 0 : powerplay_table = get_powerplay_table(hwmgr);
1159 :
1160 0 : PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1161 : "Missing PowerPlay Table!", return -1);
1162 :
1163 0 : result = check_powerplay_tables(hwmgr, powerplay_table);
1164 :
1165 0 : PP_ASSERT_WITH_CODE((result == 0),
1166 : "check_powerplay_tables failed", return result);
1167 :
1168 0 : result = set_platform_caps(hwmgr,
1169 0 : le32_to_cpu(powerplay_table->ulPlatformCaps));
1170 :
1171 0 : PP_ASSERT_WITH_CODE((result == 0),
1172 : "set_platform_caps failed", return result);
1173 :
1174 0 : result = init_thermal_controller(hwmgr, powerplay_table);
1175 :
1176 0 : PP_ASSERT_WITH_CODE((result == 0),
1177 : "init_thermal_controller failed", return result);
1178 :
1179 0 : result = init_over_drive_limits(hwmgr, powerplay_table);
1180 :
1181 0 : PP_ASSERT_WITH_CODE((result == 0),
1182 : "init_over_drive_limits failed", return result);
1183 :
1184 0 : result = init_powerplay_extended_tables(hwmgr, powerplay_table);
1185 :
1186 0 : PP_ASSERT_WITH_CODE((result == 0),
1187 : "init_powerplay_extended_tables failed", return result);
1188 :
1189 0 : result = init_dpm_2_parameters(hwmgr, powerplay_table);
1190 :
1191 0 : PP_ASSERT_WITH_CODE((result == 0),
1192 : "init_dpm_2_parameters failed", return result);
1193 :
1194 : return result;
1195 : }
1196 :
1197 0 : static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
1198 : {
1199 0 : struct phm_ppt_v2_information *pp_table_info =
1200 : (struct phm_ppt_v2_information *)(hwmgr->pptable);
1201 :
1202 0 : kfree(pp_table_info->vdd_dep_on_sclk);
1203 0 : pp_table_info->vdd_dep_on_sclk = NULL;
1204 :
1205 0 : kfree(pp_table_info->vdd_dep_on_mclk);
1206 0 : pp_table_info->vdd_dep_on_mclk = NULL;
1207 :
1208 0 : kfree(pp_table_info->valid_mclk_values);
1209 0 : pp_table_info->valid_mclk_values = NULL;
1210 :
1211 0 : kfree(pp_table_info->valid_sclk_values);
1212 0 : pp_table_info->valid_sclk_values = NULL;
1213 :
1214 0 : kfree(pp_table_info->vddc_lookup_table);
1215 0 : pp_table_info->vddc_lookup_table = NULL;
1216 :
1217 0 : kfree(pp_table_info->vddmem_lookup_table);
1218 0 : pp_table_info->vddmem_lookup_table = NULL;
1219 :
1220 0 : kfree(pp_table_info->vddci_lookup_table);
1221 0 : pp_table_info->vddci_lookup_table = NULL;
1222 :
1223 0 : kfree(pp_table_info->ppm_parameter_table);
1224 0 : pp_table_info->ppm_parameter_table = NULL;
1225 :
1226 0 : kfree(pp_table_info->mm_dep_table);
1227 0 : pp_table_info->mm_dep_table = NULL;
1228 :
1229 0 : kfree(pp_table_info->cac_dtp_table);
1230 0 : pp_table_info->cac_dtp_table = NULL;
1231 :
1232 0 : kfree(hwmgr->dyn_state.cac_dtp_table);
1233 0 : hwmgr->dyn_state.cac_dtp_table = NULL;
1234 :
1235 0 : kfree(pp_table_info->tdp_table);
1236 0 : pp_table_info->tdp_table = NULL;
1237 :
1238 0 : kfree(hwmgr->pptable);
1239 0 : hwmgr->pptable = NULL;
1240 :
1241 0 : return 0;
1242 : }
1243 :
1244 : const struct pp_table_func vega10_pptable_funcs = {
1245 : .pptable_init = vega10_pp_tables_initialize,
1246 : .pptable_fini = vega10_pp_tables_uninitialize,
1247 : };
1248 :
1249 0 : int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
1250 : {
1251 : const ATOM_Vega10_State_Array *state_arrays;
1252 0 : const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1253 :
1254 0 : PP_ASSERT_WITH_CODE((pp_table != NULL),
1255 : "Missing PowerPlay Table!", return -1);
1256 0 : PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
1257 : ATOM_Vega10_TABLE_REVISION_VEGA10),
1258 : "Incorrect PowerPlay table revision!", return -1);
1259 :
1260 0 : state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)pp_table) +
1261 0 : le16_to_cpu(pp_table->usStateArrayOffset));
1262 :
1263 0 : return (uint32_t)(state_arrays->ucNumEntries);
1264 : }
1265 :
1266 0 : static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
1267 : uint16_t classification, uint16_t classification2)
1268 : {
1269 0 : uint32_t result = 0;
1270 :
1271 0 : if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
1272 0 : result |= PP_StateClassificationFlag_Boot;
1273 :
1274 0 : if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1275 0 : result |= PP_StateClassificationFlag_Thermal;
1276 :
1277 0 : if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
1278 0 : result |= PP_StateClassificationFlag_LimitedPowerSource;
1279 :
1280 0 : if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
1281 0 : result |= PP_StateClassificationFlag_Rest;
1282 :
1283 0 : if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
1284 0 : result |= PP_StateClassificationFlag_Forced;
1285 :
1286 0 : if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
1287 0 : result |= PP_StateClassificationFlag_ACPI;
1288 :
1289 0 : if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
1290 0 : result |= PP_StateClassificationFlag_LimitedPowerSource_2;
1291 :
1292 0 : return result;
1293 : }
1294 :
1295 0 : int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
1296 : uint32_t entry_index, struct pp_power_state *power_state,
1297 : int (*call_back_func)(struct pp_hwmgr *, void *,
1298 : struct pp_power_state *, void *, uint32_t))
1299 : {
1300 0 : int result = 0;
1301 : const ATOM_Vega10_State_Array *state_arrays;
1302 : const ATOM_Vega10_State *state_entry;
1303 0 : const ATOM_Vega10_POWERPLAYTABLE *pp_table =
1304 : get_powerplay_table(hwmgr);
1305 :
1306 0 : PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
1307 : return -1;);
1308 0 : power_state->classification.bios_index = entry_index;
1309 :
1310 0 : if (pp_table->sHeader.format_revision >=
1311 : ATOM_Vega10_TABLE_REVISION_VEGA10) {
1312 0 : state_arrays = (ATOM_Vega10_State_Array *)
1313 0 : (((unsigned long)pp_table) +
1314 0 : le16_to_cpu(pp_table->usStateArrayOffset));
1315 :
1316 0 : PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
1317 : "Invalid PowerPlay Table State Array Offset.",
1318 : return -1);
1319 0 : PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
1320 : "Invalid PowerPlay Table State Array.",
1321 : return -1);
1322 0 : PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
1323 : "Invalid PowerPlay Table State Array Entry.",
1324 : return -1);
1325 :
1326 0 : state_entry = &(state_arrays->states[entry_index]);
1327 :
1328 0 : result = call_back_func(hwmgr, (void *)state_entry, power_state,
1329 : (void *)pp_table,
1330 : make_classification_flags(hwmgr,
1331 0 : le16_to_cpu(state_entry->usClassification),
1332 0 : le16_to_cpu(state_entry->usClassification2)));
1333 : }
1334 :
1335 0 : if (!result && (power_state->classification.flags &
1336 : PP_StateClassificationFlag_Boot))
1337 0 : result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
1338 :
1339 : return result;
1340 : }
1341 :
1342 0 : int vega10_baco_set_cap(struct pp_hwmgr *hwmgr)
1343 : {
1344 0 : int result = 0;
1345 :
1346 : const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1347 :
1348 0 : powerplay_table = get_powerplay_table(hwmgr);
1349 :
1350 0 : PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1351 : "Missing PowerPlay Table!", return -1);
1352 :
1353 0 : result = check_powerplay_tables(hwmgr, powerplay_table);
1354 :
1355 0 : PP_ASSERT_WITH_CODE((result == 0),
1356 : "check_powerplay_tables failed", return result);
1357 :
1358 0 : set_hw_cap(
1359 : hwmgr,
1360 0 : 0 != (le32_to_cpu(powerplay_table->ulPlatformCaps) & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),
1361 : PHM_PlatformCaps_BACO);
1362 : return result;
1363 : }
1364 :
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