Line data Source code
1 : /*
2 : * Copyright 2017 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <linux/delay.h>
25 : #include <linux/fb.h>
26 : #include <linux/module.h>
27 : #include <linux/slab.h>
28 :
29 : #include "hwmgr.h"
30 : #include "amd_powerplay.h"
31 : #include "vega12_smumgr.h"
32 : #include "hardwaremanager.h"
33 : #include "ppatomfwctrl.h"
34 : #include "atomfirmware.h"
35 : #include "cgs_common.h"
36 : #include "vega12_inc.h"
37 : #include "pppcielanes.h"
38 : #include "vega12_hwmgr.h"
39 : #include "vega12_processpptables.h"
40 : #include "vega12_pptable.h"
41 : #include "vega12_thermal.h"
42 : #include "vega12_ppsmc.h"
43 : #include "pp_debug.h"
44 : #include "amd_pcie_helpers.h"
45 : #include "ppinterrupt.h"
46 : #include "pp_overdriver.h"
47 : #include "pp_thermal.h"
48 : #include "vega12_baco.h"
49 :
50 : #define smnPCIE_LC_SPEED_CNTL 0x11140290
51 : #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
52 :
53 : #define LINK_WIDTH_MAX 6
54 : #define LINK_SPEED_MAX 3
55 : static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
56 : static const int link_speed[] = {25, 50, 80, 160};
57 :
58 : static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
59 : enum pp_clock_type type, uint32_t mask);
60 : static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
61 : uint32_t *clock,
62 : PPCLK_e clock_select,
63 : bool max);
64 :
65 0 : static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
66 : {
67 0 : struct vega12_hwmgr *data =
68 : (struct vega12_hwmgr *)(hwmgr->backend);
69 :
70 0 : data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
71 0 : data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
72 0 : data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
73 0 : data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
74 0 : data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
75 :
76 0 : data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
77 0 : data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
78 0 : data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
79 0 : data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
80 0 : data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
81 0 : data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
82 0 : data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
83 0 : data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
84 0 : data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
85 0 : data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
86 0 : data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
87 0 : data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
88 0 : data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
89 :
90 0 : data->registry_data.disallowed_features = 0x0;
91 0 : data->registry_data.od_state_in_dc_support = 0;
92 0 : data->registry_data.thermal_support = 1;
93 0 : data->registry_data.skip_baco_hardware = 0;
94 :
95 0 : data->registry_data.log_avfs_param = 0;
96 0 : data->registry_data.sclk_throttle_low_notification = 1;
97 0 : data->registry_data.force_dpm_high = 0;
98 0 : data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
99 :
100 0 : data->registry_data.didt_support = 0;
101 : if (data->registry_data.didt_support) {
102 : data->registry_data.didt_mode = 6;
103 : data->registry_data.sq_ramping_support = 1;
104 : data->registry_data.db_ramping_support = 0;
105 : data->registry_data.td_ramping_support = 0;
106 : data->registry_data.tcp_ramping_support = 0;
107 : data->registry_data.dbr_ramping_support = 0;
108 : data->registry_data.edc_didt_support = 1;
109 : data->registry_data.gc_didt_support = 0;
110 : data->registry_data.psm_didt_support = 0;
111 : }
112 :
113 0 : data->registry_data.pcie_lane_override = 0xff;
114 0 : data->registry_data.pcie_speed_override = 0xff;
115 0 : data->registry_data.pcie_clock_override = 0xffffffff;
116 0 : data->registry_data.regulator_hot_gpio_support = 1;
117 0 : data->registry_data.ac_dc_switch_gpio_support = 0;
118 0 : data->registry_data.quick_transition_support = 0;
119 0 : data->registry_data.zrpm_start_temp = 0xffff;
120 0 : data->registry_data.zrpm_stop_temp = 0xffff;
121 0 : data->registry_data.odn_feature_enable = 1;
122 0 : data->registry_data.disable_water_mark = 0;
123 0 : data->registry_data.disable_pp_tuning = 0;
124 0 : data->registry_data.disable_xlpp_tuning = 0;
125 0 : data->registry_data.disable_workload_policy = 0;
126 0 : data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
127 0 : data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
128 0 : data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
129 0 : data->registry_data.force_workload_policy_mask = 0;
130 0 : data->registry_data.disable_3d_fs_detection = 0;
131 0 : data->registry_data.fps_support = 1;
132 0 : data->registry_data.disable_auto_wattman = 1;
133 0 : data->registry_data.auto_wattman_debug = 0;
134 0 : data->registry_data.auto_wattman_sample_period = 100;
135 0 : data->registry_data.auto_wattman_threshold = 50;
136 0 : data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
137 0 : }
138 :
139 0 : static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
140 : {
141 0 : struct vega12_hwmgr *data =
142 : (struct vega12_hwmgr *)(hwmgr->backend);
143 0 : struct amdgpu_device *adev = hwmgr->adev;
144 :
145 0 : if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
146 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
147 : PHM_PlatformCaps_ControlVDDCI);
148 :
149 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
150 : PHM_PlatformCaps_TablelessHardwareInterface);
151 :
152 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
153 : PHM_PlatformCaps_EnableSMU7ThermalManagement);
154 :
155 0 : if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
156 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
157 : PHM_PlatformCaps_UVDPowerGating);
158 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
159 : PHM_PlatformCaps_UVDDynamicPowerGating);
160 : }
161 :
162 0 : if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
163 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
164 : PHM_PlatformCaps_VCEPowerGating);
165 :
166 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
167 : PHM_PlatformCaps_UnTabledHardwareInterface);
168 :
169 0 : if (data->registry_data.odn_feature_enable)
170 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
171 : PHM_PlatformCaps_ODNinACSupport);
172 : else {
173 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
174 : PHM_PlatformCaps_OD6inACSupport);
175 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
176 : PHM_PlatformCaps_OD6PlusinACSupport);
177 : }
178 :
179 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
180 : PHM_PlatformCaps_ActivityReporting);
181 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
182 : PHM_PlatformCaps_FanSpeedInTableIsRPM);
183 :
184 0 : if (data->registry_data.od_state_in_dc_support) {
185 0 : if (data->registry_data.odn_feature_enable)
186 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
187 : PHM_PlatformCaps_ODNinDCSupport);
188 : else {
189 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
190 : PHM_PlatformCaps_OD6inDCSupport);
191 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
192 : PHM_PlatformCaps_OD6PlusinDCSupport);
193 : }
194 : }
195 :
196 0 : if (data->registry_data.thermal_support
197 0 : && data->registry_data.fuzzy_fan_control_support
198 0 : && hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
199 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
200 : PHM_PlatformCaps_ODFuzzyFanControlSupport);
201 :
202 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
203 : PHM_PlatformCaps_DynamicPowerManagement);
204 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
205 : PHM_PlatformCaps_SMC);
206 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
207 : PHM_PlatformCaps_ThermalPolicyDelay);
208 :
209 0 : if (data->registry_data.force_dpm_high)
210 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
211 : PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
212 :
213 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
214 : PHM_PlatformCaps_DynamicUVDState);
215 :
216 0 : if (data->registry_data.sclk_throttle_low_notification)
217 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
218 : PHM_PlatformCaps_SclkThrottleLowNotification);
219 :
220 : /* power tune caps */
221 : /* assume disabled */
222 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
223 : PHM_PlatformCaps_PowerContainment);
224 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
225 : PHM_PlatformCaps_DiDtSupport);
226 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
227 : PHM_PlatformCaps_SQRamping);
228 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
229 : PHM_PlatformCaps_DBRamping);
230 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
231 : PHM_PlatformCaps_TDRamping);
232 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
233 : PHM_PlatformCaps_TCPRamping);
234 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
235 : PHM_PlatformCaps_DBRRamping);
236 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
237 : PHM_PlatformCaps_DiDtEDCEnable);
238 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
239 : PHM_PlatformCaps_GCEDC);
240 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
241 : PHM_PlatformCaps_PSM);
242 :
243 0 : if (data->registry_data.didt_support) {
244 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
245 0 : if (data->registry_data.sq_ramping_support)
246 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
247 0 : if (data->registry_data.db_ramping_support)
248 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
249 0 : if (data->registry_data.td_ramping_support)
250 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
251 0 : if (data->registry_data.tcp_ramping_support)
252 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
253 0 : if (data->registry_data.dbr_ramping_support)
254 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
255 0 : if (data->registry_data.edc_didt_support)
256 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
257 0 : if (data->registry_data.gc_didt_support)
258 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
259 0 : if (data->registry_data.psm_didt_support)
260 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
261 : }
262 :
263 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
264 : PHM_PlatformCaps_RegulatorHot);
265 :
266 0 : if (data->registry_data.ac_dc_switch_gpio_support) {
267 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
268 : PHM_PlatformCaps_AutomaticDCTransition);
269 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
270 : PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
271 : }
272 :
273 0 : if (data->registry_data.quick_transition_support) {
274 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
275 : PHM_PlatformCaps_AutomaticDCTransition);
276 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
277 : PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
278 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
279 : PHM_PlatformCaps_Falcon_QuickTransition);
280 : }
281 :
282 0 : if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
283 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
284 : PHM_PlatformCaps_LowestUclkReservedForUlv);
285 0 : if (data->lowest_uclk_reserved_for_ulv == 1)
286 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
287 : PHM_PlatformCaps_LowestUclkReservedForUlv);
288 : }
289 :
290 0 : if (data->registry_data.custom_fan_support)
291 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
292 : PHM_PlatformCaps_CustomFanControlSupport);
293 :
294 0 : return 0;
295 : }
296 :
297 0 : static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
298 : {
299 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
300 0 : struct amdgpu_device *adev = hwmgr->adev;
301 : uint32_t top32, bottom32;
302 : int i;
303 :
304 0 : data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
305 : FEATURE_DPM_PREFETCHER_BIT;
306 0 : data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
307 : FEATURE_DPM_GFXCLK_BIT;
308 0 : data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
309 : FEATURE_DPM_UCLK_BIT;
310 0 : data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
311 : FEATURE_DPM_SOCCLK_BIT;
312 0 : data->smu_features[GNLD_DPM_UVD].smu_feature_id =
313 : FEATURE_DPM_UVD_BIT;
314 0 : data->smu_features[GNLD_DPM_VCE].smu_feature_id =
315 : FEATURE_DPM_VCE_BIT;
316 0 : data->smu_features[GNLD_ULV].smu_feature_id =
317 : FEATURE_ULV_BIT;
318 0 : data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
319 : FEATURE_DPM_MP0CLK_BIT;
320 0 : data->smu_features[GNLD_DPM_LINK].smu_feature_id =
321 : FEATURE_DPM_LINK_BIT;
322 0 : data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
323 : FEATURE_DPM_DCEFCLK_BIT;
324 0 : data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
325 : FEATURE_DS_GFXCLK_BIT;
326 0 : data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
327 : FEATURE_DS_SOCCLK_BIT;
328 0 : data->smu_features[GNLD_DS_LCLK].smu_feature_id =
329 : FEATURE_DS_LCLK_BIT;
330 0 : data->smu_features[GNLD_PPT].smu_feature_id =
331 : FEATURE_PPT_BIT;
332 0 : data->smu_features[GNLD_TDC].smu_feature_id =
333 : FEATURE_TDC_BIT;
334 0 : data->smu_features[GNLD_THERMAL].smu_feature_id =
335 : FEATURE_THERMAL_BIT;
336 0 : data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
337 : FEATURE_GFX_PER_CU_CG_BIT;
338 0 : data->smu_features[GNLD_RM].smu_feature_id =
339 : FEATURE_RM_BIT;
340 0 : data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
341 : FEATURE_DS_DCEFCLK_BIT;
342 0 : data->smu_features[GNLD_ACDC].smu_feature_id =
343 : FEATURE_ACDC_BIT;
344 0 : data->smu_features[GNLD_VR0HOT].smu_feature_id =
345 : FEATURE_VR0HOT_BIT;
346 0 : data->smu_features[GNLD_VR1HOT].smu_feature_id =
347 : FEATURE_VR1HOT_BIT;
348 0 : data->smu_features[GNLD_FW_CTF].smu_feature_id =
349 : FEATURE_FW_CTF_BIT;
350 0 : data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
351 : FEATURE_LED_DISPLAY_BIT;
352 0 : data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
353 : FEATURE_FAN_CONTROL_BIT;
354 0 : data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
355 0 : data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
356 0 : data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
357 0 : data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
358 :
359 0 : for (i = 0; i < GNLD_FEATURES_MAX; i++) {
360 0 : data->smu_features[i].smu_feature_bitmap =
361 0 : (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
362 0 : data->smu_features[i].allowed =
363 0 : ((data->registry_data.disallowed_features >> i) & 1) ?
364 0 : false : true;
365 : }
366 :
367 : /* Get the SN to turn into a Unique ID */
368 0 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
369 0 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
370 :
371 0 : adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
372 0 : }
373 :
374 : static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
375 : {
376 : return 0;
377 : }
378 :
379 0 : static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
380 : {
381 0 : kfree(hwmgr->backend);
382 0 : hwmgr->backend = NULL;
383 :
384 0 : return 0;
385 : }
386 :
387 0 : static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
388 : {
389 0 : int result = 0;
390 : struct vega12_hwmgr *data;
391 0 : struct amdgpu_device *adev = hwmgr->adev;
392 :
393 0 : data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
394 0 : if (data == NULL)
395 : return -ENOMEM;
396 :
397 0 : hwmgr->backend = data;
398 :
399 0 : vega12_set_default_registry_data(hwmgr);
400 :
401 0 : data->disable_dpm_mask = 0xff;
402 0 : data->workload_mask = 0xff;
403 :
404 : /* need to set voltage control types before EVV patching */
405 0 : data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
406 0 : data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
407 0 : data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
408 :
409 0 : data->water_marks_bitmap = 0;
410 0 : data->avfs_exist = false;
411 :
412 0 : vega12_set_features_platform_caps(hwmgr);
413 :
414 0 : vega12_init_dpm_defaults(hwmgr);
415 :
416 : /* Parse pptable data read from VBIOS */
417 0 : vega12_set_private_data_based_on_pptable(hwmgr);
418 :
419 0 : data->is_tlu_enabled = false;
420 :
421 0 : hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
422 : VEGA12_MAX_HARDWARE_POWERLEVELS;
423 0 : hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
424 0 : hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
425 :
426 0 : hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
427 : /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
428 0 : hwmgr->platform_descriptor.clockStep.engineClock = 500;
429 0 : hwmgr->platform_descriptor.clockStep.memoryClock = 500;
430 :
431 0 : data->total_active_cus = adev->gfx.cu_info.number;
432 : /* Setup default Overdrive Fan control settings */
433 0 : data->odn_fan_table.target_fan_speed =
434 0 : hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
435 0 : data->odn_fan_table.target_temperature =
436 0 : hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
437 0 : data->odn_fan_table.min_performance_clock =
438 0 : hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
439 0 : data->odn_fan_table.min_fan_limit =
440 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
441 0 : hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
442 :
443 0 : if (hwmgr->feature_mask & PP_GFXOFF_MASK)
444 0 : data->gfxoff_controlled_by_driver = true;
445 : else
446 0 : data->gfxoff_controlled_by_driver = false;
447 :
448 : return result;
449 : }
450 :
451 : static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
452 : {
453 0 : struct vega12_hwmgr *data =
454 : (struct vega12_hwmgr *)(hwmgr->backend);
455 :
456 0 : data->low_sclk_interrupt_threshold = 0;
457 :
458 : return 0;
459 : }
460 :
461 0 : static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
462 : {
463 0 : PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
464 : "Failed to init sclk threshold!",
465 : return -EINVAL);
466 :
467 : return 0;
468 : }
469 :
470 : /*
471 : * @fn vega12_init_dpm_state
472 : * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
473 : *
474 : * @param dpm_state - the address of the DPM Table to initiailize.
475 : * @return None.
476 : */
477 : static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
478 : {
479 0 : dpm_state->soft_min_level = 0x0;
480 0 : dpm_state->soft_max_level = 0xffff;
481 0 : dpm_state->hard_min_level = 0x0;
482 0 : dpm_state->hard_max_level = 0xffff;
483 : }
484 :
485 0 : static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr)
486 : {
487 0 : struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
488 0 : struct vega12_hwmgr *data =
489 : (struct vega12_hwmgr *)(hwmgr->backend);
490 0 : uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;
491 0 : PPTable_t *pp_table = &(data->smc_state_table.pp_table);
492 : int i;
493 : int ret;
494 :
495 0 : if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
496 : pcie_gen = 3;
497 0 : else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
498 : pcie_gen = 2;
499 0 : else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
500 : pcie_gen = 1;
501 : else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
502 : pcie_gen = 0;
503 :
504 0 : if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
505 : pcie_width = 6;
506 0 : else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
507 : pcie_width = 5;
508 0 : else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
509 : pcie_width = 4;
510 0 : else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
511 : pcie_width = 3;
512 0 : else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
513 : pcie_width = 2;
514 0 : else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
515 0 : pcie_width = 1;
516 :
517 : /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
518 : * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
519 : * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
520 : */
521 0 : for (i = 0; i < NUM_LINK_LEVELS; i++) {
522 0 : pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen :
523 0 : pp_table->PcieGenSpeed[i];
524 0 : pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width :
525 0 : pp_table->PcieLaneCount[i];
526 :
527 0 : if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg !=
528 : pp_table->PcieLaneCount[i]) {
529 0 : smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg;
530 0 : ret = smum_send_msg_to_smc_with_parameter(hwmgr,
531 : PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
532 : NULL);
533 0 : PP_ASSERT_WITH_CODE(!ret,
534 : "[OverridePcieParameters] Attempt to override pcie params failed!",
535 : return ret);
536 : }
537 :
538 : /* update the pptable */
539 0 : pp_table->PcieGenSpeed[i] = pcie_gen_arg;
540 0 : pp_table->PcieLaneCount[i] = pcie_width_arg;
541 : }
542 :
543 : /* override to the highest if it's disabled from ppfeaturmask */
544 0 : if (data->registry_data.pcie_dpm_key_disabled) {
545 0 : for (i = 0; i < NUM_LINK_LEVELS; i++) {
546 0 : smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;
547 0 : ret = smum_send_msg_to_smc_with_parameter(hwmgr,
548 : PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
549 : NULL);
550 0 : PP_ASSERT_WITH_CODE(!ret,
551 : "[OverridePcieParameters] Attempt to override pcie params failed!",
552 : return ret);
553 :
554 0 : pp_table->PcieGenSpeed[i] = pcie_gen;
555 0 : pp_table->PcieLaneCount[i] = pcie_width;
556 : }
557 0 : ret = vega12_enable_smc_features(hwmgr,
558 : false,
559 : data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);
560 0 : PP_ASSERT_WITH_CODE(!ret,
561 : "Attempt to Disable DPM LINK Failed!",
562 : return ret);
563 0 : data->smu_features[GNLD_DPM_LINK].enabled = false;
564 0 : data->smu_features[GNLD_DPM_LINK].supported = false;
565 : }
566 : return 0;
567 : }
568 :
569 0 : static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
570 : PPCLK_e clk_id, uint32_t *num_of_levels)
571 : {
572 0 : int ret = 0;
573 :
574 0 : ret = smum_send_msg_to_smc_with_parameter(hwmgr,
575 : PPSMC_MSG_GetDpmFreqByIndex,
576 0 : (clk_id << 16 | 0xFF),
577 : num_of_levels);
578 0 : PP_ASSERT_WITH_CODE(!ret,
579 : "[GetNumOfDpmLevel] failed to get dpm levels!",
580 : return ret);
581 :
582 : return ret;
583 : }
584 :
585 0 : static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
586 : PPCLK_e clkID, uint32_t index, uint32_t *clock)
587 : {
588 : /*
589 : *SMU expects the Clock ID to be in the top 16 bits.
590 : *Lower 16 bits specify the level
591 : */
592 0 : PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
593 : PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index),
594 : clock) == 0,
595 : "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",
596 : return -EINVAL);
597 :
598 : return 0;
599 : }
600 :
601 0 : static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
602 : struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
603 : {
604 0 : int ret = 0;
605 : uint32_t i, num_of_levels, clk;
606 :
607 0 : ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
608 0 : PP_ASSERT_WITH_CODE(!ret,
609 : "[SetupSingleDpmTable] failed to get clk levels!",
610 : return ret);
611 :
612 0 : dpm_table->count = num_of_levels;
613 :
614 0 : for (i = 0; i < num_of_levels; i++) {
615 0 : ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
616 0 : PP_ASSERT_WITH_CODE(!ret,
617 : "[SetupSingleDpmTable] failed to get clk of specific level!",
618 : return ret);
619 0 : dpm_table->dpm_levels[i].value = clk;
620 0 : dpm_table->dpm_levels[i].enabled = true;
621 : }
622 :
623 : return ret;
624 : }
625 :
626 : /*
627 : * This function is to initialize all DPM state tables
628 : * for SMU based on the dependency table.
629 : * Dynamic state patching function will then trim these
630 : * state tables to the allowed range based
631 : * on the power policy or external client requests,
632 : * such as UVD request, etc.
633 : */
634 0 : static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
635 : {
636 :
637 0 : struct vega12_hwmgr *data =
638 : (struct vega12_hwmgr *)(hwmgr->backend);
639 : struct vega12_single_dpm_table *dpm_table;
640 0 : int ret = 0;
641 :
642 0 : memset(&data->dpm_table, 0, sizeof(data->dpm_table));
643 :
644 : /* socclk */
645 0 : dpm_table = &(data->dpm_table.soc_table);
646 0 : if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
647 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
648 0 : PP_ASSERT_WITH_CODE(!ret,
649 : "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
650 : return ret);
651 : } else {
652 0 : dpm_table->count = 1;
653 0 : dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
654 : }
655 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
656 :
657 : /* gfxclk */
658 0 : dpm_table = &(data->dpm_table.gfx_table);
659 0 : if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
660 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
661 0 : PP_ASSERT_WITH_CODE(!ret,
662 : "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
663 : return ret);
664 : } else {
665 0 : dpm_table->count = 1;
666 0 : dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
667 : }
668 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
669 :
670 : /* memclk */
671 0 : dpm_table = &(data->dpm_table.mem_table);
672 0 : if (data->smu_features[GNLD_DPM_UCLK].enabled) {
673 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
674 0 : PP_ASSERT_WITH_CODE(!ret,
675 : "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
676 : return ret);
677 : } else {
678 0 : dpm_table->count = 1;
679 0 : dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
680 : }
681 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
682 :
683 : /* eclk */
684 0 : dpm_table = &(data->dpm_table.eclk_table);
685 0 : if (data->smu_features[GNLD_DPM_VCE].enabled) {
686 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
687 0 : PP_ASSERT_WITH_CODE(!ret,
688 : "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
689 : return ret);
690 : } else {
691 0 : dpm_table->count = 1;
692 0 : dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
693 : }
694 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
695 :
696 : /* vclk */
697 0 : dpm_table = &(data->dpm_table.vclk_table);
698 0 : if (data->smu_features[GNLD_DPM_UVD].enabled) {
699 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
700 0 : PP_ASSERT_WITH_CODE(!ret,
701 : "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
702 : return ret);
703 : } else {
704 0 : dpm_table->count = 1;
705 0 : dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
706 : }
707 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
708 :
709 : /* dclk */
710 0 : dpm_table = &(data->dpm_table.dclk_table);
711 0 : if (data->smu_features[GNLD_DPM_UVD].enabled) {
712 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
713 0 : PP_ASSERT_WITH_CODE(!ret,
714 : "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
715 : return ret);
716 : } else {
717 0 : dpm_table->count = 1;
718 0 : dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
719 : }
720 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
721 :
722 : /* dcefclk */
723 0 : dpm_table = &(data->dpm_table.dcef_table);
724 0 : if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
725 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
726 0 : PP_ASSERT_WITH_CODE(!ret,
727 : "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
728 : return ret);
729 : } else {
730 0 : dpm_table->count = 1;
731 0 : dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
732 : }
733 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
734 :
735 : /* pixclk */
736 0 : dpm_table = &(data->dpm_table.pixel_table);
737 0 : if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
738 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
739 0 : PP_ASSERT_WITH_CODE(!ret,
740 : "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
741 : return ret);
742 : } else
743 0 : dpm_table->count = 0;
744 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
745 :
746 : /* dispclk */
747 0 : dpm_table = &(data->dpm_table.display_table);
748 0 : if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
749 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
750 0 : PP_ASSERT_WITH_CODE(!ret,
751 : "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
752 : return ret);
753 : } else
754 0 : dpm_table->count = 0;
755 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
756 :
757 : /* phyclk */
758 0 : dpm_table = &(data->dpm_table.phy_table);
759 0 : if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
760 0 : ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
761 0 : PP_ASSERT_WITH_CODE(!ret,
762 : "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
763 : return ret);
764 : } else
765 0 : dpm_table->count = 0;
766 0 : vega12_init_dpm_state(&(dpm_table->dpm_state));
767 :
768 : /* save a copy of the default DPM table */
769 0 : memcpy(&(data->golden_dpm_table), &(data->dpm_table),
770 : sizeof(struct vega12_dpm_table));
771 :
772 0 : return 0;
773 : }
774 :
775 : #if 0
776 : static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
777 : {
778 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
779 : struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
780 : uint32_t min_level;
781 :
782 : hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
783 : hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
784 :
785 : /* Optimize compute power profile: Use only highest
786 : * 2 power levels (if more than 2 are available)
787 : */
788 : if (dpm_table->count > 2)
789 : min_level = dpm_table->count - 2;
790 : else if (dpm_table->count == 2)
791 : min_level = 1;
792 : else
793 : min_level = 0;
794 :
795 : hwmgr->default_compute_power_profile.min_sclk =
796 : dpm_table->dpm_levels[min_level].value;
797 :
798 : hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
799 : hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
800 :
801 : return 0;
802 : }
803 : #endif
804 :
805 : /**
806 : * vega12_init_smc_table - Initializes the SMC table and uploads it
807 : *
808 : * @hwmgr: the address of the powerplay hardware manager.
809 : * return: always 0
810 : */
811 0 : static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
812 : {
813 : int result;
814 0 : struct vega12_hwmgr *data =
815 : (struct vega12_hwmgr *)(hwmgr->backend);
816 0 : PPTable_t *pp_table = &(data->smc_state_table.pp_table);
817 : struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
818 0 : struct phm_ppt_v3_information *pptable_information =
819 : (struct phm_ppt_v3_information *)hwmgr->pptable;
820 :
821 0 : result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
822 0 : if (!result) {
823 0 : data->vbios_boot_state.vddc = boot_up_values.usVddc;
824 0 : data->vbios_boot_state.vddci = boot_up_values.usVddci;
825 0 : data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
826 0 : data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
827 0 : data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
828 0 : data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
829 0 : data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
830 0 : data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
831 0 : data->vbios_boot_state.eclock = boot_up_values.ulEClk;
832 0 : data->vbios_boot_state.dclock = boot_up_values.ulDClk;
833 0 : data->vbios_boot_state.vclock = boot_up_values.ulVClk;
834 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
835 : PPSMC_MSG_SetMinDeepSleepDcefclk,
836 0 : (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
837 : NULL);
838 : }
839 :
840 0 : memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
841 :
842 0 : result = smum_smc_table_manager(hwmgr,
843 : (uint8_t *)pp_table, TABLE_PPTABLE, false);
844 0 : PP_ASSERT_WITH_CODE(!result,
845 : "Failed to upload PPtable!", return result);
846 :
847 : return 0;
848 : }
849 :
850 0 : static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
851 : {
852 : uint32_t result;
853 :
854 0 : PP_ASSERT_WITH_CODE(
855 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0,
856 : "[Run_ACG_BTC] Attempt to run ACG BTC failed!",
857 : return -EINVAL);
858 :
859 0 : PP_ASSERT_WITH_CODE(result == 1,
860 : "Failed to run ACG BTC!", return -EINVAL);
861 :
862 : return 0;
863 : }
864 :
865 0 : static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
866 : {
867 0 : struct vega12_hwmgr *data =
868 : (struct vega12_hwmgr *)(hwmgr->backend);
869 : int i;
870 0 : uint32_t allowed_features_low = 0, allowed_features_high = 0;
871 :
872 0 : for (i = 0; i < GNLD_FEATURES_MAX; i++)
873 0 : if (data->smu_features[i].allowed)
874 0 : data->smu_features[i].smu_feature_id > 31 ?
875 0 : (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
876 0 : (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
877 :
878 0 : PP_ASSERT_WITH_CODE(
879 : smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high,
880 : NULL) == 0,
881 : "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
882 : return -1);
883 :
884 0 : PP_ASSERT_WITH_CODE(
885 : smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low,
886 : NULL) == 0,
887 : "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
888 : return -1);
889 :
890 : return 0;
891 : }
892 :
893 : static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
894 : {
895 0 : struct vega12_hwmgr *data =
896 : (struct vega12_hwmgr *)(hwmgr->backend);
897 :
898 0 : data->uvd_power_gated = true;
899 0 : data->vce_power_gated = true;
900 :
901 0 : if (data->smu_features[GNLD_DPM_UVD].enabled)
902 0 : data->uvd_power_gated = false;
903 :
904 0 : if (data->smu_features[GNLD_DPM_VCE].enabled)
905 0 : data->vce_power_gated = false;
906 : }
907 :
908 0 : static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
909 : {
910 0 : struct vega12_hwmgr *data =
911 : (struct vega12_hwmgr *)(hwmgr->backend);
912 : uint64_t features_enabled;
913 : int i;
914 : bool enabled;
915 :
916 0 : PP_ASSERT_WITH_CODE(
917 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0,
918 : "[EnableAllSMUFeatures] Failed to enable all smu features!",
919 : return -1);
920 :
921 0 : if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
922 0 : for (i = 0; i < GNLD_FEATURES_MAX; i++) {
923 0 : enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
924 0 : data->smu_features[i].enabled = enabled;
925 0 : data->smu_features[i].supported = enabled;
926 : }
927 : }
928 :
929 0 : vega12_init_powergate_state(hwmgr);
930 :
931 : return 0;
932 : }
933 :
934 0 : static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
935 : {
936 0 : struct vega12_hwmgr *data =
937 : (struct vega12_hwmgr *)(hwmgr->backend);
938 : uint64_t features_enabled;
939 : int i;
940 : bool enabled;
941 :
942 0 : PP_ASSERT_WITH_CODE(
943 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0,
944 : "[DisableAllSMUFeatures] Failed to disable all smu features!",
945 : return -1);
946 :
947 0 : if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
948 0 : for (i = 0; i < GNLD_FEATURES_MAX; i++) {
949 0 : enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
950 0 : data->smu_features[i].enabled = enabled;
951 0 : data->smu_features[i].supported = enabled;
952 : }
953 : }
954 :
955 : return 0;
956 : }
957 :
958 : static int vega12_odn_initialize_default_settings(
959 : struct pp_hwmgr *hwmgr)
960 : {
961 : return 0;
962 : }
963 :
964 : static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
965 : uint32_t adjust_percent)
966 : {
967 0 : return smum_send_msg_to_smc_with_parameter(hwmgr,
968 : PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
969 : NULL);
970 : }
971 :
972 0 : static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
973 : {
974 0 : int adjust_percent, result = 0;
975 :
976 0 : if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
977 0 : adjust_percent =
978 0 : hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
979 0 : hwmgr->platform_descriptor.TDPAdjustment :
980 0 : (-1 * hwmgr->platform_descriptor.TDPAdjustment);
981 0 : result = vega12_set_overdrive_target_percentage(hwmgr,
982 : (uint32_t)adjust_percent);
983 : }
984 0 : return result;
985 : }
986 :
987 0 : static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
988 : PPCLK_e clkid, struct vega12_clock_range *clock)
989 : {
990 : /* AC Max */
991 0 : PP_ASSERT_WITH_CODE(
992 : smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16),
993 : &(clock->ACMax)) == 0,
994 : "[GetClockRanges] Failed to get max ac clock from SMC!",
995 : return -EINVAL);
996 :
997 : /* AC Min */
998 0 : PP_ASSERT_WITH_CODE(
999 : smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16),
1000 : &(clock->ACMin)) == 0,
1001 : "[GetClockRanges] Failed to get min ac clock from SMC!",
1002 : return -EINVAL);
1003 :
1004 : /* DC Max */
1005 0 : PP_ASSERT_WITH_CODE(
1006 : smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16),
1007 : &(clock->DCMax)) == 0,
1008 : "[GetClockRanges] Failed to get max dc clock from SMC!",
1009 : return -EINVAL);
1010 :
1011 : return 0;
1012 : }
1013 :
1014 0 : static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
1015 : {
1016 0 : struct vega12_hwmgr *data =
1017 : (struct vega12_hwmgr *)(hwmgr->backend);
1018 : uint32_t i;
1019 :
1020 0 : for (i = 0; i < PPCLK_COUNT; i++)
1021 0 : PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
1022 : i, &(data->clk_range[i])),
1023 : "Failed to get clk range from SMC!",
1024 : return -EINVAL);
1025 :
1026 : return 0;
1027 : }
1028 :
1029 0 : static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1030 : {
1031 0 : int tmp_result, result = 0;
1032 :
1033 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
1034 : PPSMC_MSG_NumOfDisplays, 0, NULL);
1035 :
1036 0 : result = vega12_set_allowed_featuresmask(hwmgr);
1037 0 : PP_ASSERT_WITH_CODE(result == 0,
1038 : "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1039 : return result);
1040 :
1041 0 : tmp_result = vega12_init_smc_table(hwmgr);
1042 0 : PP_ASSERT_WITH_CODE(!tmp_result,
1043 : "Failed to initialize SMC table!",
1044 : result = tmp_result);
1045 :
1046 0 : tmp_result = vega12_run_acg_btc(hwmgr);
1047 0 : PP_ASSERT_WITH_CODE(!tmp_result,
1048 : "Failed to run ACG BTC!",
1049 : result = tmp_result);
1050 :
1051 0 : result = vega12_enable_all_smu_features(hwmgr);
1052 0 : PP_ASSERT_WITH_CODE(!result,
1053 : "Failed to enable all smu features!",
1054 : return result);
1055 :
1056 0 : result = vega12_override_pcie_parameters(hwmgr);
1057 0 : PP_ASSERT_WITH_CODE(!result,
1058 : "[EnableDPMTasks] Failed to override pcie parameters!",
1059 : return result);
1060 :
1061 0 : tmp_result = vega12_power_control_set_level(hwmgr);
1062 0 : PP_ASSERT_WITH_CODE(!tmp_result,
1063 : "Failed to power control set level!",
1064 : result = tmp_result);
1065 :
1066 0 : result = vega12_get_all_clock_ranges(hwmgr);
1067 0 : PP_ASSERT_WITH_CODE(!result,
1068 : "Failed to get all clock ranges!",
1069 : return result);
1070 :
1071 0 : result = vega12_odn_initialize_default_settings(hwmgr);
1072 : PP_ASSERT_WITH_CODE(!result,
1073 : "Failed to power control set level!",
1074 : return result);
1075 :
1076 0 : result = vega12_setup_default_dpm_tables(hwmgr);
1077 0 : PP_ASSERT_WITH_CODE(!result,
1078 : "Failed to setup default DPM tables!",
1079 : return result);
1080 : return result;
1081 : }
1082 :
1083 0 : static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
1084 : struct pp_hw_power_state *hw_ps)
1085 : {
1086 0 : return 0;
1087 : }
1088 :
1089 : static uint32_t vega12_find_lowest_dpm_level(
1090 : struct vega12_single_dpm_table *table)
1091 : {
1092 : uint32_t i;
1093 :
1094 0 : for (i = 0; i < table->count; i++) {
1095 0 : if (table->dpm_levels[i].enabled)
1096 : break;
1097 : }
1098 :
1099 0 : if (i >= table->count) {
1100 0 : i = 0;
1101 0 : table->dpm_levels[i].enabled = true;
1102 : }
1103 :
1104 : return i;
1105 : }
1106 :
1107 0 : static uint32_t vega12_find_highest_dpm_level(
1108 : struct vega12_single_dpm_table *table)
1109 : {
1110 0 : int32_t i = 0;
1111 0 : PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1112 : "[FindHighestDPMLevel] DPM Table has too many entries!",
1113 : return MAX_REGULAR_DPM_NUMBER - 1);
1114 :
1115 0 : for (i = table->count - 1; i >= 0; i--) {
1116 0 : if (table->dpm_levels[i].enabled)
1117 : break;
1118 : }
1119 :
1120 0 : if (i < 0) {
1121 0 : i = 0;
1122 0 : table->dpm_levels[i].enabled = true;
1123 : }
1124 :
1125 0 : return (uint32_t)i;
1126 : }
1127 :
1128 0 : static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1129 : {
1130 0 : struct vega12_hwmgr *data = hwmgr->backend;
1131 : uint32_t min_freq;
1132 0 : int ret = 0;
1133 :
1134 0 : if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1135 0 : min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1136 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1137 : hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1138 : (PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1139 : NULL)),
1140 : "Failed to set soft min gfxclk !",
1141 : return ret);
1142 : }
1143 :
1144 0 : if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1145 0 : min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1146 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1147 : hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1148 : (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1149 : NULL)),
1150 : "Failed to set soft min memclk !",
1151 : return ret);
1152 :
1153 0 : min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1154 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1155 : hwmgr, PPSMC_MSG_SetHardMinByFreq,
1156 : (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1157 : NULL)),
1158 : "Failed to set hard min memclk !",
1159 : return ret);
1160 : }
1161 :
1162 0 : if (data->smu_features[GNLD_DPM_UVD].enabled) {
1163 0 : min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1164 :
1165 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1166 : hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1167 : (PPCLK_VCLK << 16) | (min_freq & 0xffff),
1168 : NULL)),
1169 : "Failed to set soft min vclk!",
1170 : return ret);
1171 :
1172 0 : min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1173 :
1174 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1175 : hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1176 : (PPCLK_DCLK << 16) | (min_freq & 0xffff),
1177 : NULL)),
1178 : "Failed to set soft min dclk!",
1179 : return ret);
1180 : }
1181 :
1182 0 : if (data->smu_features[GNLD_DPM_VCE].enabled) {
1183 0 : min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1184 :
1185 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1186 : hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1187 : (PPCLK_ECLK << 16) | (min_freq & 0xffff),
1188 : NULL)),
1189 : "Failed to set soft min eclk!",
1190 : return ret);
1191 : }
1192 :
1193 0 : if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1194 0 : min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1195 :
1196 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1197 : hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1198 : (PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1199 : NULL)),
1200 : "Failed to set soft min socclk!",
1201 : return ret);
1202 : }
1203 :
1204 0 : if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1205 0 : min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1206 :
1207 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1208 : hwmgr, PPSMC_MSG_SetHardMinByFreq,
1209 : (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1210 : NULL)),
1211 : "Failed to set hard min dcefclk!",
1212 : return ret);
1213 : }
1214 :
1215 : return ret;
1216 :
1217 : }
1218 :
1219 0 : static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1220 : {
1221 0 : struct vega12_hwmgr *data = hwmgr->backend;
1222 : uint32_t max_freq;
1223 0 : int ret = 0;
1224 :
1225 0 : if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1226 0 : max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1227 :
1228 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1229 : hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1230 : (PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1231 : NULL)),
1232 : "Failed to set soft max gfxclk!",
1233 : return ret);
1234 : }
1235 :
1236 0 : if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1237 0 : max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1238 :
1239 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1240 : hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1241 : (PPCLK_UCLK << 16) | (max_freq & 0xffff),
1242 : NULL)),
1243 : "Failed to set soft max memclk!",
1244 : return ret);
1245 : }
1246 :
1247 0 : if (data->smu_features[GNLD_DPM_UVD].enabled) {
1248 0 : max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1249 :
1250 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1251 : hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1252 : (PPCLK_VCLK << 16) | (max_freq & 0xffff),
1253 : NULL)),
1254 : "Failed to set soft max vclk!",
1255 : return ret);
1256 :
1257 0 : max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1258 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1259 : hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1260 : (PPCLK_DCLK << 16) | (max_freq & 0xffff),
1261 : NULL)),
1262 : "Failed to set soft max dclk!",
1263 : return ret);
1264 : }
1265 :
1266 0 : if (data->smu_features[GNLD_DPM_VCE].enabled) {
1267 0 : max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1268 :
1269 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1270 : hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1271 : (PPCLK_ECLK << 16) | (max_freq & 0xffff),
1272 : NULL)),
1273 : "Failed to set soft max eclk!",
1274 : return ret);
1275 : }
1276 :
1277 0 : if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1278 0 : max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1279 :
1280 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1281 : hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1282 : (PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1283 : NULL)),
1284 : "Failed to set soft max socclk!",
1285 : return ret);
1286 : }
1287 :
1288 : return ret;
1289 : }
1290 :
1291 0 : int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1292 : {
1293 0 : struct vega12_hwmgr *data =
1294 : (struct vega12_hwmgr *)(hwmgr->backend);
1295 :
1296 0 : if (data->smu_features[GNLD_DPM_VCE].supported) {
1297 0 : PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
1298 : enable,
1299 : data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
1300 : "Attempt to Enable/Disable DPM VCE Failed!",
1301 : return -1);
1302 0 : data->smu_features[GNLD_DPM_VCE].enabled = enable;
1303 : }
1304 :
1305 : return 0;
1306 : }
1307 :
1308 0 : static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1309 : {
1310 0 : struct vega12_hwmgr *data =
1311 : (struct vega12_hwmgr *)(hwmgr->backend);
1312 : uint32_t gfx_clk;
1313 :
1314 0 : if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1315 : return -1;
1316 :
1317 0 : if (low)
1318 0 : PP_ASSERT_WITH_CODE(
1319 : vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
1320 : "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1321 : return -1);
1322 : else
1323 0 : PP_ASSERT_WITH_CODE(
1324 : vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
1325 : "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1326 : return -1);
1327 :
1328 0 : return (gfx_clk * 100);
1329 : }
1330 :
1331 0 : static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1332 : {
1333 0 : struct vega12_hwmgr *data =
1334 : (struct vega12_hwmgr *)(hwmgr->backend);
1335 : uint32_t mem_clk;
1336 :
1337 0 : if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1338 : return -1;
1339 :
1340 0 : if (low)
1341 0 : PP_ASSERT_WITH_CODE(
1342 : vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
1343 : "[GetMclks]: fail to get min PPCLK_UCLK\n",
1344 : return -1);
1345 : else
1346 0 : PP_ASSERT_WITH_CODE(
1347 : vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
1348 : "[GetMclks]: fail to get max PPCLK_UCLK\n",
1349 : return -1);
1350 :
1351 0 : return (mem_clk * 100);
1352 : }
1353 :
1354 0 : static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr,
1355 : SmuMetrics_t *metrics_table,
1356 : bool bypass_cache)
1357 : {
1358 0 : struct vega12_hwmgr *data =
1359 : (struct vega12_hwmgr *)(hwmgr->backend);
1360 0 : int ret = 0;
1361 :
1362 0 : if (bypass_cache ||
1363 0 : !data->metrics_time ||
1364 0 : time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) {
1365 0 : ret = smum_smc_table_manager(hwmgr,
1366 0 : (uint8_t *)(&data->metrics_table),
1367 : TABLE_SMU_METRICS,
1368 : true);
1369 0 : if (ret) {
1370 0 : pr_info("Failed to export SMU metrics table!\n");
1371 0 : return ret;
1372 : }
1373 0 : data->metrics_time = jiffies;
1374 : }
1375 :
1376 0 : if (metrics_table)
1377 0 : memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
1378 :
1379 : return ret;
1380 : }
1381 :
1382 0 : static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
1383 : {
1384 : SmuMetrics_t metrics_table;
1385 0 : int ret = 0;
1386 :
1387 0 : ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1388 0 : if (ret)
1389 : return ret;
1390 :
1391 0 : *query = metrics_table.CurrSocketPower << 8;
1392 :
1393 0 : return ret;
1394 : }
1395 :
1396 0 : static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1397 : {
1398 0 : uint32_t gfx_clk = 0;
1399 :
1400 0 : *gfx_freq = 0;
1401 :
1402 0 : PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
1403 : PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16),
1404 : &gfx_clk) == 0,
1405 : "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1406 : return -EINVAL);
1407 :
1408 0 : *gfx_freq = gfx_clk * 100;
1409 :
1410 0 : return 0;
1411 : }
1412 :
1413 0 : static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1414 : {
1415 0 : uint32_t mem_clk = 0;
1416 :
1417 0 : *mclk_freq = 0;
1418 :
1419 0 : PP_ASSERT_WITH_CODE(
1420 : smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16),
1421 : &mem_clk) == 0,
1422 : "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1423 : return -EINVAL);
1424 :
1425 0 : *mclk_freq = mem_clk * 100;
1426 :
1427 0 : return 0;
1428 : }
1429 :
1430 0 : static int vega12_get_current_activity_percent(
1431 : struct pp_hwmgr *hwmgr,
1432 : int idx,
1433 : uint32_t *activity_percent)
1434 : {
1435 : SmuMetrics_t metrics_table;
1436 0 : int ret = 0;
1437 :
1438 0 : ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1439 0 : if (ret)
1440 : return ret;
1441 :
1442 0 : switch (idx) {
1443 : case AMDGPU_PP_SENSOR_GPU_LOAD:
1444 0 : *activity_percent = metrics_table.AverageGfxActivity;
1445 0 : break;
1446 : case AMDGPU_PP_SENSOR_MEM_LOAD:
1447 0 : *activity_percent = metrics_table.AverageUclkActivity;
1448 0 : break;
1449 : default:
1450 0 : pr_err("Invalid index for retrieving clock activity\n");
1451 0 : return -EINVAL;
1452 : }
1453 :
1454 : return ret;
1455 : }
1456 :
1457 0 : static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1458 : void *value, int *size)
1459 : {
1460 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1461 : SmuMetrics_t metrics_table;
1462 0 : int ret = 0;
1463 :
1464 0 : switch (idx) {
1465 : case AMDGPU_PP_SENSOR_GFX_SCLK:
1466 0 : ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1467 0 : if (!ret)
1468 0 : *size = 4;
1469 : break;
1470 : case AMDGPU_PP_SENSOR_GFX_MCLK:
1471 0 : ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1472 0 : if (!ret)
1473 0 : *size = 4;
1474 : break;
1475 : case AMDGPU_PP_SENSOR_GPU_LOAD:
1476 : case AMDGPU_PP_SENSOR_MEM_LOAD:
1477 0 : ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
1478 0 : if (!ret)
1479 0 : *size = 4;
1480 : break;
1481 : case AMDGPU_PP_SENSOR_GPU_TEMP:
1482 0 : *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
1483 0 : *size = 4;
1484 0 : break;
1485 : case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1486 0 : ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1487 0 : if (ret)
1488 : return ret;
1489 :
1490 0 : *((uint32_t *)value) = metrics_table.TemperatureHotspot *
1491 : PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1492 0 : *size = 4;
1493 0 : break;
1494 : case AMDGPU_PP_SENSOR_MEM_TEMP:
1495 0 : ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1496 0 : if (ret)
1497 : return ret;
1498 :
1499 0 : *((uint32_t *)value) = metrics_table.TemperatureHBM *
1500 : PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1501 0 : *size = 4;
1502 0 : break;
1503 : case AMDGPU_PP_SENSOR_UVD_POWER:
1504 0 : *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1505 0 : *size = 4;
1506 0 : break;
1507 : case AMDGPU_PP_SENSOR_VCE_POWER:
1508 0 : *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1509 0 : *size = 4;
1510 0 : break;
1511 : case AMDGPU_PP_SENSOR_GPU_POWER:
1512 0 : ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
1513 0 : if (!ret)
1514 0 : *size = 4;
1515 : break;
1516 : case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1517 0 : ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1518 0 : if (!ret)
1519 0 : *size = 8;
1520 : break;
1521 : default:
1522 : ret = -EOPNOTSUPP;
1523 : break;
1524 : }
1525 : return ret;
1526 : }
1527 :
1528 : static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1529 : bool has_disp)
1530 : {
1531 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1532 :
1533 0 : if (data->smu_features[GNLD_DPM_UCLK].enabled)
1534 0 : return smum_send_msg_to_smc_with_parameter(hwmgr,
1535 : PPSMC_MSG_SetUclkFastSwitch,
1536 : has_disp ? 1 : 0,
1537 : NULL);
1538 :
1539 : return 0;
1540 : }
1541 :
1542 0 : static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1543 : struct pp_display_clock_request *clock_req)
1544 : {
1545 0 : int result = 0;
1546 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1547 0 : enum amd_pp_clock_type clk_type = clock_req->clock_type;
1548 0 : uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1549 0 : PPCLK_e clk_select = 0;
1550 0 : uint32_t clk_request = 0;
1551 :
1552 0 : if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1553 0 : switch (clk_type) {
1554 : case amd_pp_dcef_clock:
1555 : clk_select = PPCLK_DCEFCLK;
1556 : break;
1557 : case amd_pp_disp_clock:
1558 0 : clk_select = PPCLK_DISPCLK;
1559 0 : break;
1560 : case amd_pp_pixel_clock:
1561 0 : clk_select = PPCLK_PIXCLK;
1562 0 : break;
1563 : case amd_pp_phy_clock:
1564 0 : clk_select = PPCLK_PHYCLK;
1565 0 : break;
1566 : default:
1567 0 : pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
1568 0 : result = -1;
1569 0 : break;
1570 : }
1571 :
1572 0 : if (!result) {
1573 0 : clk_request = (clk_select << 16) | clk_freq;
1574 0 : result = smum_send_msg_to_smc_with_parameter(hwmgr,
1575 : PPSMC_MSG_SetHardMinByFreq,
1576 : clk_request,
1577 : NULL);
1578 : }
1579 : }
1580 :
1581 0 : return result;
1582 : }
1583 :
1584 0 : static int vega12_notify_smc_display_config_after_ps_adjustment(
1585 : struct pp_hwmgr *hwmgr)
1586 : {
1587 0 : struct vega12_hwmgr *data =
1588 : (struct vega12_hwmgr *)(hwmgr->backend);
1589 0 : struct PP_Clocks min_clocks = {0};
1590 : struct pp_display_clock_request clock_req;
1591 :
1592 0 : if ((hwmgr->display_config->num_display > 1) &&
1593 0 : !hwmgr->display_config->multi_monitor_in_sync &&
1594 0 : !hwmgr->display_config->nb_pstate_switch_disable)
1595 : vega12_notify_smc_display_change(hwmgr, false);
1596 : else
1597 : vega12_notify_smc_display_change(hwmgr, true);
1598 :
1599 0 : min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1600 0 : min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1601 0 : min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1602 :
1603 0 : if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1604 0 : clock_req.clock_type = amd_pp_dcef_clock;
1605 0 : clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1606 0 : if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
1607 0 : if (data->smu_features[GNLD_DS_DCEFCLK].supported)
1608 0 : PP_ASSERT_WITH_CODE(
1609 : !smum_send_msg_to_smc_with_parameter(
1610 : hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
1611 : min_clocks.dcefClockInSR /100,
1612 : NULL),
1613 : "Attempt to set divider for DCEFCLK Failed!",
1614 : return -1);
1615 : } else {
1616 0 : pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1617 : }
1618 : }
1619 :
1620 : return 0;
1621 : }
1622 :
1623 0 : static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
1624 : {
1625 0 : struct vega12_hwmgr *data =
1626 : (struct vega12_hwmgr *)(hwmgr->backend);
1627 :
1628 : uint32_t soft_level;
1629 :
1630 0 : soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
1631 :
1632 0 : data->dpm_table.gfx_table.dpm_state.soft_min_level =
1633 0 : data->dpm_table.gfx_table.dpm_state.soft_max_level =
1634 0 : data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1635 :
1636 0 : soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
1637 :
1638 0 : data->dpm_table.mem_table.dpm_state.soft_min_level =
1639 0 : data->dpm_table.mem_table.dpm_state.soft_max_level =
1640 0 : data->dpm_table.mem_table.dpm_levels[soft_level].value;
1641 :
1642 0 : PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1643 : "Failed to upload boot level to highest!",
1644 : return -1);
1645 :
1646 0 : PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1647 : "Failed to upload dpm max level to highest!",
1648 : return -1);
1649 :
1650 : return 0;
1651 : }
1652 :
1653 0 : static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1654 : {
1655 0 : struct vega12_hwmgr *data =
1656 : (struct vega12_hwmgr *)(hwmgr->backend);
1657 : uint32_t soft_level;
1658 :
1659 0 : soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
1660 :
1661 0 : data->dpm_table.gfx_table.dpm_state.soft_min_level =
1662 0 : data->dpm_table.gfx_table.dpm_state.soft_max_level =
1663 0 : data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1664 :
1665 0 : soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
1666 :
1667 0 : data->dpm_table.mem_table.dpm_state.soft_min_level =
1668 0 : data->dpm_table.mem_table.dpm_state.soft_max_level =
1669 0 : data->dpm_table.mem_table.dpm_levels[soft_level].value;
1670 :
1671 0 : PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1672 : "Failed to upload boot level to highest!",
1673 : return -1);
1674 :
1675 0 : PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1676 : "Failed to upload dpm max level to highest!",
1677 : return -1);
1678 :
1679 : return 0;
1680 :
1681 : }
1682 :
1683 0 : static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1684 : {
1685 0 : PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1686 : "Failed to upload DPM Bootup Levels!",
1687 : return -1);
1688 :
1689 0 : PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1690 : "Failed to upload DPM Max Levels!",
1691 : return -1);
1692 :
1693 : return 0;
1694 : }
1695 :
1696 0 : static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
1697 : uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1698 : {
1699 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1700 0 : struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1701 0 : struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1702 0 : struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
1703 :
1704 0 : *sclk_mask = 0;
1705 0 : *mclk_mask = 0;
1706 0 : *soc_mask = 0;
1707 :
1708 0 : if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1709 0 : mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL &&
1710 0 : soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) {
1711 0 : *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1712 0 : *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1713 0 : *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1714 : }
1715 :
1716 0 : if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1717 0 : *sclk_mask = 0;
1718 0 : } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1719 0 : *mclk_mask = 0;
1720 0 : } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1721 0 : *sclk_mask = gfx_dpm_table->count - 1;
1722 0 : *mclk_mask = mem_dpm_table->count - 1;
1723 0 : *soc_mask = soc_dpm_table->count - 1;
1724 : }
1725 :
1726 0 : return 0;
1727 : }
1728 :
1729 0 : static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
1730 : {
1731 0 : switch (mode) {
1732 : case AMD_FAN_CTRL_NONE:
1733 : break;
1734 : case AMD_FAN_CTRL_MANUAL:
1735 0 : if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1736 0 : vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
1737 : break;
1738 : case AMD_FAN_CTRL_AUTO:
1739 0 : if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1740 0 : vega12_fan_ctrl_start_smc_fan_control(hwmgr);
1741 : break;
1742 : default:
1743 : break;
1744 : }
1745 0 : }
1746 :
1747 0 : static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1748 : enum amd_dpm_forced_level level)
1749 : {
1750 0 : int ret = 0;
1751 0 : uint32_t sclk_mask = 0;
1752 0 : uint32_t mclk_mask = 0;
1753 0 : uint32_t soc_mask = 0;
1754 :
1755 0 : switch (level) {
1756 : case AMD_DPM_FORCED_LEVEL_HIGH:
1757 0 : ret = vega12_force_dpm_highest(hwmgr);
1758 0 : break;
1759 : case AMD_DPM_FORCED_LEVEL_LOW:
1760 0 : ret = vega12_force_dpm_lowest(hwmgr);
1761 0 : break;
1762 : case AMD_DPM_FORCED_LEVEL_AUTO:
1763 0 : ret = vega12_unforce_dpm_levels(hwmgr);
1764 0 : break;
1765 : case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1766 : case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1767 : case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1768 : case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1769 0 : ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1770 0 : if (ret)
1771 : return ret;
1772 0 : vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
1773 0 : vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1774 0 : break;
1775 : case AMD_DPM_FORCED_LEVEL_MANUAL:
1776 : case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1777 : default:
1778 : break;
1779 : }
1780 :
1781 : return ret;
1782 : }
1783 :
1784 0 : static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
1785 : {
1786 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1787 :
1788 0 : if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
1789 : return AMD_FAN_CTRL_MANUAL;
1790 : else
1791 0 : return AMD_FAN_CTRL_AUTO;
1792 : }
1793 :
1794 0 : static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
1795 : struct amd_pp_simple_clock_info *info)
1796 : {
1797 : #if 0
1798 : struct phm_ppt_v2_information *table_info =
1799 : (struct phm_ppt_v2_information *)hwmgr->pptable;
1800 : struct phm_clock_and_voltage_limits *max_limits =
1801 : &table_info->max_clock_voltage_on_ac;
1802 :
1803 : info->engine_max_clock = max_limits->sclk;
1804 : info->memory_max_clock = max_limits->mclk;
1805 : #endif
1806 0 : return 0;
1807 : }
1808 :
1809 : static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
1810 : uint32_t *clock,
1811 : PPCLK_e clock_select,
1812 : bool max)
1813 : {
1814 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1815 :
1816 : if (max)
1817 0 : *clock = data->clk_range[clock_select].ACMax;
1818 : else
1819 0 : *clock = data->clk_range[clock_select].ACMin;
1820 :
1821 : return 0;
1822 : }
1823 :
1824 : static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
1825 : struct pp_clock_levels_with_latency *clocks)
1826 : {
1827 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1828 : uint32_t ucount;
1829 : int i;
1830 : struct vega12_single_dpm_table *dpm_table;
1831 :
1832 0 : if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1833 : return -1;
1834 :
1835 0 : dpm_table = &(data->dpm_table.gfx_table);
1836 0 : ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1837 0 : MAX_NUM_CLOCKS : dpm_table->count;
1838 :
1839 0 : for (i = 0; i < ucount; i++) {
1840 0 : clocks->data[i].clocks_in_khz =
1841 0 : dpm_table->dpm_levels[i].value * 1000;
1842 :
1843 0 : clocks->data[i].latency_in_us = 0;
1844 : }
1845 :
1846 0 : clocks->num_levels = ucount;
1847 :
1848 : return 0;
1849 : }
1850 :
1851 : static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
1852 : uint32_t clock)
1853 : {
1854 : return 25;
1855 : }
1856 :
1857 : static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
1858 : struct pp_clock_levels_with_latency *clocks)
1859 : {
1860 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1861 : uint32_t ucount;
1862 : int i;
1863 : struct vega12_single_dpm_table *dpm_table;
1864 0 : if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1865 : return -1;
1866 :
1867 0 : dpm_table = &(data->dpm_table.mem_table);
1868 0 : ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1869 0 : MAX_NUM_CLOCKS : dpm_table->count;
1870 :
1871 0 : for (i = 0; i < ucount; i++) {
1872 0 : clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1873 0 : data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
1874 0 : clocks->data[i].latency_in_us =
1875 0 : data->mclk_latency_table.entries[i].latency =
1876 0 : vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
1877 : }
1878 :
1879 0 : clocks->num_levels = data->mclk_latency_table.count = ucount;
1880 :
1881 : return 0;
1882 : }
1883 :
1884 : static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
1885 : struct pp_clock_levels_with_latency *clocks)
1886 : {
1887 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1888 : uint32_t ucount;
1889 : int i;
1890 : struct vega12_single_dpm_table *dpm_table;
1891 :
1892 0 : if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
1893 : return -1;
1894 :
1895 :
1896 0 : dpm_table = &(data->dpm_table.dcef_table);
1897 0 : ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1898 0 : MAX_NUM_CLOCKS : dpm_table->count;
1899 :
1900 0 : for (i = 0; i < ucount; i++) {
1901 0 : clocks->data[i].clocks_in_khz =
1902 0 : dpm_table->dpm_levels[i].value * 1000;
1903 :
1904 0 : clocks->data[i].latency_in_us = 0;
1905 : }
1906 :
1907 0 : clocks->num_levels = ucount;
1908 :
1909 : return 0;
1910 : }
1911 :
1912 : static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
1913 : struct pp_clock_levels_with_latency *clocks)
1914 : {
1915 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1916 : uint32_t ucount;
1917 : int i;
1918 : struct vega12_single_dpm_table *dpm_table;
1919 :
1920 0 : if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
1921 : return -1;
1922 :
1923 :
1924 0 : dpm_table = &(data->dpm_table.soc_table);
1925 0 : ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1926 0 : MAX_NUM_CLOCKS : dpm_table->count;
1927 :
1928 0 : for (i = 0; i < ucount; i++) {
1929 0 : clocks->data[i].clocks_in_khz =
1930 0 : dpm_table->dpm_levels[i].value * 1000;
1931 :
1932 0 : clocks->data[i].latency_in_us = 0;
1933 : }
1934 :
1935 0 : clocks->num_levels = ucount;
1936 :
1937 : return 0;
1938 :
1939 : }
1940 :
1941 0 : static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1942 : enum amd_pp_clock_type type,
1943 : struct pp_clock_levels_with_latency *clocks)
1944 : {
1945 : int ret;
1946 :
1947 0 : switch (type) {
1948 : case amd_pp_sys_clock:
1949 0 : ret = vega12_get_sclks(hwmgr, clocks);
1950 : break;
1951 : case amd_pp_mem_clock:
1952 0 : ret = vega12_get_memclocks(hwmgr, clocks);
1953 : break;
1954 : case amd_pp_dcef_clock:
1955 0 : ret = vega12_get_dcefclocks(hwmgr, clocks);
1956 : break;
1957 : case amd_pp_soc_clock:
1958 0 : ret = vega12_get_socclocks(hwmgr, clocks);
1959 : break;
1960 : default:
1961 : return -EINVAL;
1962 : }
1963 :
1964 : return ret;
1965 : }
1966 :
1967 0 : static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1968 : enum amd_pp_clock_type type,
1969 : struct pp_clock_levels_with_voltage *clocks)
1970 : {
1971 0 : clocks->num_levels = 0;
1972 :
1973 0 : return 0;
1974 : }
1975 :
1976 0 : static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1977 : void *clock_ranges)
1978 : {
1979 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1980 0 : Watermarks_t *table = &(data->smc_state_table.water_marks_table);
1981 0 : struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1982 :
1983 0 : if (!data->registry_data.disable_water_mark &&
1984 0 : data->smu_features[GNLD_DPM_DCEFCLK].supported &&
1985 0 : data->smu_features[GNLD_DPM_SOCCLK].supported) {
1986 0 : smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
1987 0 : data->water_marks_bitmap |= WaterMarksExist;
1988 0 : data->water_marks_bitmap &= ~WaterMarksLoaded;
1989 : }
1990 :
1991 0 : return 0;
1992 : }
1993 :
1994 0 : static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
1995 : enum pp_clock_type type, uint32_t mask)
1996 : {
1997 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1998 : uint32_t soft_min_level, soft_max_level, hard_min_level;
1999 0 : int ret = 0;
2000 :
2001 0 : switch (type) {
2002 : case PP_SCLK:
2003 0 : soft_min_level = mask ? (ffs(mask) - 1) : 0;
2004 0 : soft_max_level = mask ? (fls(mask) - 1) : 0;
2005 :
2006 0 : data->dpm_table.gfx_table.dpm_state.soft_min_level =
2007 0 : data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2008 0 : data->dpm_table.gfx_table.dpm_state.soft_max_level =
2009 0 : data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2010 :
2011 0 : ret = vega12_upload_dpm_min_level(hwmgr);
2012 0 : PP_ASSERT_WITH_CODE(!ret,
2013 : "Failed to upload boot level to lowest!",
2014 : return ret);
2015 :
2016 0 : ret = vega12_upload_dpm_max_level(hwmgr);
2017 0 : PP_ASSERT_WITH_CODE(!ret,
2018 : "Failed to upload dpm max level to highest!",
2019 : return ret);
2020 : break;
2021 :
2022 : case PP_MCLK:
2023 0 : soft_min_level = mask ? (ffs(mask) - 1) : 0;
2024 0 : soft_max_level = mask ? (fls(mask) - 1) : 0;
2025 :
2026 0 : data->dpm_table.mem_table.dpm_state.soft_min_level =
2027 0 : data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2028 0 : data->dpm_table.mem_table.dpm_state.soft_max_level =
2029 0 : data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2030 :
2031 0 : ret = vega12_upload_dpm_min_level(hwmgr);
2032 0 : PP_ASSERT_WITH_CODE(!ret,
2033 : "Failed to upload boot level to lowest!",
2034 : return ret);
2035 :
2036 0 : ret = vega12_upload_dpm_max_level(hwmgr);
2037 0 : PP_ASSERT_WITH_CODE(!ret,
2038 : "Failed to upload dpm max level to highest!",
2039 : return ret);
2040 :
2041 : break;
2042 :
2043 : case PP_SOCCLK:
2044 0 : soft_min_level = mask ? (ffs(mask) - 1) : 0;
2045 0 : soft_max_level = mask ? (fls(mask) - 1) : 0;
2046 :
2047 0 : if (soft_max_level >= data->dpm_table.soc_table.count) {
2048 0 : pr_err("Clock level specified %d is over max allowed %d\n",
2049 : soft_max_level,
2050 : data->dpm_table.soc_table.count - 1);
2051 0 : return -EINVAL;
2052 : }
2053 :
2054 0 : data->dpm_table.soc_table.dpm_state.soft_min_level =
2055 0 : data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2056 0 : data->dpm_table.soc_table.dpm_state.soft_max_level =
2057 0 : data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2058 :
2059 0 : ret = vega12_upload_dpm_min_level(hwmgr);
2060 0 : PP_ASSERT_WITH_CODE(!ret,
2061 : "Failed to upload boot level to lowest!",
2062 : return ret);
2063 :
2064 0 : ret = vega12_upload_dpm_max_level(hwmgr);
2065 0 : PP_ASSERT_WITH_CODE(!ret,
2066 : "Failed to upload dpm max level to highest!",
2067 : return ret);
2068 :
2069 : break;
2070 :
2071 : case PP_DCEFCLK:
2072 0 : hard_min_level = mask ? (ffs(mask) - 1) : 0;
2073 :
2074 0 : if (hard_min_level >= data->dpm_table.dcef_table.count) {
2075 0 : pr_err("Clock level specified %d is over max allowed %d\n",
2076 : hard_min_level,
2077 : data->dpm_table.dcef_table.count - 1);
2078 0 : return -EINVAL;
2079 : }
2080 :
2081 0 : data->dpm_table.dcef_table.dpm_state.hard_min_level =
2082 0 : data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2083 :
2084 0 : ret = vega12_upload_dpm_min_level(hwmgr);
2085 0 : PP_ASSERT_WITH_CODE(!ret,
2086 : "Failed to upload boot level to lowest!",
2087 : return ret);
2088 :
2089 : //TODO: Setting DCEFCLK max dpm level is not supported
2090 :
2091 : break;
2092 :
2093 : case PP_PCIE:
2094 : break;
2095 :
2096 : default:
2097 : break;
2098 : }
2099 :
2100 : return 0;
2101 : }
2102 :
2103 0 : static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
2104 : {
2105 : static const char *ppfeature_name[] = {
2106 : "DPM_PREFETCHER",
2107 : "GFXCLK_DPM",
2108 : "UCLK_DPM",
2109 : "SOCCLK_DPM",
2110 : "UVD_DPM",
2111 : "VCE_DPM",
2112 : "ULV",
2113 : "MP0CLK_DPM",
2114 : "LINK_DPM",
2115 : "DCEFCLK_DPM",
2116 : "GFXCLK_DS",
2117 : "SOCCLK_DS",
2118 : "LCLK_DS",
2119 : "PPT",
2120 : "TDC",
2121 : "THERMAL",
2122 : "GFX_PER_CU_CG",
2123 : "RM",
2124 : "DCEFCLK_DS",
2125 : "ACDC",
2126 : "VR0HOT",
2127 : "VR1HOT",
2128 : "FW_CTF",
2129 : "LED_DISPLAY",
2130 : "FAN_CONTROL",
2131 : "DIDT",
2132 : "GFXOFF",
2133 : "CG",
2134 : "ACG"};
2135 : static const char *output_title[] = {
2136 : "FEATURES",
2137 : "BITMASK",
2138 : "ENABLEMENT"};
2139 : uint64_t features_enabled;
2140 : int i;
2141 0 : int ret = 0;
2142 0 : int size = 0;
2143 :
2144 0 : phm_get_sysfs_buf(&buf, &size);
2145 :
2146 0 : ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2147 0 : PP_ASSERT_WITH_CODE(!ret,
2148 : "[EnableAllSmuFeatures] Failed to get enabled smc features!",
2149 : return ret);
2150 :
2151 0 : size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2152 0 : size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
2153 : output_title[0],
2154 : output_title[1],
2155 : output_title[2]);
2156 0 : for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2157 0 : size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
2158 : ppfeature_name[i],
2159 : 1ULL << i,
2160 0 : (features_enabled & (1ULL << i)) ? "Y" : "N");
2161 : }
2162 :
2163 : return size;
2164 : }
2165 :
2166 0 : static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
2167 : {
2168 : uint64_t features_enabled;
2169 : uint64_t features_to_enable;
2170 : uint64_t features_to_disable;
2171 0 : int ret = 0;
2172 :
2173 0 : if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2174 : return -EINVAL;
2175 :
2176 0 : ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2177 0 : if (ret)
2178 : return ret;
2179 :
2180 0 : features_to_disable =
2181 0 : features_enabled & ~new_ppfeature_masks;
2182 0 : features_to_enable =
2183 0 : ~features_enabled & new_ppfeature_masks;
2184 :
2185 : pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2186 : pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2187 :
2188 0 : if (features_to_disable) {
2189 0 : ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
2190 0 : if (ret)
2191 : return ret;
2192 : }
2193 :
2194 0 : if (features_to_enable) {
2195 0 : ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);
2196 0 : if (ret)
2197 : return ret;
2198 : }
2199 :
2200 : return 0;
2201 : }
2202 :
2203 : static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
2204 : {
2205 0 : struct amdgpu_device *adev = hwmgr->adev;
2206 :
2207 0 : return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2208 : PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2209 0 : >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2210 : }
2211 :
2212 : static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
2213 : {
2214 : uint32_t width_level;
2215 :
2216 0 : width_level = vega12_get_current_pcie_link_width_level(hwmgr);
2217 0 : if (width_level > LINK_WIDTH_MAX)
2218 0 : width_level = 0;
2219 :
2220 0 : return link_width[width_level];
2221 : }
2222 :
2223 : static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
2224 : {
2225 0 : struct amdgpu_device *adev = hwmgr->adev;
2226 :
2227 0 : return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2228 : PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2229 0 : >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2230 : }
2231 :
2232 : static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
2233 : {
2234 : uint32_t speed_level;
2235 :
2236 0 : speed_level = vega12_get_current_pcie_link_speed_level(hwmgr);
2237 0 : if (speed_level > LINK_SPEED_MAX)
2238 0 : speed_level = 0;
2239 :
2240 0 : return link_speed[speed_level];
2241 : }
2242 :
2243 0 : static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
2244 : enum pp_clock_type type, char *buf)
2245 : {
2246 0 : int i, now, size = 0;
2247 : struct pp_clock_levels_with_latency clocks;
2248 :
2249 0 : switch (type) {
2250 : case PP_SCLK:
2251 0 : PP_ASSERT_WITH_CODE(
2252 : vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
2253 : "Attempt to get current gfx clk Failed!",
2254 : return -1);
2255 :
2256 0 : PP_ASSERT_WITH_CODE(
2257 : vega12_get_sclks(hwmgr, &clocks) == 0,
2258 : "Attempt to get gfx clk levels Failed!",
2259 : return -1);
2260 0 : for (i = 0; i < clocks.num_levels; i++)
2261 0 : size += sprintf(buf + size, "%d: %uMhz %s\n",
2262 : i, clocks.data[i].clocks_in_khz / 1000,
2263 0 : (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2264 : break;
2265 :
2266 : case PP_MCLK:
2267 0 : PP_ASSERT_WITH_CODE(
2268 : vega12_get_current_mclk_freq(hwmgr, &now) == 0,
2269 : "Attempt to get current mclk freq Failed!",
2270 : return -1);
2271 :
2272 0 : PP_ASSERT_WITH_CODE(
2273 : vega12_get_memclocks(hwmgr, &clocks) == 0,
2274 : "Attempt to get memory clk levels Failed!",
2275 : return -1);
2276 0 : for (i = 0; i < clocks.num_levels; i++)
2277 0 : size += sprintf(buf + size, "%d: %uMhz %s\n",
2278 : i, clocks.data[i].clocks_in_khz / 1000,
2279 0 : (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2280 : break;
2281 :
2282 : case PP_SOCCLK:
2283 0 : PP_ASSERT_WITH_CODE(
2284 : smum_send_msg_to_smc_with_parameter(hwmgr,
2285 : PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16),
2286 : &now) == 0,
2287 : "Attempt to get Current SOCCLK Frequency Failed!",
2288 : return -EINVAL);
2289 :
2290 0 : PP_ASSERT_WITH_CODE(
2291 : vega12_get_socclocks(hwmgr, &clocks) == 0,
2292 : "Attempt to get soc clk levels Failed!",
2293 : return -1);
2294 0 : for (i = 0; i < clocks.num_levels; i++)
2295 0 : size += sprintf(buf + size, "%d: %uMhz %s\n",
2296 : i, clocks.data[i].clocks_in_khz / 1000,
2297 0 : (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2298 : break;
2299 :
2300 : case PP_DCEFCLK:
2301 0 : PP_ASSERT_WITH_CODE(
2302 : smum_send_msg_to_smc_with_parameter(hwmgr,
2303 : PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16),
2304 : &now) == 0,
2305 : "Attempt to get Current DCEFCLK Frequency Failed!",
2306 : return -EINVAL);
2307 :
2308 0 : PP_ASSERT_WITH_CODE(
2309 : vega12_get_dcefclocks(hwmgr, &clocks) == 0,
2310 : "Attempt to get dcef clk levels Failed!",
2311 : return -1);
2312 0 : for (i = 0; i < clocks.num_levels; i++)
2313 0 : size += sprintf(buf + size, "%d: %uMhz %s\n",
2314 : i, clocks.data[i].clocks_in_khz / 1000,
2315 0 : (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2316 : break;
2317 :
2318 : case PP_PCIE:
2319 : break;
2320 :
2321 : default:
2322 : break;
2323 : }
2324 : return size;
2325 : }
2326 :
2327 0 : static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
2328 : {
2329 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2330 : struct vega12_single_dpm_table *dpm_table;
2331 0 : bool vblank_too_short = false;
2332 : bool disable_mclk_switching;
2333 : uint32_t i, latency;
2334 :
2335 0 : disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2336 0 : !hwmgr->display_config->multi_monitor_in_sync) ||
2337 : vblank_too_short;
2338 0 : latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
2339 :
2340 : /* gfxclk */
2341 0 : dpm_table = &(data->dpm_table.gfx_table);
2342 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2343 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2344 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2345 0 : dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2346 :
2347 0 : if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2348 0 : if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2349 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2350 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2351 : }
2352 :
2353 0 : if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2354 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2355 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2356 : }
2357 :
2358 0 : if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2359 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2360 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2361 : }
2362 : }
2363 :
2364 : /* memclk */
2365 0 : dpm_table = &(data->dpm_table.mem_table);
2366 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2367 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2368 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2369 0 : dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2370 :
2371 0 : if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2372 0 : if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2373 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2374 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2375 : }
2376 :
2377 0 : if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2378 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2379 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2380 : }
2381 :
2382 0 : if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2383 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2384 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2385 : }
2386 : }
2387 :
2388 : /* honour DAL's UCLK Hardmin */
2389 0 : if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
2390 0 : dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
2391 :
2392 : /* Hardmin is dependent on displayconfig */
2393 0 : if (disable_mclk_switching) {
2394 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2395 0 : for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
2396 0 : if (data->mclk_latency_table.entries[i].latency <= latency) {
2397 0 : if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
2398 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2399 0 : break;
2400 : }
2401 : }
2402 : }
2403 : }
2404 :
2405 0 : if (hwmgr->display_config->nb_pstate_switch_disable)
2406 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2407 :
2408 : /* vclk */
2409 0 : dpm_table = &(data->dpm_table.vclk_table);
2410 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2411 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2412 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2413 0 : dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2414 :
2415 0 : if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2416 0 : if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2417 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2418 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2419 : }
2420 :
2421 0 : if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2422 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2423 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2424 : }
2425 : }
2426 :
2427 : /* dclk */
2428 0 : dpm_table = &(data->dpm_table.dclk_table);
2429 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2430 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2431 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2432 0 : dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2433 :
2434 0 : if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2435 0 : if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2436 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2437 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2438 : }
2439 :
2440 0 : if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2441 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2442 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2443 : }
2444 : }
2445 :
2446 : /* socclk */
2447 0 : dpm_table = &(data->dpm_table.soc_table);
2448 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2449 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2450 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2451 0 : dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2452 :
2453 0 : if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2454 0 : if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2455 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2456 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2457 : }
2458 :
2459 0 : if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2460 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2461 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2462 : }
2463 : }
2464 :
2465 : /* eclk */
2466 0 : dpm_table = &(data->dpm_table.eclk_table);
2467 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2468 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2469 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2470 0 : dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2471 :
2472 0 : if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2473 0 : if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2474 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2475 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2476 : }
2477 :
2478 0 : if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2479 0 : dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2480 0 : dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2481 : }
2482 : }
2483 :
2484 0 : return 0;
2485 : }
2486 :
2487 0 : static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2488 : struct vega12_single_dpm_table *dpm_table)
2489 : {
2490 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2491 0 : int ret = 0;
2492 :
2493 0 : if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2494 0 : PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2495 : "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2496 : return -EINVAL);
2497 0 : PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2498 : "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2499 : return -EINVAL);
2500 :
2501 0 : dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2502 0 : PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2503 : PPSMC_MSG_SetHardMinByFreq,
2504 : (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
2505 : NULL)),
2506 : "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2507 : return ret);
2508 : }
2509 :
2510 : return ret;
2511 : }
2512 :
2513 0 : static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2514 : {
2515 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2516 0 : int ret = 0;
2517 :
2518 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2519 : PPSMC_MSG_NumOfDisplays, 0,
2520 : NULL);
2521 :
2522 0 : ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
2523 : &data->dpm_table.mem_table);
2524 :
2525 0 : return ret;
2526 : }
2527 :
2528 0 : static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2529 : {
2530 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2531 0 : int result = 0;
2532 0 : Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2533 :
2534 0 : if ((data->water_marks_bitmap & WaterMarksExist) &&
2535 : !(data->water_marks_bitmap & WaterMarksLoaded)) {
2536 0 : result = smum_smc_table_manager(hwmgr,
2537 : (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2538 0 : PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
2539 0 : data->water_marks_bitmap |= WaterMarksLoaded;
2540 : }
2541 :
2542 0 : if ((data->water_marks_bitmap & WaterMarksExist) &&
2543 0 : data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2544 0 : data->smu_features[GNLD_DPM_SOCCLK].supported)
2545 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2546 0 : PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
2547 : NULL);
2548 :
2549 : return result;
2550 : }
2551 :
2552 0 : static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2553 : {
2554 0 : struct vega12_hwmgr *data =
2555 : (struct vega12_hwmgr *)(hwmgr->backend);
2556 :
2557 0 : if (data->smu_features[GNLD_DPM_UVD].supported) {
2558 0 : PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
2559 : enable,
2560 : data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
2561 : "Attempt to Enable/Disable DPM UVD Failed!",
2562 : return -1);
2563 0 : data->smu_features[GNLD_DPM_UVD].enabled = enable;
2564 : }
2565 :
2566 : return 0;
2567 : }
2568 :
2569 0 : static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2570 : {
2571 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2572 :
2573 0 : if (data->vce_power_gated == bgate)
2574 : return;
2575 :
2576 0 : data->vce_power_gated = bgate;
2577 0 : vega12_enable_disable_vce_dpm(hwmgr, !bgate);
2578 : }
2579 :
2580 0 : static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2581 : {
2582 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2583 :
2584 0 : if (data->uvd_power_gated == bgate)
2585 : return;
2586 :
2587 0 : data->uvd_power_gated = bgate;
2588 0 : vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
2589 : }
2590 :
2591 : static bool
2592 0 : vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
2593 : {
2594 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2595 0 : bool is_update_required = false;
2596 :
2597 0 : if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2598 0 : is_update_required = true;
2599 :
2600 0 : if (data->registry_data.gfx_clk_deep_sleep_support) {
2601 0 : if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
2602 0 : is_update_required = true;
2603 : }
2604 :
2605 0 : return is_update_required;
2606 : }
2607 :
2608 0 : static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2609 : {
2610 0 : int tmp_result, result = 0;
2611 :
2612 0 : tmp_result = vega12_disable_all_smu_features(hwmgr);
2613 0 : PP_ASSERT_WITH_CODE((tmp_result == 0),
2614 : "Failed to disable all smu features!", result = tmp_result);
2615 :
2616 0 : return result;
2617 : }
2618 :
2619 0 : static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
2620 : {
2621 0 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2622 : int result;
2623 :
2624 0 : result = vega12_disable_dpm_tasks(hwmgr);
2625 0 : PP_ASSERT_WITH_CODE((0 == result),
2626 : "[disable_dpm_tasks] Failed to disable DPM!",
2627 : );
2628 0 : data->water_marks_bitmap &= ~(WaterMarksLoaded);
2629 :
2630 0 : return result;
2631 : }
2632 :
2633 : #if 0
2634 : static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2635 : uint32_t *sclk_idx, uint32_t *mclk_idx,
2636 : uint32_t min_sclk, uint32_t min_mclk)
2637 : {
2638 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2639 : struct vega12_dpm_table *dpm_table = &(data->dpm_table);
2640 : uint32_t i;
2641 :
2642 : for (i = 0; i < dpm_table->gfx_table.count; i++) {
2643 : if (dpm_table->gfx_table.dpm_levels[i].enabled &&
2644 : dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
2645 : *sclk_idx = i;
2646 : break;
2647 : }
2648 : }
2649 :
2650 : for (i = 0; i < dpm_table->mem_table.count; i++) {
2651 : if (dpm_table->mem_table.dpm_levels[i].enabled &&
2652 : dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
2653 : *mclk_idx = i;
2654 : break;
2655 : }
2656 : }
2657 : }
2658 : #endif
2659 :
2660 : #if 0
2661 : static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2662 : struct amd_pp_profile *request)
2663 : {
2664 : return 0;
2665 : }
2666 :
2667 : static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2668 : {
2669 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2670 : struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2671 : struct vega12_single_dpm_table *golden_sclk_table =
2672 : &(data->golden_dpm_table.gfx_table);
2673 : int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2674 : int golden_value = golden_sclk_table->dpm_levels
2675 : [golden_sclk_table->count - 1].value;
2676 :
2677 : value -= golden_value;
2678 : value = DIV_ROUND_UP(value * 100, golden_value);
2679 :
2680 : return value;
2681 : }
2682 :
2683 : static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2684 : {
2685 : return 0;
2686 : }
2687 :
2688 : static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2689 : {
2690 : struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2691 : struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2692 : struct vega12_single_dpm_table *golden_mclk_table =
2693 : &(data->golden_dpm_table.mem_table);
2694 : int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2695 : int golden_value = golden_mclk_table->dpm_levels
2696 : [golden_mclk_table->count - 1].value;
2697 :
2698 : value -= golden_value;
2699 : value = DIV_ROUND_UP(value * 100, golden_value);
2700 :
2701 : return value;
2702 : }
2703 :
2704 : static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2705 : {
2706 : return 0;
2707 : }
2708 : #endif
2709 :
2710 0 : static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
2711 : uint32_t virtual_addr_low,
2712 : uint32_t virtual_addr_hi,
2713 : uint32_t mc_addr_low,
2714 : uint32_t mc_addr_hi,
2715 : uint32_t size)
2716 : {
2717 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2718 : PPSMC_MSG_SetSystemVirtualDramAddrHigh,
2719 : virtual_addr_hi,
2720 : NULL);
2721 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2722 : PPSMC_MSG_SetSystemVirtualDramAddrLow,
2723 : virtual_addr_low,
2724 : NULL);
2725 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2726 : PPSMC_MSG_DramLogSetDramAddrHigh,
2727 : mc_addr_hi,
2728 : NULL);
2729 :
2730 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2731 : PPSMC_MSG_DramLogSetDramAddrLow,
2732 : mc_addr_low,
2733 : NULL);
2734 :
2735 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2736 : PPSMC_MSG_DramLogSetDramSize,
2737 : size,
2738 : NULL);
2739 0 : return 0;
2740 : }
2741 :
2742 0 : static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2743 : struct PP_TemperatureRange *thermal_data)
2744 : {
2745 0 : struct vega12_hwmgr *data =
2746 : (struct vega12_hwmgr *)(hwmgr->backend);
2747 0 : PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2748 :
2749 0 : memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
2750 :
2751 0 : thermal_data->max = pp_table->TedgeLimit *
2752 : PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2753 0 : thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
2754 : PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2755 0 : thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
2756 : PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2757 0 : thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2758 : PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2759 0 : thermal_data->mem_crit_max = pp_table->ThbmLimit *
2760 : PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2761 0 : thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
2762 : PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2763 :
2764 0 : return 0;
2765 : }
2766 :
2767 : static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
2768 : {
2769 0 : struct vega12_hwmgr *data =
2770 : (struct vega12_hwmgr *)(hwmgr->backend);
2771 0 : int ret = 0;
2772 :
2773 0 : if (data->gfxoff_controlled_by_driver)
2774 0 : ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL);
2775 :
2776 : return ret;
2777 : }
2778 :
2779 : static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
2780 : {
2781 0 : struct vega12_hwmgr *data =
2782 : (struct vega12_hwmgr *)(hwmgr->backend);
2783 0 : int ret = 0;
2784 :
2785 0 : if (data->gfxoff_controlled_by_driver)
2786 0 : ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL);
2787 :
2788 : return ret;
2789 : }
2790 :
2791 0 : static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
2792 : {
2793 0 : if (enable)
2794 : return vega12_enable_gfx_off(hwmgr);
2795 : else
2796 : return vega12_disable_gfx_off(hwmgr);
2797 : }
2798 :
2799 0 : static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2800 : PHM_PerformanceLevelDesignation designation, uint32_t index,
2801 : PHM_PerformanceLevel *level)
2802 : {
2803 0 : return 0;
2804 : }
2805 :
2806 0 : static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
2807 : enum pp_mp1_state mp1_state)
2808 : {
2809 : uint16_t msg;
2810 : int ret;
2811 :
2812 0 : switch (mp1_state) {
2813 : case PP_MP1_STATE_UNLOAD:
2814 0 : msg = PPSMC_MSG_PrepareMp1ForUnload;
2815 : break;
2816 : case PP_MP1_STATE_SHUTDOWN:
2817 : case PP_MP1_STATE_RESET:
2818 : case PP_MP1_STATE_NONE:
2819 : default:
2820 : return 0;
2821 : }
2822 :
2823 0 : PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
2824 : "[PrepareMp1] Failed!",
2825 : return ret);
2826 :
2827 : return 0;
2828 : }
2829 :
2830 0 : static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
2831 : {
2832 0 : memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
2833 :
2834 0 : gpu_metrics->common_header.structure_size =
2835 : sizeof(struct gpu_metrics_v1_0);
2836 0 : gpu_metrics->common_header.format_revision = 1;
2837 0 : gpu_metrics->common_header.content_revision = 0;
2838 :
2839 0 : gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2840 0 : }
2841 :
2842 0 : static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr,
2843 : void **table)
2844 : {
2845 0 : struct vega12_hwmgr *data =
2846 : (struct vega12_hwmgr *)(hwmgr->backend);
2847 0 : struct gpu_metrics_v1_0 *gpu_metrics =
2848 : &data->gpu_metrics_table;
2849 : SmuMetrics_t metrics;
2850 : uint32_t fan_speed_rpm;
2851 : int ret;
2852 :
2853 0 : ret = vega12_get_metrics_table(hwmgr, &metrics, true);
2854 0 : if (ret)
2855 0 : return ret;
2856 :
2857 0 : vega12_init_gpu_metrics_v1_0(gpu_metrics);
2858 :
2859 0 : gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2860 0 : gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2861 0 : gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2862 0 : gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2863 0 : gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2864 :
2865 0 : gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2866 0 : gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2867 :
2868 0 : gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2869 0 : gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2870 0 : gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2871 :
2872 0 : gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2873 0 : gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2874 0 : gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2875 0 : gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2876 0 : gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2877 :
2878 0 : gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2879 :
2880 0 : vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm);
2881 0 : gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm;
2882 :
2883 0 : gpu_metrics->pcie_link_width =
2884 0 : vega12_get_current_pcie_link_width(hwmgr);
2885 0 : gpu_metrics->pcie_link_speed =
2886 0 : vega12_get_current_pcie_link_speed(hwmgr);
2887 :
2888 0 : *table = (void *)gpu_metrics;
2889 :
2890 0 : return sizeof(struct gpu_metrics_v1_0);
2891 : }
2892 :
2893 : static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2894 : .backend_init = vega12_hwmgr_backend_init,
2895 : .backend_fini = vega12_hwmgr_backend_fini,
2896 : .asic_setup = vega12_setup_asic_task,
2897 : .dynamic_state_management_enable = vega12_enable_dpm_tasks,
2898 : .dynamic_state_management_disable = vega12_disable_dpm_tasks,
2899 : .patch_boot_state = vega12_patch_boot_state,
2900 : .get_sclk = vega12_dpm_get_sclk,
2901 : .get_mclk = vega12_dpm_get_mclk,
2902 : .notify_smc_display_config_after_ps_adjustment =
2903 : vega12_notify_smc_display_config_after_ps_adjustment,
2904 : .force_dpm_level = vega12_dpm_force_dpm_level,
2905 : .stop_thermal_controller = vega12_thermal_stop_thermal_controller,
2906 : .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
2907 : .reset_fan_speed_to_default =
2908 : vega12_fan_ctrl_reset_fan_speed_to_default,
2909 : .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
2910 : .set_fan_control_mode = vega12_set_fan_control_mode,
2911 : .get_fan_control_mode = vega12_get_fan_control_mode,
2912 : .read_sensor = vega12_read_sensor,
2913 : .get_dal_power_level = vega12_get_dal_power_level,
2914 : .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
2915 : .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
2916 : .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
2917 : .display_clock_voltage_request = vega12_display_clock_voltage_request,
2918 : .force_clock_level = vega12_force_clock_level,
2919 : .print_clock_levels = vega12_print_clock_levels,
2920 : .apply_clocks_adjust_rules =
2921 : vega12_apply_clocks_adjust_rules,
2922 : .pre_display_config_changed =
2923 : vega12_pre_display_configuration_changed_task,
2924 : .display_config_changed = vega12_display_configuration_changed_task,
2925 : .powergate_uvd = vega12_power_gate_uvd,
2926 : .powergate_vce = vega12_power_gate_vce,
2927 : .check_smc_update_required_for_display_configuration =
2928 : vega12_check_smc_update_required_for_display_configuration,
2929 : .power_off_asic = vega12_power_off_asic,
2930 : .disable_smc_firmware_ctf = vega12_thermal_disable_alert,
2931 : #if 0
2932 : .set_power_profile_state = vega12_set_power_profile_state,
2933 : .get_sclk_od = vega12_get_sclk_od,
2934 : .set_sclk_od = vega12_set_sclk_od,
2935 : .get_mclk_od = vega12_get_mclk_od,
2936 : .set_mclk_od = vega12_set_mclk_od,
2937 : #endif
2938 : .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2939 : .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2940 : .register_irq_handlers = smu9_register_irq_handlers,
2941 : .start_thermal_controller = vega12_start_thermal_controller,
2942 : .powergate_gfx = vega12_gfx_off_control,
2943 : .get_performance_level = vega12_get_performance_level,
2944 : .get_asic_baco_capability = smu9_baco_get_capability,
2945 : .get_asic_baco_state = smu9_baco_get_state,
2946 : .set_asic_baco_state = vega12_baco_set_state,
2947 : .get_ppfeature_status = vega12_get_ppfeature_status,
2948 : .set_ppfeature_status = vega12_set_ppfeature_status,
2949 : .set_mp1_state = vega12_set_mp1_state,
2950 : .get_gpu_metrics = vega12_get_gpu_metrics,
2951 : };
2952 :
2953 0 : int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
2954 : {
2955 0 : hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
2956 0 : hwmgr->pptable_func = &vega12_pptable_funcs;
2957 :
2958 0 : return 0;
2959 : }
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