Line data Source code
1 : /*
2 : * Copyright 2018 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include <linux/module.h>
24 : #include <linux/slab.h>
25 : #include <linux/fb.h>
26 :
27 : #include "smu11_driver_if.h"
28 : #include "vega20_processpptables.h"
29 : #include "ppatomfwctrl.h"
30 : #include "atomfirmware.h"
31 : #include "pp_debug.h"
32 : #include "cgs_common.h"
33 : #include "vega20_pptable.h"
34 :
35 : #define VEGA20_FAN_TARGET_TEMPERATURE_OVERRIDE 105
36 :
37 : static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
38 : enum phm_platform_caps cap)
39 : {
40 0 : if (enable)
41 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
42 : else
43 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
44 : }
45 :
46 0 : static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
47 : {
48 0 : int index = GetIndexIntoMasterDataTable(powerplayinfo);
49 :
50 : u16 size;
51 : u8 frev, crev;
52 0 : const void *table_address = hwmgr->soft_pp_table;
53 :
54 0 : if (!table_address) {
55 0 : table_address = (ATOM_Vega20_POWERPLAYTABLE *)
56 0 : smu_atom_get_data_table(hwmgr->adev, index,
57 : &size, &frev, &crev);
58 :
59 0 : hwmgr->soft_pp_table = table_address;
60 0 : hwmgr->soft_pp_table_size = size;
61 : }
62 :
63 0 : return table_address;
64 : }
65 :
66 : #if 0
67 : static void dump_pptable(PPTable_t *pptable)
68 : {
69 : int i;
70 :
71 : pr_info("Version = 0x%08x\n", pptable->Version);
72 :
73 : pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
74 : pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
75 :
76 : pr_info("SocketPowerLimitAc0 = %d\n", pptable->SocketPowerLimitAc0);
77 : pr_info("SocketPowerLimitAc0Tau = %d\n", pptable->SocketPowerLimitAc0Tau);
78 : pr_info("SocketPowerLimitAc1 = %d\n", pptable->SocketPowerLimitAc1);
79 : pr_info("SocketPowerLimitAc1Tau = %d\n", pptable->SocketPowerLimitAc1Tau);
80 : pr_info("SocketPowerLimitAc2 = %d\n", pptable->SocketPowerLimitAc2);
81 : pr_info("SocketPowerLimitAc2Tau = %d\n", pptable->SocketPowerLimitAc2Tau);
82 : pr_info("SocketPowerLimitAc3 = %d\n", pptable->SocketPowerLimitAc3);
83 : pr_info("SocketPowerLimitAc3Tau = %d\n", pptable->SocketPowerLimitAc3Tau);
84 : pr_info("SocketPowerLimitDc = %d\n", pptable->SocketPowerLimitDc);
85 : pr_info("SocketPowerLimitDcTau = %d\n", pptable->SocketPowerLimitDcTau);
86 : pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
87 : pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
88 : pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
89 : pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
90 :
91 : pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
92 : pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
93 : pr_info("ThbmLimit = %d\n", pptable->ThbmLimit);
94 : pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
95 : pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
96 : pr_info("Tliquid1Limit = %d\n", pptable->Tliquid1Limit);
97 : pr_info("Tliquid2Limit = %d\n", pptable->Tliquid2Limit);
98 : pr_info("TplxLimit = %d\n", pptable->TplxLimit);
99 : pr_info("FitLimit = %d\n", pptable->FitLimit);
100 :
101 : pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
102 : pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
103 :
104 : pr_info("MemoryOnPackage = 0x%02x\n", pptable->MemoryOnPackage);
105 : pr_info("padding8_limits = 0x%02x\n", pptable->padding8_limits);
106 : pr_info("Tvr_SocLimit = %d\n", pptable->Tvr_SocLimit);
107 :
108 : pr_info("UlvVoltageOffsetSoc = %d\n", pptable->UlvVoltageOffsetSoc);
109 : pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
110 :
111 : pr_info("UlvSmnclkDid = %d\n", pptable->UlvSmnclkDid);
112 : pr_info("UlvMp1clkDid = %d\n", pptable->UlvMp1clkDid);
113 : pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
114 : pr_info("Padding234 = 0x%02x\n", pptable->Padding234);
115 :
116 : pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
117 : pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
118 : pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
119 : pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
120 :
121 : pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
122 : pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
123 :
124 : pr_info("[PPCLK_GFXCLK]\n"
125 : " .VoltageMode = 0x%02x\n"
126 : " .SnapToDiscrete = 0x%02x\n"
127 : " .NumDiscreteLevels = 0x%02x\n"
128 : " .padding = 0x%02x\n"
129 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
130 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
131 : pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
132 : pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
133 : pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
134 : pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
135 : pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
136 : pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
137 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
138 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
139 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c);
140 :
141 : pr_info("[PPCLK_VCLK]\n"
142 : " .VoltageMode = 0x%02x\n"
143 : " .SnapToDiscrete = 0x%02x\n"
144 : " .NumDiscreteLevels = 0x%02x\n"
145 : " .padding = 0x%02x\n"
146 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
147 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
148 : pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
149 : pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
150 : pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
151 : pptable->DpmDescriptor[PPCLK_VCLK].padding,
152 : pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
153 : pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
154 : pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
155 : pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
156 : pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c);
157 :
158 : pr_info("[PPCLK_DCLK]\n"
159 : " .VoltageMode = 0x%02x\n"
160 : " .SnapToDiscrete = 0x%02x\n"
161 : " .NumDiscreteLevels = 0x%02x\n"
162 : " .padding = 0x%02x\n"
163 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
164 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
165 : pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
166 : pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
167 : pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
168 : pptable->DpmDescriptor[PPCLK_DCLK].padding,
169 : pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
170 : pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
171 : pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
172 : pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
173 : pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c);
174 :
175 : pr_info("[PPCLK_ECLK]\n"
176 : " .VoltageMode = 0x%02x\n"
177 : " .SnapToDiscrete = 0x%02x\n"
178 : " .NumDiscreteLevels = 0x%02x\n"
179 : " .padding = 0x%02x\n"
180 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
181 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
182 : pptable->DpmDescriptor[PPCLK_ECLK].VoltageMode,
183 : pptable->DpmDescriptor[PPCLK_ECLK].SnapToDiscrete,
184 : pptable->DpmDescriptor[PPCLK_ECLK].NumDiscreteLevels,
185 : pptable->DpmDescriptor[PPCLK_ECLK].padding,
186 : pptable->DpmDescriptor[PPCLK_ECLK].ConversionToAvfsClk.m,
187 : pptable->DpmDescriptor[PPCLK_ECLK].ConversionToAvfsClk.b,
188 : pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.a,
189 : pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.b,
190 : pptable->DpmDescriptor[PPCLK_ECLK].SsCurve.c);
191 :
192 : pr_info("[PPCLK_SOCCLK]\n"
193 : " .VoltageMode = 0x%02x\n"
194 : " .SnapToDiscrete = 0x%02x\n"
195 : " .NumDiscreteLevels = 0x%02x\n"
196 : " .padding = 0x%02x\n"
197 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
198 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
199 : pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
200 : pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
201 : pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
202 : pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
203 : pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
204 : pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
205 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
206 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
207 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c);
208 :
209 : pr_info("[PPCLK_UCLK]\n"
210 : " .VoltageMode = 0x%02x\n"
211 : " .SnapToDiscrete = 0x%02x\n"
212 : " .NumDiscreteLevels = 0x%02x\n"
213 : " .padding = 0x%02x\n"
214 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
215 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
216 : pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
217 : pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
218 : pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
219 : pptable->DpmDescriptor[PPCLK_UCLK].padding,
220 : pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
221 : pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
222 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
223 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
224 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c);
225 :
226 : pr_info("[PPCLK_DCEFCLK]\n"
227 : " .VoltageMode = 0x%02x\n"
228 : " .SnapToDiscrete = 0x%02x\n"
229 : " .NumDiscreteLevels = 0x%02x\n"
230 : " .padding = 0x%02x\n"
231 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
232 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
233 : pptable->DpmDescriptor[PPCLK_DCEFCLK].VoltageMode,
234 : pptable->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete,
235 : pptable->DpmDescriptor[PPCLK_DCEFCLK].NumDiscreteLevels,
236 : pptable->DpmDescriptor[PPCLK_DCEFCLK].padding,
237 : pptable->DpmDescriptor[PPCLK_DCEFCLK].ConversionToAvfsClk.m,
238 : pptable->DpmDescriptor[PPCLK_DCEFCLK].ConversionToAvfsClk.b,
239 : pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.a,
240 : pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.b,
241 : pptable->DpmDescriptor[PPCLK_DCEFCLK].SsCurve.c);
242 :
243 : pr_info("[PPCLK_DISPCLK]\n"
244 : " .VoltageMode = 0x%02x\n"
245 : " .SnapToDiscrete = 0x%02x\n"
246 : " .NumDiscreteLevels = 0x%02x\n"
247 : " .padding = 0x%02x\n"
248 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
249 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
250 : pptable->DpmDescriptor[PPCLK_DISPCLK].VoltageMode,
251 : pptable->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete,
252 : pptable->DpmDescriptor[PPCLK_DISPCLK].NumDiscreteLevels,
253 : pptable->DpmDescriptor[PPCLK_DISPCLK].padding,
254 : pptable->DpmDescriptor[PPCLK_DISPCLK].ConversionToAvfsClk.m,
255 : pptable->DpmDescriptor[PPCLK_DISPCLK].ConversionToAvfsClk.b,
256 : pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.a,
257 : pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.b,
258 : pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.c);
259 :
260 : pr_info("[PPCLK_PIXCLK]\n"
261 : " .VoltageMode = 0x%02x\n"
262 : " .SnapToDiscrete = 0x%02x\n"
263 : " .NumDiscreteLevels = 0x%02x\n"
264 : " .padding = 0x%02x\n"
265 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
266 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
267 : pptable->DpmDescriptor[PPCLK_PIXCLK].VoltageMode,
268 : pptable->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete,
269 : pptable->DpmDescriptor[PPCLK_PIXCLK].NumDiscreteLevels,
270 : pptable->DpmDescriptor[PPCLK_PIXCLK].padding,
271 : pptable->DpmDescriptor[PPCLK_PIXCLK].ConversionToAvfsClk.m,
272 : pptable->DpmDescriptor[PPCLK_PIXCLK].ConversionToAvfsClk.b,
273 : pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.a,
274 : pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.b,
275 : pptable->DpmDescriptor[PPCLK_PIXCLK].SsCurve.c);
276 :
277 : pr_info("[PPCLK_PHYCLK]\n"
278 : " .VoltageMode = 0x%02x\n"
279 : " .SnapToDiscrete = 0x%02x\n"
280 : " .NumDiscreteLevels = 0x%02x\n"
281 : " .padding = 0x%02x\n"
282 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
283 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
284 : pptable->DpmDescriptor[PPCLK_PHYCLK].VoltageMode,
285 : pptable->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete,
286 : pptable->DpmDescriptor[PPCLK_PHYCLK].NumDiscreteLevels,
287 : pptable->DpmDescriptor[PPCLK_PHYCLK].padding,
288 : pptable->DpmDescriptor[PPCLK_PHYCLK].ConversionToAvfsClk.m,
289 : pptable->DpmDescriptor[PPCLK_PHYCLK].ConversionToAvfsClk.b,
290 : pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.a,
291 : pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.b,
292 : pptable->DpmDescriptor[PPCLK_PHYCLK].SsCurve.c);
293 :
294 : pr_info("[PPCLK_FCLK]\n"
295 : " .VoltageMode = 0x%02x\n"
296 : " .SnapToDiscrete = 0x%02x\n"
297 : " .NumDiscreteLevels = 0x%02x\n"
298 : " .padding = 0x%02x\n"
299 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
300 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n",
301 : pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
302 : pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
303 : pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
304 : pptable->DpmDescriptor[PPCLK_FCLK].padding,
305 : pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
306 : pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
307 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
308 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
309 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c);
310 :
311 :
312 : pr_info("FreqTableGfx\n");
313 : for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
314 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
315 :
316 : pr_info("FreqTableVclk\n");
317 : for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
318 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
319 :
320 : pr_info("FreqTableDclk\n");
321 : for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
322 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
323 :
324 : pr_info("FreqTableEclk\n");
325 : for (i = 0; i < NUM_ECLK_DPM_LEVELS; i++)
326 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableEclk[i]);
327 :
328 : pr_info("FreqTableSocclk\n");
329 : for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
330 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
331 :
332 : pr_info("FreqTableUclk\n");
333 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
334 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
335 :
336 : pr_info("FreqTableFclk\n");
337 : for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
338 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
339 :
340 : pr_info("FreqTableDcefclk\n");
341 : for (i = 0; i < NUM_DCEFCLK_DPM_LEVELS; i++)
342 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDcefclk[i]);
343 :
344 : pr_info("FreqTableDispclk\n");
345 : for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)
346 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDispclk[i]);
347 :
348 : pr_info("FreqTablePixclk\n");
349 : for (i = 0; i < NUM_PIXCLK_DPM_LEVELS; i++)
350 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTablePixclk[i]);
351 :
352 : pr_info("FreqTablePhyclk\n");
353 : for (i = 0; i < NUM_PHYCLK_DPM_LEVELS; i++)
354 : pr_info(" .[%02d] = %d\n", i, pptable->FreqTablePhyclk[i]);
355 :
356 : pr_info("DcModeMaxFreq[PPCLK_GFXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
357 : pr_info("DcModeMaxFreq[PPCLK_VCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_VCLK]);
358 : pr_info("DcModeMaxFreq[PPCLK_DCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DCLK]);
359 : pr_info("DcModeMaxFreq[PPCLK_ECLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_ECLK]);
360 : pr_info("DcModeMaxFreq[PPCLK_SOCCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
361 : pr_info("DcModeMaxFreq[PPCLK_UCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
362 : pr_info("DcModeMaxFreq[PPCLK_DCEFCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DCEFCLK]);
363 : pr_info("DcModeMaxFreq[PPCLK_DISPCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DISPCLK]);
364 : pr_info("DcModeMaxFreq[PPCLK_PIXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_PIXCLK]);
365 : pr_info("DcModeMaxFreq[PPCLK_PHYCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_PHYCLK]);
366 : pr_info("DcModeMaxFreq[PPCLK_FCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
367 : pr_info("Padding8_Clks = %d\n", pptable->Padding8_Clks);
368 :
369 : pr_info("Mp0clkFreq\n");
370 : for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
371 : pr_info(" .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
372 :
373 : pr_info("Mp0DpmVoltage\n");
374 : for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
375 : pr_info(" .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
376 :
377 : pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
378 : pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
379 : pr_info("CksEnableFreq = 0x%x\n", pptable->CksEnableFreq);
380 : pr_info("Padding789 = 0x%x\n", pptable->Padding789);
381 : pr_info("CksVoltageOffset[a = 0x%08x b = 0x%08x c = 0x%08x]\n",
382 : pptable->CksVoltageOffset.a,
383 : pptable->CksVoltageOffset.b,
384 : pptable->CksVoltageOffset.c);
385 : pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
386 : pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
387 : pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
388 : pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
389 : pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
390 : pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
391 : pr_info("Padding456 = 0x%x\n", pptable->Padding456);
392 :
393 : pr_info("LowestUclkReservedForUlv = %d\n", pptable->LowestUclkReservedForUlv);
394 : pr_info("Padding8_Uclk[0] = 0x%x\n", pptable->Padding8_Uclk[0]);
395 : pr_info("Padding8_Uclk[1] = 0x%x\n", pptable->Padding8_Uclk[1]);
396 : pr_info("Padding8_Uclk[2] = 0x%x\n", pptable->Padding8_Uclk[2]);
397 :
398 : pr_info("PcieGenSpeed\n");
399 : for (i = 0; i < NUM_LINK_LEVELS; i++)
400 : pr_info(" .[%d] = %d\n", i, pptable->PcieGenSpeed[i]);
401 :
402 : pr_info("PcieLaneCount\n");
403 : for (i = 0; i < NUM_LINK_LEVELS; i++)
404 : pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]);
405 :
406 : pr_info("LclkFreq\n");
407 : for (i = 0; i < NUM_LINK_LEVELS; i++)
408 : pr_info(" .[%d] = %d\n", i, pptable->LclkFreq[i]);
409 :
410 : pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
411 : pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
412 : pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
413 : pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
414 :
415 : pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
416 : pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
417 :
418 : pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
419 : pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
420 : pr_info("FanGainLiquid = %d\n", pptable->FanGainLiquid);
421 : pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
422 : pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
423 : pr_info("FanGainPlx = %d\n", pptable->FanGainPlx);
424 : pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
425 : pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
426 : pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
427 : pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
428 : pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
429 : pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
430 : pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
431 : pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
432 : pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
433 :
434 : pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
435 : pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
436 : pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
437 : pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
438 :
439 : pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
440 : pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
441 : pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
442 : pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
443 :
444 : pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
445 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
446 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
447 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
448 : pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
449 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
450 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
451 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
452 : pr_info("dBtcGbGfxCksOn{a = 0x%x b = 0x%x c = 0x%x}\n",
453 : pptable->dBtcGbGfxCksOn.a,
454 : pptable->dBtcGbGfxCksOn.b,
455 : pptable->dBtcGbGfxCksOn.c);
456 : pr_info("dBtcGbGfxCksOff{a = 0x%x b = 0x%x c = 0x%x}\n",
457 : pptable->dBtcGbGfxCksOff.a,
458 : pptable->dBtcGbGfxCksOff.b,
459 : pptable->dBtcGbGfxCksOff.c);
460 : pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
461 : pptable->dBtcGbGfxAfll.a,
462 : pptable->dBtcGbGfxAfll.b,
463 : pptable->dBtcGbGfxAfll.c);
464 : pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
465 : pptable->dBtcGbSoc.a,
466 : pptable->dBtcGbSoc.b,
467 : pptable->dBtcGbSoc.c);
468 : pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
469 : pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
470 : pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
471 : pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
472 : pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
473 : pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
474 :
475 : pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
476 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
477 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
478 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
479 : pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
480 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
481 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
482 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
483 :
484 : pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
485 : pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
486 :
487 : pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
488 : pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
489 : pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
490 : pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
491 :
492 : pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
493 : pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
494 : pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
495 : pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
496 :
497 : pr_info("XgmiLinkSpeed\n");
498 : for (i = 0; i < NUM_XGMI_LEVELS; i++)
499 : pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
500 : pr_info("XgmiLinkWidth\n");
501 : for (i = 0; i < NUM_XGMI_LEVELS; i++)
502 : pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
503 : pr_info("XgmiFclkFreq\n");
504 : for (i = 0; i < NUM_XGMI_LEVELS; i++)
505 : pr_info(" .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
506 : pr_info("XgmiUclkFreq\n");
507 : for (i = 0; i < NUM_XGMI_LEVELS; i++)
508 : pr_info(" .[%d] = %d\n", i, pptable->XgmiUclkFreq[i]);
509 : pr_info("XgmiSocclkFreq\n");
510 : for (i = 0; i < NUM_XGMI_LEVELS; i++)
511 : pr_info(" .[%d] = %d\n", i, pptable->XgmiSocclkFreq[i]);
512 : pr_info("XgmiSocVoltage\n");
513 : for (i = 0; i < NUM_XGMI_LEVELS; i++)
514 : pr_info(" .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
515 :
516 : pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
517 : pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
518 : pptable->ReservedEquation0.a,
519 : pptable->ReservedEquation0.b,
520 : pptable->ReservedEquation0.c);
521 : pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
522 : pptable->ReservedEquation1.a,
523 : pptable->ReservedEquation1.b,
524 : pptable->ReservedEquation1.c);
525 : pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
526 : pptable->ReservedEquation2.a,
527 : pptable->ReservedEquation2.b,
528 : pptable->ReservedEquation2.c);
529 : pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
530 : pptable->ReservedEquation3.a,
531 : pptable->ReservedEquation3.b,
532 : pptable->ReservedEquation3.c);
533 :
534 : pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
535 : pr_info("MinVoltageUlvSoc = %d\n", pptable->MinVoltageUlvSoc);
536 :
537 : pr_info("MGpuFanBoostLimitRpm = %d\n", pptable->MGpuFanBoostLimitRpm);
538 : pr_info("padding16_Fan = %d\n", pptable->padding16_Fan);
539 :
540 : pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0);
541 : pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0);
542 :
543 : pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
544 : pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
545 :
546 : for (i = 0; i < 11; i++)
547 : pr_info("Reserved[%d] = 0x%x\n", i, pptable->Reserved[i]);
548 :
549 : for (i = 0; i < 3; i++)
550 : pr_info("Padding32[%d] = 0x%x\n", i, pptable->Padding32[i]);
551 :
552 : pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
553 : pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
554 :
555 : pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
556 : pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
557 : pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
558 : pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
559 :
560 : pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
561 : pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
562 : pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
563 : pr_info("Padding8_V = 0x%x\n", pptable->Padding8_V);
564 :
565 : pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
566 : pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
567 : pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
568 :
569 : pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
570 : pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
571 : pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
572 :
573 : pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
574 : pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
575 : pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
576 :
577 : pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
578 : pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
579 : pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
580 :
581 : pr_info("AcDcGpio = %d\n", pptable->AcDcGpio);
582 : pr_info("AcDcPolarity = %d\n", pptable->AcDcPolarity);
583 : pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
584 : pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
585 :
586 : pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
587 : pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
588 : pr_info("Padding1 = 0x%x\n", pptable->Padding1);
589 : pr_info("Padding2 = 0x%x\n", pptable->Padding2);
590 :
591 : pr_info("LedPin0 = %d\n", pptable->LedPin0);
592 : pr_info("LedPin1 = %d\n", pptable->LedPin1);
593 : pr_info("LedPin2 = %d\n", pptable->LedPin2);
594 : pr_info("padding8_4 = 0x%x\n", pptable->padding8_4);
595 :
596 : pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
597 : pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
598 : pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
599 :
600 : pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
601 : pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
602 : pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
603 :
604 : pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
605 : pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
606 : pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
607 :
608 : pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
609 : pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
610 : pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
611 :
612 : for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
613 : pr_info("I2cControllers[%d]:\n", i);
614 : pr_info(" .Enabled = %d\n",
615 : pptable->I2cControllers[i].Enabled);
616 : pr_info(" .SlaveAddress = 0x%x\n",
617 : pptable->I2cControllers[i].SlaveAddress);
618 : pr_info(" .ControllerPort = %d\n",
619 : pptable->I2cControllers[i].ControllerPort);
620 : pr_info(" .ControllerName = %d\n",
621 : pptable->I2cControllers[i].ControllerName);
622 : pr_info(" .ThermalThrottler = %d\n",
623 : pptable->I2cControllers[i].ThermalThrottler);
624 : pr_info(" .I2cProtocol = %d\n",
625 : pptable->I2cControllers[i].I2cProtocol);
626 : pr_info(" .I2cSpeed = %d\n",
627 : pptable->I2cControllers[i].I2cSpeed);
628 : }
629 :
630 : for (i = 0; i < 10; i++)
631 : pr_info("BoardReserved[%d] = 0x%x\n", i, pptable->BoardReserved[i]);
632 :
633 : for (i = 0; i < 8; i++)
634 : pr_info("MmHubPadding[%d] = 0x%x\n", i, pptable->MmHubPadding[i]);
635 : }
636 : #endif
637 :
638 0 : static int check_powerplay_tables(
639 : struct pp_hwmgr *hwmgr,
640 : const ATOM_Vega20_POWERPLAYTABLE *powerplay_table)
641 : {
642 0 : PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
643 : ATOM_VEGA20_TABLE_REVISION_VEGA20),
644 : "Unsupported PPTable format!", return -1);
645 0 : PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
646 : "Invalid PowerPlay Table!", return -1);
647 :
648 0 : if (powerplay_table->smcPPTable.Version != PPTABLE_V20_SMU_VERSION) {
649 0 : pr_info("Unmatch PPTable version: "
650 : "pptable from VBIOS is V%d while driver supported is V%d!",
651 : powerplay_table->smcPPTable.Version,
652 : PPTABLE_V20_SMU_VERSION);
653 : return -EINVAL;
654 : }
655 :
656 : //dump_pptable(&powerplay_table->smcPPTable);
657 :
658 : return 0;
659 : }
660 :
661 0 : static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
662 : {
663 0 : set_hw_cap(
664 : hwmgr,
665 0 : 0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_POWERPLAY),
666 : PHM_PlatformCaps_PowerPlaySupport);
667 :
668 0 : set_hw_cap(
669 : hwmgr,
670 0 : 0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
671 : PHM_PlatformCaps_BiosPowerSourceControl);
672 :
673 0 : set_hw_cap(
674 : hwmgr,
675 0 : 0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_BACO),
676 : PHM_PlatformCaps_BACO);
677 :
678 0 : set_hw_cap(
679 : hwmgr,
680 0 : 0 != (powerplay_caps & ATOM_VEGA20_PP_PLATFORM_CAP_BAMACO),
681 : PHM_PlatformCaps_BAMACO);
682 :
683 0 : return 0;
684 : }
685 :
686 0 : static int copy_overdrive_feature_capabilities_array(
687 : struct pp_hwmgr *hwmgr,
688 : uint8_t **pptable_info_array,
689 : const uint8_t *pptable_array,
690 : uint8_t od_feature_count)
691 : {
692 : uint32_t array_size, i;
693 : uint8_t *table;
694 0 : bool od_supported = false;
695 :
696 0 : array_size = sizeof(uint8_t) * od_feature_count;
697 0 : table = kzalloc(array_size, GFP_KERNEL);
698 0 : if (NULL == table)
699 : return -ENOMEM;
700 :
701 0 : for (i = 0; i < od_feature_count; i++) {
702 0 : table[i] = le32_to_cpu(pptable_array[i]);
703 0 : if (table[i])
704 0 : od_supported = true;
705 : }
706 :
707 0 : *pptable_info_array = table;
708 :
709 0 : if (od_supported)
710 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
711 : PHM_PlatformCaps_ACOverdriveSupport);
712 :
713 : return 0;
714 : }
715 :
716 0 : static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
717 : {
718 : struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
719 0 : int index = GetIndexIntoMasterDataTable(smc_dpm_info);
720 : int i;
721 :
722 0 : PP_ASSERT_WITH_CODE(
723 : smc_dpm_table = smu_atom_get_data_table(hwmgr->adev, index, NULL, NULL, NULL),
724 : "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
725 : return -1);
726 :
727 0 : ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
728 0 : ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
729 :
730 0 : ppsmc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
731 0 : ppsmc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
732 0 : ppsmc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
733 0 : ppsmc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
734 :
735 0 : ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
736 0 : ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
737 0 : ppsmc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
738 :
739 0 : ppsmc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
740 0 : ppsmc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
741 0 : ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
742 :
743 0 : ppsmc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
744 0 : ppsmc_pptable->SocOffset = smc_dpm_table->socoffset;
745 0 : ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
746 :
747 0 : ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
748 0 : ppsmc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
749 0 : ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
750 :
751 0 : ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
752 0 : ppsmc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
753 0 : ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
754 :
755 0 : ppsmc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
756 0 : ppsmc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
757 0 : ppsmc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
758 0 : ppsmc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
759 :
760 0 : ppsmc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
761 0 : ppsmc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
762 0 : ppsmc_pptable->Padding1 = smc_dpm_table->padding1;
763 0 : ppsmc_pptable->Padding2 = smc_dpm_table->padding2;
764 :
765 0 : ppsmc_pptable->LedPin0 = smc_dpm_table->ledpin0;
766 0 : ppsmc_pptable->LedPin1 = smc_dpm_table->ledpin1;
767 0 : ppsmc_pptable->LedPin2 = smc_dpm_table->ledpin2;
768 :
769 0 : ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
770 0 : ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
771 0 : ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
772 :
773 0 : ppsmc_pptable->UclkSpreadEnabled = 0;
774 0 : ppsmc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
775 0 : ppsmc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
776 :
777 0 : ppsmc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
778 0 : ppsmc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
779 0 : ppsmc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
780 :
781 0 : ppsmc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
782 0 : ppsmc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
783 0 : ppsmc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
784 :
785 0 : for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
786 0 : ppsmc_pptable->I2cControllers[i].Enabled =
787 0 : smc_dpm_table->i2ccontrollers[i].enabled;
788 0 : ppsmc_pptable->I2cControllers[i].SlaveAddress =
789 0 : smc_dpm_table->i2ccontrollers[i].slaveaddress;
790 0 : ppsmc_pptable->I2cControllers[i].ControllerPort =
791 0 : smc_dpm_table->i2ccontrollers[i].controllerport;
792 0 : ppsmc_pptable->I2cControllers[i].ThermalThrottler =
793 0 : smc_dpm_table->i2ccontrollers[i].thermalthrottler;
794 0 : ppsmc_pptable->I2cControllers[i].I2cProtocol =
795 0 : smc_dpm_table->i2ccontrollers[i].i2cprotocol;
796 0 : ppsmc_pptable->I2cControllers[i].I2cSpeed =
797 0 : smc_dpm_table->i2ccontrollers[i].i2cspeed;
798 : }
799 :
800 : return 0;
801 : }
802 :
803 : static int override_powerplay_table_fantargettemperature(struct pp_hwmgr *hwmgr)
804 : {
805 0 : struct phm_ppt_v3_information *pptable_information =
806 : (struct phm_ppt_v3_information *)hwmgr->pptable;
807 0 : PPTable_t *ppsmc_pptable = (PPTable_t *)(pptable_information->smc_pptable);
808 :
809 0 : ppsmc_pptable->FanTargetTemperature = VEGA20_FAN_TARGET_TEMPERATURE_OVERRIDE;
810 :
811 : return 0;
812 : }
813 :
814 : #define VEGA20_ENGINECLOCK_HARDMAX 198000
815 0 : static int init_powerplay_table_information(
816 : struct pp_hwmgr *hwmgr,
817 : const ATOM_Vega20_POWERPLAYTABLE *powerplay_table)
818 : {
819 0 : struct phm_ppt_v3_information *pptable_information =
820 : (struct phm_ppt_v3_information *)hwmgr->pptable;
821 0 : uint32_t disable_power_control = 0;
822 : uint32_t od_feature_count, od_setting_count, power_saving_clock_count;
823 : int result;
824 :
825 0 : hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
826 0 : pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType;
827 0 : hwmgr->thermal_controller.fanInfo.ulMinRPM = 0;
828 0 : hwmgr->thermal_controller.fanInfo.ulMaxRPM = powerplay_table->smcPPTable.FanMaximumRpm;
829 :
830 0 : set_hw_cap(hwmgr,
831 0 : ATOM_VEGA20_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
832 : PHM_PlatformCaps_ThermalController);
833 :
834 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
835 :
836 0 : if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
837 0 : od_feature_count =
838 : (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
839 : ATOM_VEGA20_ODFEATURE_COUNT) ?
840 : ATOM_VEGA20_ODFEATURE_COUNT :
841 0 : le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
842 0 : od_setting_count =
843 : (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
844 : ATOM_VEGA20_ODSETTING_COUNT) ?
845 : ATOM_VEGA20_ODSETTING_COUNT :
846 0 : le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
847 :
848 0 : copy_overdrive_feature_capabilities_array(hwmgr,
849 : &pptable_information->od_feature_capabilities,
850 0 : powerplay_table->OverDrive8Table.ODFeatureCapabilities,
851 : od_feature_count);
852 0 : phm_copy_overdrive_settings_limits_array(hwmgr,
853 : &pptable_information->od_settings_max,
854 0 : powerplay_table->OverDrive8Table.ODSettingsMax,
855 : od_setting_count);
856 0 : phm_copy_overdrive_settings_limits_array(hwmgr,
857 : &pptable_information->od_settings_min,
858 0 : powerplay_table->OverDrive8Table.ODSettingsMin,
859 : od_setting_count);
860 : }
861 :
862 0 : pptable_information->us_small_power_limit1 = le16_to_cpu(powerplay_table->usSmallPowerLimit1);
863 0 : pptable_information->us_small_power_limit2 = le16_to_cpu(powerplay_table->usSmallPowerLimit2);
864 0 : pptable_information->us_boost_power_limit = le16_to_cpu(powerplay_table->usBoostPowerLimit);
865 0 : pptable_information->us_od_turbo_power_limit = le16_to_cpu(powerplay_table->usODTurboPowerLimit);
866 0 : pptable_information->us_od_powersave_power_limit = le16_to_cpu(powerplay_table->usODPowerSavePowerLimit);
867 :
868 0 : pptable_information->us_software_shutdown_temp = le16_to_cpu(powerplay_table->usSoftwareShutdownTemp);
869 :
870 0 : hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
871 :
872 0 : disable_power_control = 0;
873 0 : if (!disable_power_control && hwmgr->platform_descriptor.TDPODLimit)
874 : /* enable TDP overdrive (PowerControl) feature as well if supported */
875 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerControl);
876 :
877 0 : if (powerplay_table->PowerSavingClockTable.ucTableRevision == 1) {
878 0 : power_saving_clock_count =
879 0 : (le32_to_cpu(powerplay_table->PowerSavingClockTable.PowerSavingClockCount) >=
880 : ATOM_VEGA20_PPCLOCK_COUNT) ?
881 : ATOM_VEGA20_PPCLOCK_COUNT :
882 : le32_to_cpu(powerplay_table->PowerSavingClockTable.PowerSavingClockCount);
883 0 : phm_copy_clock_limits_array(hwmgr,
884 : &pptable_information->power_saving_clock_max,
885 0 : powerplay_table->PowerSavingClockTable.PowerSavingClockMax,
886 : power_saving_clock_count);
887 0 : phm_copy_clock_limits_array(hwmgr,
888 : &pptable_information->power_saving_clock_min,
889 0 : powerplay_table->PowerSavingClockTable.PowerSavingClockMin,
890 : power_saving_clock_count);
891 : }
892 :
893 0 : pptable_information->smc_pptable = kmemdup(&(powerplay_table->smcPPTable),
894 : sizeof(PPTable_t),
895 : GFP_KERNEL);
896 0 : if (pptable_information->smc_pptable == NULL)
897 : return -ENOMEM;
898 :
899 :
900 0 : result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
901 0 : if (result)
902 : return result;
903 :
904 0 : result = override_powerplay_table_fantargettemperature(hwmgr);
905 :
906 0 : return result;
907 : }
908 :
909 0 : static int vega20_pp_tables_initialize(struct pp_hwmgr *hwmgr)
910 : {
911 0 : int result = 0;
912 : const ATOM_Vega20_POWERPLAYTABLE *powerplay_table;
913 :
914 0 : hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
915 0 : PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
916 : "Failed to allocate hwmgr->pptable!", return -ENOMEM);
917 :
918 0 : powerplay_table = get_powerplay_table(hwmgr);
919 0 : PP_ASSERT_WITH_CODE((powerplay_table != NULL),
920 : "Missing PowerPlay Table!", return -1);
921 :
922 0 : result = check_powerplay_tables(hwmgr, powerplay_table);
923 0 : PP_ASSERT_WITH_CODE((result == 0),
924 : "check_powerplay_tables failed", return result);
925 :
926 0 : result = set_platform_caps(hwmgr,
927 0 : le32_to_cpu(powerplay_table->ulPlatformCaps));
928 0 : PP_ASSERT_WITH_CODE((result == 0),
929 : "set_platform_caps failed", return result);
930 :
931 0 : result = init_powerplay_table_information(hwmgr, powerplay_table);
932 0 : PP_ASSERT_WITH_CODE((result == 0),
933 : "init_powerplay_table_information failed", return result);
934 :
935 : return result;
936 : }
937 :
938 0 : static int vega20_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
939 : {
940 0 : struct phm_ppt_v3_information *pp_table_info =
941 : (struct phm_ppt_v3_information *)(hwmgr->pptable);
942 :
943 0 : kfree(pp_table_info->power_saving_clock_max);
944 0 : pp_table_info->power_saving_clock_max = NULL;
945 :
946 0 : kfree(pp_table_info->power_saving_clock_min);
947 0 : pp_table_info->power_saving_clock_min = NULL;
948 :
949 0 : kfree(pp_table_info->od_feature_capabilities);
950 0 : pp_table_info->od_feature_capabilities = NULL;
951 :
952 0 : kfree(pp_table_info->od_settings_max);
953 0 : pp_table_info->od_settings_max = NULL;
954 :
955 0 : kfree(pp_table_info->od_settings_min);
956 0 : pp_table_info->od_settings_min = NULL;
957 :
958 0 : kfree(pp_table_info->smc_pptable);
959 0 : pp_table_info->smc_pptable = NULL;
960 :
961 0 : kfree(hwmgr->pptable);
962 0 : hwmgr->pptable = NULL;
963 :
964 0 : return 0;
965 : }
966 :
967 : const struct pp_table_func vega20_pptable_funcs = {
968 : .pptable_init = vega20_pp_tables_initialize,
969 : .pptable_fini = vega20_pp_tables_uninitialize,
970 : };
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