Line data Source code
1 : /*
2 : * Copyright 2015 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <linux/pci.h>
25 :
26 : #include "pp_debug.h"
27 : #include "smumgr.h"
28 : #include "smu74.h"
29 : #include "smu_ucode_xfer_vi.h"
30 : #include "polaris10_smumgr.h"
31 : #include "smu74_discrete.h"
32 : #include "smu/smu_7_1_3_d.h"
33 : #include "smu/smu_7_1_3_sh_mask.h"
34 : #include "gmc/gmc_8_1_d.h"
35 : #include "gmc/gmc_8_1_sh_mask.h"
36 : #include "oss/oss_3_0_d.h"
37 : #include "gca/gfx_8_0_d.h"
38 : #include "bif/bif_5_0_d.h"
39 : #include "bif/bif_5_0_sh_mask.h"
40 : #include "ppatomctrl.h"
41 : #include "cgs_common.h"
42 : #include "smu7_ppsmc.h"
43 : #include "smu7_smumgr.h"
44 :
45 : #include "smu7_dyn_defaults.h"
46 :
47 : #include "smu7_hwmgr.h"
48 : #include "hardwaremanager.h"
49 : #include "atombios.h"
50 : #include "pppcielanes.h"
51 :
52 : #include "dce/dce_10_0_d.h"
53 : #include "dce/dce_10_0_sh_mask.h"
54 :
55 : #define POLARIS10_SMC_SIZE 0x20000
56 : #define POWERTUNE_DEFAULT_SET_MAX 1
57 : #define VDDC_VDDCI_DELTA 200
58 : #define MC_CG_ARB_FREQ_F1 0x0b
59 :
60 : static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
61 : /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
62 : * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
63 : { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
64 : { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
65 : { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
66 : };
67 :
68 : static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
69 : {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
70 : {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
71 : {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
72 : {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
73 : {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
74 : {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
75 : {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
76 : {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
77 :
78 : #define PPPOLARIS10_TARGETACTIVITY_DFLT 50
79 :
80 : static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
81 : /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
82 : /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
83 : { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
84 : { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
85 : { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
86 : { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
87 : { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
88 : { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
89 : { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
90 : { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
91 : };
92 :
93 : static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
94 : 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
95 :
96 0 : static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
97 : {
98 0 : int result = 0;
99 0 : struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
100 :
101 0 : if (0 != smu_data->avfs_btc_param) {
102 0 : if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param,
103 : NULL)) {
104 0 : pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
105 0 : result = -1;
106 : }
107 : }
108 0 : if (smu_data->avfs_btc_param > 1) {
109 : /* Soft-Reset to reset the engine before loading uCode */
110 : /* halt */
111 0 : cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
112 : /* reset everything */
113 0 : cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
114 0 : cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
115 : }
116 0 : return result;
117 : }
118 :
119 :
120 0 : static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
121 : {
122 : uint32_t vr_config;
123 : uint32_t dpm_table_start;
124 :
125 : uint16_t u16_boot_mvdd;
126 : uint32_t graphics_level_address, vr_config_address, graphics_level_size;
127 :
128 0 : graphics_level_size = sizeof(avfs_graphics_level_polaris10);
129 0 : u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
130 :
131 0 : PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
132 : SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
133 : &dpm_table_start, 0x40000),
134 : "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
135 : return -1);
136 :
137 : /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
138 0 : vr_config = 0x01000500; /* Real value:0x50001 */
139 :
140 0 : vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
141 :
142 0 : PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
143 : (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
144 : "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
145 : return -1);
146 :
147 0 : graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
148 :
149 0 : PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
150 : (uint8_t *)(&avfs_graphics_level_polaris10),
151 : graphics_level_size, 0x40000),
152 : "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
153 : return -1);
154 :
155 0 : graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
156 :
157 0 : PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
158 : (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
159 : "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
160 : return -1);
161 :
162 : /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
163 :
164 0 : graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
165 :
166 0 : PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
167 : (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
168 : "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
169 : return -1);
170 :
171 : return 0;
172 : }
173 :
174 :
175 0 : static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
176 : {
177 0 : struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
178 :
179 0 : if (!hwmgr->avfs_supported)
180 : return 0;
181 :
182 0 : PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
183 : "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
184 : return -EINVAL);
185 :
186 0 : if (smu_data->avfs_btc_param > 1) {
187 0 : pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
188 0 : PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
189 : "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
190 : return -EINVAL);
191 : }
192 :
193 0 : PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
194 : "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
195 : return -EINVAL);
196 :
197 : return 0;
198 : }
199 :
200 0 : static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
201 : {
202 0 : int result = 0;
203 :
204 : /* Wait for smc boot up */
205 : /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
206 :
207 : /* Assert reset */
208 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
209 : SMC_SYSCON_RESET_CNTL, rst_reg, 1);
210 :
211 0 : result = smu7_upload_smu_firmware_image(hwmgr);
212 0 : if (result != 0)
213 : return result;
214 :
215 : /* Clear status */
216 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
217 :
218 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
219 : SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
220 :
221 : /* De-assert reset */
222 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
223 : SMC_SYSCON_RESET_CNTL, rst_reg, 0);
224 :
225 :
226 0 : PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
227 :
228 :
229 : /* Call Test SMU message with 0x20000 offset to trigger SMU start */
230 0 : smu7_send_msg_to_smc_offset(hwmgr);
231 :
232 : /* Wait done bit to be set */
233 : /* Check pass/failed indicator */
234 :
235 0 : PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
236 :
237 0 : if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
238 : SMU_STATUS, SMU_PASS))
239 0 : PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
240 :
241 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
242 :
243 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
244 : SMC_SYSCON_RESET_CNTL, rst_reg, 1);
245 :
246 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
247 : SMC_SYSCON_RESET_CNTL, rst_reg, 0);
248 :
249 : /* Wait for firmware to initialize */
250 0 : PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
251 :
252 0 : return result;
253 : }
254 :
255 0 : static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
256 : {
257 0 : int result = 0;
258 :
259 : /* wait for smc boot up */
260 0 : PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
261 :
262 : /* Clear firmware interrupt enable flag */
263 : /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
264 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
265 : ixFIRMWARE_FLAGS, 0);
266 :
267 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
268 : SMC_SYSCON_RESET_CNTL,
269 : rst_reg, 1);
270 :
271 0 : result = smu7_upload_smu_firmware_image(hwmgr);
272 0 : if (result != 0)
273 : return result;
274 :
275 : /* Set smc instruct start point at 0x0 */
276 0 : smu7_program_jump_on_start(hwmgr);
277 :
278 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
279 : SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
280 :
281 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
282 : SMC_SYSCON_RESET_CNTL, rst_reg, 0);
283 :
284 : /* Wait for firmware to initialize */
285 :
286 0 : PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
287 : FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
288 :
289 0 : return result;
290 : }
291 :
292 0 : static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
293 : {
294 0 : int result = 0;
295 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
296 :
297 : /* Only start SMC if SMC RAM is not running */
298 0 : if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
299 0 : smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
300 0 : smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
301 :
302 : /* Check if SMU is running in protected mode */
303 0 : if (smu_data->protected_mode == 0)
304 0 : result = polaris10_start_smu_in_non_protection_mode(hwmgr);
305 : else
306 0 : result = polaris10_start_smu_in_protection_mode(hwmgr);
307 :
308 0 : if (result != 0)
309 0 : PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
310 :
311 0 : polaris10_avfs_event_mgr(hwmgr);
312 : }
313 :
314 : /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
315 0 : smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
316 : &(smu_data->smu7_data.soft_regs_start), 0x40000);
317 :
318 0 : result = smu7_request_smu_load_fw(hwmgr);
319 :
320 0 : return result;
321 : }
322 :
323 0 : static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
324 : {
325 : uint32_t efuse;
326 :
327 0 : efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
328 0 : efuse &= 0x00000001;
329 0 : if (efuse)
330 : return true;
331 :
332 0 : return false;
333 : }
334 :
335 0 : static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
336 : {
337 : struct polaris10_smumgr *smu_data;
338 :
339 0 : smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
340 0 : if (smu_data == NULL)
341 : return -ENOMEM;
342 :
343 0 : hwmgr->smu_backend = smu_data;
344 :
345 0 : if (smu7_init(hwmgr)) {
346 0 : kfree(smu_data);
347 0 : return -EINVAL;
348 : }
349 :
350 : return 0;
351 : }
352 :
353 0 : static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
354 : struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
355 : uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
356 : {
357 : uint32_t i;
358 : uint16_t vddci;
359 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
360 :
361 0 : *voltage = *mvdd = 0;
362 :
363 : /* clock - voltage dependency table is empty table */
364 0 : if (dep_table->count == 0)
365 : return -EINVAL;
366 :
367 0 : for (i = 0; i < dep_table->count; i++) {
368 : /* find first sclk bigger than request */
369 0 : if (dep_table->entries[i].clk >= clock) {
370 0 : *voltage |= (dep_table->entries[i].vddc *
371 0 : VOLTAGE_SCALE) << VDDC_SHIFT;
372 0 : if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
373 0 : *voltage |= (data->vbios_boot_state.vddci_bootup_value *
374 0 : VOLTAGE_SCALE) << VDDCI_SHIFT;
375 0 : else if (dep_table->entries[i].vddci)
376 0 : *voltage |= (dep_table->entries[i].vddci *
377 0 : VOLTAGE_SCALE) << VDDCI_SHIFT;
378 : else {
379 0 : vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
380 0 : (dep_table->entries[i].vddc -
381 : (uint16_t)VDDC_VDDCI_DELTA));
382 0 : *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
383 : }
384 :
385 0 : if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
386 0 : *mvdd = data->vbios_boot_state.mvdd_bootup_value *
387 : VOLTAGE_SCALE;
388 0 : else if (dep_table->entries[i].mvdd)
389 0 : *mvdd = (uint32_t) dep_table->entries[i].mvdd *
390 : VOLTAGE_SCALE;
391 :
392 0 : *voltage |= 1 << PHASES_SHIFT;
393 : return 0;
394 : }
395 : }
396 :
397 : /* sclk is bigger than max sclk in the dependence table */
398 0 : *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
399 :
400 0 : if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
401 0 : *voltage |= (data->vbios_boot_state.vddci_bootup_value *
402 0 : VOLTAGE_SCALE) << VDDCI_SHIFT;
403 0 : else if (dep_table->entries[i-1].vddci) {
404 0 : *voltage |= (dep_table->entries[i - 1].vddci * VOLTAGE_SCALE) << VDDC_SHIFT;
405 : } else {
406 0 : vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
407 0 : (dep_table->entries[i].vddc -
408 : (uint16_t)VDDC_VDDCI_DELTA));
409 0 : *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
410 : }
411 :
412 0 : if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
413 0 : *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
414 0 : else if (dep_table->entries[i].mvdd)
415 0 : *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
416 :
417 : return 0;
418 : }
419 :
420 : static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
421 : {
422 : uint32_t tmp;
423 0 : tmp = raw_setting * 4096 / 100;
424 0 : return (uint16_t)tmp;
425 : }
426 :
427 0 : static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
428 : {
429 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
430 :
431 0 : const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
432 0 : SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
433 0 : struct phm_ppt_v1_information *table_info =
434 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
435 0 : struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
436 0 : struct pp_advance_fan_control_parameters *fan_table =
437 : &hwmgr->thermal_controller.advanceFanControlParameters;
438 : int i, j, k;
439 : const uint16_t *pdef1;
440 : const uint16_t *pdef2;
441 :
442 0 : table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
443 0 : table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
444 :
445 0 : PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
446 : "Target Operating Temp is out of Range!",
447 : );
448 :
449 0 : table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
450 : cac_dtp_table->usTargetOperatingTemp * 256);
451 0 : table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
452 : cac_dtp_table->usTemperatureLimitHotspot * 256);
453 0 : table->FanGainEdge = PP_HOST_TO_SMC_US(
454 : scale_fan_gain_settings(fan_table->usFanGainEdge));
455 0 : table->FanGainHotspot = PP_HOST_TO_SMC_US(
456 : scale_fan_gain_settings(fan_table->usFanGainHotspot));
457 :
458 0 : pdef1 = defaults->BAPMTI_R;
459 0 : pdef2 = defaults->BAPMTI_RC;
460 :
461 0 : for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
462 0 : for (j = 0; j < SMU74_DTE_SOURCES; j++) {
463 0 : for (k = 0; k < SMU74_DTE_SINKS; k++) {
464 0 : table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
465 0 : table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
466 0 : pdef1++;
467 0 : pdef2++;
468 : }
469 : }
470 : }
471 :
472 0 : return 0;
473 : }
474 :
475 : static void polaris10_populate_zero_rpm_parameters(struct pp_hwmgr *hwmgr)
476 : {
477 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
478 0 : SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
479 0 : uint16_t fan_stop_temp =
480 0 : ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStopTemperature) << 8;
481 0 : uint16_t fan_start_temp =
482 0 : ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStartTemperature) << 8;
483 :
484 0 : if (hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM) {
485 0 : table->FanStartTemperature = PP_HOST_TO_SMC_US(fan_start_temp);
486 0 : table->FanStopTemperature = PP_HOST_TO_SMC_US(fan_stop_temp);
487 : }
488 : }
489 :
490 : static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
491 : {
492 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
493 0 : const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
494 :
495 0 : smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
496 0 : smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
497 0 : smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
498 0 : smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
499 :
500 : return 0;
501 : }
502 :
503 : static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
504 : {
505 : uint16_t tdc_limit;
506 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
507 0 : struct phm_ppt_v1_information *table_info =
508 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
509 0 : const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
510 :
511 0 : tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
512 0 : smu_data->power_tune_table.TDC_VDDC_PkgLimit =
513 0 : CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
514 0 : smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
515 0 : defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
516 0 : smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
517 :
518 : return 0;
519 : }
520 :
521 0 : static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
522 : {
523 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
524 0 : const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
525 : uint32_t temp;
526 :
527 0 : if (smu7_read_smc_sram_dword(hwmgr,
528 : fuse_table_offset +
529 : offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
530 : (uint32_t *)&temp, SMC_RAM_END))
531 0 : PP_ASSERT_WITH_CODE(false,
532 : "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
533 : return -EINVAL);
534 : else {
535 0 : smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
536 0 : smu_data->power_tune_table.LPMLTemperatureMin =
537 0 : (uint8_t)((temp >> 16) & 0xff);
538 0 : smu_data->power_tune_table.LPMLTemperatureMax =
539 0 : (uint8_t)((temp >> 8) & 0xff);
540 0 : smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
541 : }
542 0 : return 0;
543 : }
544 :
545 : static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
546 : {
547 : int i;
548 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
549 :
550 : /* Currently not used. Set all to zero. */
551 0 : for (i = 0; i < 16; i++)
552 0 : smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
553 :
554 : return 0;
555 : }
556 :
557 : static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
558 : {
559 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
560 :
561 : /* TO DO move to hwmgr */
562 0 : if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
563 0 : || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
564 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
565 0 : hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
566 :
567 0 : smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
568 : hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
569 : return 0;
570 : }
571 :
572 : static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
573 : {
574 : int i;
575 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
576 :
577 : /* Currently not used. Set all to zero. */
578 0 : for (i = 0; i < 16; i++)
579 0 : smu_data->power_tune_table.GnbLPML[i] = 0;
580 :
581 : return 0;
582 : }
583 :
584 : static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
585 : {
586 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
587 0 : struct phm_ppt_v1_information *table_info =
588 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
589 0 : uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
590 0 : uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
591 0 : struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
592 :
593 0 : hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
594 0 : lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
595 :
596 0 : smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
597 0 : CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
598 0 : smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
599 0 : CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
600 :
601 : return 0;
602 : }
603 :
604 0 : static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
605 : {
606 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
607 : uint32_t pm_fuse_table_offset;
608 :
609 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
610 : PHM_PlatformCaps_PowerContainment)) {
611 0 : if (smu7_read_smc_sram_dword(hwmgr,
612 : SMU7_FIRMWARE_HEADER_LOCATION +
613 : offsetof(SMU74_Firmware_Header, PmFuseTable),
614 : &pm_fuse_table_offset, SMC_RAM_END))
615 0 : PP_ASSERT_WITH_CODE(false,
616 : "Attempt to get pm_fuse_table_offset Failed!",
617 : return -EINVAL);
618 :
619 0 : if (polaris10_populate_svi_load_line(hwmgr))
620 : PP_ASSERT_WITH_CODE(false,
621 : "Attempt to populate SviLoadLine Failed!",
622 : return -EINVAL);
623 :
624 0 : if (polaris10_populate_tdc_limit(hwmgr))
625 : PP_ASSERT_WITH_CODE(false,
626 : "Attempt to populate TDCLimit Failed!", return -EINVAL);
627 :
628 0 : if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
629 0 : PP_ASSERT_WITH_CODE(false,
630 : "Attempt to populate TdcWaterfallCtl, "
631 : "LPMLTemperature Min and Max Failed!",
632 : return -EINVAL);
633 :
634 0 : if (0 != polaris10_populate_temperature_scaler(hwmgr))
635 : PP_ASSERT_WITH_CODE(false,
636 : "Attempt to populate LPMLTemperatureScaler Failed!",
637 : return -EINVAL);
638 :
639 0 : if (polaris10_populate_fuzzy_fan(hwmgr))
640 : PP_ASSERT_WITH_CODE(false,
641 : "Attempt to populate Fuzzy Fan Control parameters Failed!",
642 : return -EINVAL);
643 :
644 0 : if (polaris10_populate_gnb_lpml(hwmgr))
645 : PP_ASSERT_WITH_CODE(false,
646 : "Attempt to populate GnbLPML Failed!",
647 : return -EINVAL);
648 :
649 0 : if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
650 : PP_ASSERT_WITH_CODE(false,
651 : "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
652 : "Sidd Failed!", return -EINVAL);
653 :
654 0 : if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
655 0 : (uint8_t *)&smu_data->power_tune_table,
656 : (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
657 0 : PP_ASSERT_WITH_CODE(false,
658 : "Attempt to download PmFuseTable Failed!",
659 : return -EINVAL);
660 : }
661 : return 0;
662 : }
663 :
664 0 : static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
665 : SMU74_Discrete_DpmTable *table)
666 : {
667 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
668 : uint32_t count, level;
669 :
670 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
671 0 : count = data->mvdd_voltage_table.count;
672 0 : if (count > SMU_MAX_SMIO_LEVELS)
673 0 : count = SMU_MAX_SMIO_LEVELS;
674 0 : for (level = 0; level < count; level++) {
675 0 : table->SmioTable2.Pattern[level].Voltage =
676 0 : PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
677 : /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
678 0 : table->SmioTable2.Pattern[level].Smio =
679 0 : (uint8_t) level;
680 0 : table->Smio[level] |=
681 0 : data->mvdd_voltage_table.entries[level].smio_low;
682 : }
683 0 : table->SmioMask2 = data->mvdd_voltage_table.mask_low;
684 :
685 0 : table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
686 : }
687 :
688 0 : return 0;
689 : }
690 :
691 0 : static int polaris10_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
692 : struct SMU74_Discrete_DpmTable *table)
693 : {
694 : uint32_t count, level;
695 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
696 :
697 0 : count = data->vddc_voltage_table.count;
698 :
699 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
700 0 : if (count > SMU_MAX_SMIO_LEVELS)
701 0 : count = SMU_MAX_SMIO_LEVELS;
702 0 : for (level = 0; level < count; ++level) {
703 0 : table->SmioTable1.Pattern[level].Voltage =
704 0 : PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[level].value * VOLTAGE_SCALE);
705 0 : table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
706 :
707 0 : table->Smio[level] |= data->vddc_voltage_table.entries[level].smio_low;
708 : }
709 :
710 0 : table->SmioMask1 = data->vddc_voltage_table.mask_low;
711 : }
712 :
713 0 : return 0;
714 : }
715 :
716 0 : static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
717 : struct SMU74_Discrete_DpmTable *table)
718 : {
719 : uint32_t count, level;
720 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
721 :
722 0 : count = data->vddci_voltage_table.count;
723 :
724 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
725 0 : if (count > SMU_MAX_SMIO_LEVELS)
726 0 : count = SMU_MAX_SMIO_LEVELS;
727 0 : for (level = 0; level < count; ++level) {
728 0 : table->SmioTable1.Pattern[level].Voltage =
729 0 : PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
730 0 : table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
731 :
732 0 : table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
733 : }
734 :
735 0 : table->SmioMask1 = data->vddci_voltage_table.mask_low;
736 : }
737 :
738 0 : return 0;
739 : }
740 :
741 0 : static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
742 : struct SMU74_Discrete_DpmTable *table)
743 : {
744 : uint32_t count;
745 : uint8_t index;
746 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
747 0 : struct phm_ppt_v1_information *table_info =
748 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
749 0 : struct phm_ppt_v1_voltage_lookup_table *lookup_table =
750 : table_info->vddc_lookup_table;
751 : /* tables is already swapped, so in order to use the value from it,
752 : * we need to swap it back.
753 : * We are populating vddc CAC data to BapmVddc table
754 : * in split and merged mode
755 : */
756 0 : for (count = 0; count < lookup_table->count; count++) {
757 0 : index = phm_get_voltage_index(lookup_table,
758 0 : data->vddc_voltage_table.entries[count].value);
759 0 : table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
760 0 : table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
761 0 : table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
762 : }
763 :
764 0 : return 0;
765 : }
766 :
767 0 : static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
768 : struct SMU74_Discrete_DpmTable *table)
769 : {
770 0 : polaris10_populate_smc_vddc_table(hwmgr, table);
771 0 : polaris10_populate_smc_vddci_table(hwmgr, table);
772 0 : polaris10_populate_smc_mvdd_table(hwmgr, table);
773 0 : polaris10_populate_cac_table(hwmgr, table);
774 :
775 0 : return 0;
776 : }
777 :
778 0 : static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
779 : struct SMU74_Discrete_Ulv *state)
780 : {
781 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
782 0 : struct phm_ppt_v1_information *table_info =
783 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
784 0 : struct amdgpu_device *adev = hwmgr->adev;
785 :
786 0 : state->CcPwrDynRm = 0;
787 0 : state->CcPwrDynRm1 = 0;
788 :
789 0 : state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
790 0 : state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
791 0 : VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
792 :
793 0 : if ((hwmgr->chip_id == CHIP_POLARIS12) ||
794 0 : ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
795 0 : ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
796 0 : ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
797 0 : ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
798 0 : state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
799 : else
800 0 : state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
801 :
802 : CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
803 : CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
804 0 : CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
805 :
806 0 : return 0;
807 : }
808 :
809 : static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
810 : struct SMU74_Discrete_DpmTable *table)
811 : {
812 0 : return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
813 : }
814 :
815 0 : static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
816 : struct SMU74_Discrete_DpmTable *table)
817 : {
818 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
819 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
820 0 : struct smu7_dpm_table *dpm_table = &data->dpm_table;
821 : int i;
822 :
823 : /* Index (dpm_table->pcie_speed_table.count)
824 : * is reserved for PCIE boot level. */
825 0 : for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
826 0 : table->LinkLevel[i].PcieGenSpeed =
827 0 : (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
828 0 : table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
829 : dpm_table->pcie_speed_table.dpm_levels[i].param1);
830 0 : table->LinkLevel[i].EnabledForActivity = 1;
831 0 : table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
832 0 : table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
833 0 : table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
834 : }
835 :
836 0 : smu_data->smc_state_table.LinkLevelCount =
837 0 : (uint8_t)dpm_table->pcie_speed_table.count;
838 :
839 : /* To Do move to hwmgr */
840 0 : data->dpm_level_enable_mask.pcie_dpm_enable_mask =
841 0 : phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
842 :
843 0 : return 0;
844 : }
845 :
846 :
847 0 : static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
848 : SMU74_Discrete_DpmTable *table)
849 : {
850 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
851 : uint32_t i, ref_clk;
852 :
853 0 : struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
854 :
855 0 : ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
856 :
857 0 : if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
858 0 : for (i = 0; i < NUM_SCLK_RANGE; i++) {
859 0 : table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
860 0 : table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
861 0 : table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
862 :
863 0 : table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
864 0 : table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
865 :
866 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
867 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
868 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
869 : }
870 0 : return;
871 : }
872 :
873 0 : for (i = 0; i < NUM_SCLK_RANGE; i++) {
874 0 : smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
875 0 : smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
876 :
877 0 : table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
878 0 : table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
879 0 : table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
880 :
881 0 : table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
882 0 : table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
883 :
884 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
885 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
886 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
887 : }
888 : }
889 :
890 0 : static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
891 : uint32_t clock, SMU_SclkSetting *sclk_setting)
892 : {
893 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
894 0 : const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
895 : struct pp_atomctrl_clock_dividers_ai dividers;
896 : uint32_t ref_clock;
897 : uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
898 : uint8_t i;
899 : int result;
900 : uint64_t temp;
901 :
902 0 : sclk_setting->SclkFrequency = clock;
903 : /* get the engine clock dividers for this clock value */
904 0 : result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
905 0 : if (result == 0) {
906 0 : sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
907 0 : sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
908 0 : sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
909 0 : sclk_setting->PllRange = dividers.ucSclkPllRange;
910 0 : sclk_setting->Sclk_slew_rate = 0x400;
911 0 : sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
912 0 : sclk_setting->Pcc_down_slew_rate = 0xffff;
913 0 : sclk_setting->SSc_En = dividers.ucSscEnable;
914 0 : sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
915 0 : sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
916 0 : sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
917 0 : return result;
918 : }
919 :
920 0 : ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
921 :
922 0 : for (i = 0; i < NUM_SCLK_RANGE; i++) {
923 0 : if (clock > smu_data->range_table[i].trans_lower_frequency
924 0 : && clock <= smu_data->range_table[i].trans_upper_frequency) {
925 0 : sclk_setting->PllRange = i;
926 0 : break;
927 : }
928 : }
929 :
930 0 : sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
931 0 : temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
932 0 : temp <<= 0x10;
933 0 : do_div(temp, ref_clock);
934 0 : sclk_setting->Fcw_frac = temp & 0xffff;
935 :
936 0 : pcc_target_percent = 10; /* Hardcode 10% for now. */
937 0 : pcc_target_freq = clock - (clock * pcc_target_percent / 100);
938 0 : sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
939 :
940 0 : ss_target_percent = 2; /* Hardcode 2% for now. */
941 : sclk_setting->SSc_En = 0;
942 : if (ss_target_percent) {
943 0 : sclk_setting->SSc_En = 1;
944 0 : ss_target_freq = clock - (clock * ss_target_percent / 100);
945 0 : sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
946 0 : temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
947 0 : temp <<= 0x10;
948 0 : do_div(temp, ref_clock);
949 0 : sclk_setting->Fcw1_frac = temp & 0xffff;
950 : }
951 :
952 0 : return 0;
953 : }
954 :
955 0 : static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
956 : uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
957 : {
958 : int result;
959 : /* PP_Clocks minClocks; */
960 : uint32_t mvdd;
961 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
962 0 : struct phm_ppt_v1_information *table_info =
963 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
964 0 : SMU_SclkSetting curr_sclk_setting = { 0 };
965 0 : phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
966 :
967 0 : result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
968 :
969 0 : if (hwmgr->od_enabled)
970 0 : vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
971 : else
972 0 : vdd_dep_table = table_info->vdd_dep_on_sclk;
973 :
974 : /* populate graphics levels */
975 0 : result = polaris10_get_dependency_volt_by_clk(hwmgr,
976 : vdd_dep_table, clock,
977 : &level->MinVoltage, &mvdd);
978 :
979 0 : PP_ASSERT_WITH_CODE((0 == result),
980 : "can not find VDDC voltage value for "
981 : "VDDC engine clock dependency table",
982 : return result);
983 0 : level->ActivityLevel = data->current_profile_setting.sclk_activity;
984 :
985 0 : level->CcPwrDynRm = 0;
986 0 : level->CcPwrDynRm1 = 0;
987 0 : level->EnabledForActivity = 0;
988 0 : level->EnabledForThrottle = 1;
989 0 : level->UpHyst = data->current_profile_setting.sclk_up_hyst;
990 0 : level->DownHyst = data->current_profile_setting.sclk_down_hyst;
991 0 : level->VoltageDownHyst = 0;
992 0 : level->PowerThrottle = 0;
993 0 : data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
994 :
995 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
996 0 : level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
997 0 : hwmgr->display_config->min_core_set_clock_in_sr);
998 :
999 : /* Default to slow, highest DPM level will be
1000 : * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1001 : */
1002 0 : if (data->update_up_hyst)
1003 0 : level->UpHyst = (uint8_t)data->up_hyst;
1004 0 : if (data->update_down_hyst)
1005 0 : level->DownHyst = (uint8_t)data->down_hyst;
1006 :
1007 0 : level->SclkSetting = curr_sclk_setting;
1008 :
1009 0 : CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1010 0 : CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1011 0 : CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1012 0 : CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1013 0 : CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1014 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1015 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1016 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1017 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1018 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1019 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1020 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1021 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1022 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1023 0 : return 0;
1024 : }
1025 :
1026 : static void polaris10_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr)
1027 : {
1028 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1029 0 : SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1030 : uint8_t shared_rail;
1031 :
1032 0 : if (!atomctrl_get_vddc_shared_railinfo(hwmgr, &shared_rail))
1033 0 : table->SharedRails = shared_rail;
1034 : }
1035 :
1036 0 : static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1037 : {
1038 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1039 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1040 0 : struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1041 0 : struct phm_ppt_v1_information *table_info =
1042 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1043 0 : struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1044 0 : uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
1045 0 : int result = 0;
1046 0 : uint32_t array = smu_data->smu7_data.dpm_table_start +
1047 : offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1048 0 : uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1049 : SMU74_MAX_LEVELS_GRAPHICS;
1050 0 : struct SMU74_Discrete_GraphicsLevel *levels =
1051 : smu_data->smc_state_table.GraphicsLevel;
1052 : uint32_t i, max_entry;
1053 0 : uint8_t hightest_pcie_level_enabled = 0,
1054 0 : lowest_pcie_level_enabled = 0,
1055 0 : mid_pcie_level_enabled = 0,
1056 0 : count = 0;
1057 0 : struct amdgpu_device *adev = hwmgr->adev;
1058 : pp_atomctrl_clock_dividers_vi dividers;
1059 0 : uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency;
1060 :
1061 0 : if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1062 0 : ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
1063 : polaris10_get_vddc_shared_railinfo(hwmgr);
1064 :
1065 0 : polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1066 :
1067 0 : for (i = 0; i < dpm_table->sclk_table.count; i++) {
1068 :
1069 0 : result = polaris10_populate_single_graphic_level(hwmgr,
1070 : dpm_table->sclk_table.dpm_levels[i].value,
1071 0 : &(smu_data->smc_state_table.GraphicsLevel[i]));
1072 0 : if (result)
1073 : return result;
1074 :
1075 : /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1076 0 : if (i > 1)
1077 0 : levels[i].DeepSleepDivId = 0;
1078 : }
1079 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1080 : PHM_PlatformCaps_SPLLShutdownSupport)) {
1081 0 : smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1082 0 : if (dpm0_sclkfrequency != levels[0].SclkSetting.SclkFrequency) {
1083 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1084 : dpm_table->sclk_table.dpm_levels[0].value,
1085 : ÷rs);
1086 0 : PP_ASSERT_WITH_CODE((0 == result),
1087 : "can not find divide id for sclk",
1088 : return result);
1089 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
1090 : PPSMC_MSG_SetGpuPllDfsForSclk,
1091 0 : dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ?
1092 0 : dividers.pll_post_divider - 1 : dividers.pll_post_divider,
1093 : NULL);
1094 : }
1095 : }
1096 :
1097 0 : smu_data->smc_state_table.GraphicsDpmLevelCount =
1098 0 : (uint8_t)dpm_table->sclk_table.count;
1099 0 : hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1100 0 : phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1101 :
1102 0 : for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++)
1103 0 : smu_data->smc_state_table.GraphicsLevel[i].EnabledForActivity =
1104 0 : (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i;
1105 :
1106 0 : if (pcie_table != NULL) {
1107 0 : PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1108 : "There must be 1 or more PCIE levels defined in PPTable.",
1109 : return -EINVAL);
1110 0 : max_entry = pcie_entry_cnt - 1;
1111 0 : for (i = 0; i < dpm_table->sclk_table.count; i++)
1112 0 : levels[i].pcieDpmLevel =
1113 0 : (uint8_t) ((i < max_entry) ? i : max_entry);
1114 : } else {
1115 0 : while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1116 0 : ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1117 0 : (1 << (hightest_pcie_level_enabled + 1))) != 0))
1118 0 : hightest_pcie_level_enabled++;
1119 :
1120 0 : while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1121 0 : ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1122 0 : (1 << lowest_pcie_level_enabled)) == 0))
1123 0 : lowest_pcie_level_enabled++;
1124 :
1125 0 : while ((count < hightest_pcie_level_enabled) &&
1126 0 : ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1127 0 : (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1128 0 : count++;
1129 :
1130 0 : mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1131 : hightest_pcie_level_enabled ?
1132 0 : (lowest_pcie_level_enabled + 1 + count) :
1133 : hightest_pcie_level_enabled;
1134 :
1135 : /* set pcieDpmLevel to hightest_pcie_level_enabled */
1136 0 : for (i = 2; i < dpm_table->sclk_table.count; i++)
1137 0 : levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1138 :
1139 : /* set pcieDpmLevel to lowest_pcie_level_enabled */
1140 0 : levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1141 :
1142 : /* set pcieDpmLevel to mid_pcie_level_enabled */
1143 0 : levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1144 : }
1145 : /* level count will send to smc once at init smc table and never change */
1146 0 : result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1147 : (uint32_t)array_size, SMC_RAM_END);
1148 :
1149 0 : return result;
1150 : }
1151 :
1152 :
1153 0 : static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1154 : uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1155 : {
1156 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1157 0 : struct phm_ppt_v1_information *table_info =
1158 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1159 0 : int result = 0;
1160 0 : uint32_t mclk_stutter_mode_threshold = 40000;
1161 0 : phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1162 :
1163 :
1164 0 : if (hwmgr->od_enabled)
1165 0 : vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1166 : else
1167 0 : vdd_dep_table = table_info->vdd_dep_on_mclk;
1168 :
1169 0 : if (vdd_dep_table) {
1170 0 : result = polaris10_get_dependency_volt_by_clk(hwmgr,
1171 : vdd_dep_table, clock,
1172 : &mem_level->MinVoltage, &mem_level->MinMvdd);
1173 0 : PP_ASSERT_WITH_CODE((0 == result),
1174 : "can not find MinVddc voltage value from memory "
1175 : "VDDC voltage dependency table", return result);
1176 : }
1177 :
1178 0 : mem_level->MclkFrequency = clock;
1179 0 : mem_level->EnabledForThrottle = 1;
1180 0 : mem_level->EnabledForActivity = 0;
1181 0 : mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1182 0 : mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1183 0 : mem_level->VoltageDownHyst = 0;
1184 0 : mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1185 0 : mem_level->StutterEnable = false;
1186 0 : mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1187 :
1188 0 : data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1189 0 : data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1190 :
1191 0 : if (mclk_stutter_mode_threshold &&
1192 0 : (clock <= mclk_stutter_mode_threshold) &&
1193 0 : (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1194 0 : STUTTER_ENABLE) & 0x1) &&
1195 0 : (data->display_timing.num_existing_displays <= 2) &&
1196 : data->display_timing.num_existing_displays)
1197 0 : mem_level->StutterEnable = true;
1198 :
1199 0 : if (!result) {
1200 0 : CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1201 0 : CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1202 0 : CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1203 0 : CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1204 : }
1205 : return result;
1206 : }
1207 :
1208 0 : static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1209 : {
1210 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1211 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1212 0 : struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1213 : int result;
1214 : /* populate MCLK dpm table to SMU7 */
1215 0 : uint32_t array = smu_data->smu7_data.dpm_table_start +
1216 : offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1217 0 : uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1218 : SMU74_MAX_LEVELS_MEMORY;
1219 0 : struct SMU74_Discrete_MemoryLevel *levels =
1220 : smu_data->smc_state_table.MemoryLevel;
1221 : uint32_t i;
1222 :
1223 0 : for (i = 0; i < dpm_table->mclk_table.count; i++) {
1224 0 : PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1225 : "can not populate memory level as memory clock is zero",
1226 : return -EINVAL);
1227 0 : result = polaris10_populate_single_memory_level(hwmgr,
1228 : dpm_table->mclk_table.dpm_levels[i].value,
1229 0 : &levels[i]);
1230 0 : if (i == dpm_table->mclk_table.count - 1)
1231 0 : levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1232 0 : if (result)
1233 : return result;
1234 : }
1235 :
1236 0 : smu_data->smc_state_table.MemoryDpmLevelCount =
1237 0 : (uint8_t)dpm_table->mclk_table.count;
1238 0 : hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1239 0 : phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1240 :
1241 0 : for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++)
1242 0 : smu_data->smc_state_table.MemoryLevel[i].EnabledForActivity =
1243 0 : (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask & (1 << i)) >> i;
1244 :
1245 : /* level count will send to smc once at init smc table and never change */
1246 0 : result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1247 : (uint32_t)array_size, SMC_RAM_END);
1248 :
1249 0 : return result;
1250 : }
1251 :
1252 0 : static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1253 : uint32_t mclk, SMIO_Pattern *smio_pat)
1254 : {
1255 0 : const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1256 0 : struct phm_ppt_v1_information *table_info =
1257 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1258 0 : uint32_t i = 0;
1259 :
1260 0 : if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1261 : /* find mvdd value which clock is more than request */
1262 0 : for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1263 0 : if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1264 0 : smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1265 : break;
1266 : }
1267 : }
1268 0 : PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1269 : "MVDD Voltage is outside the supported range.",
1270 : return -EINVAL);
1271 : } else
1272 : return -EINVAL;
1273 :
1274 : return 0;
1275 : }
1276 :
1277 0 : static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1278 : SMU74_Discrete_DpmTable *table)
1279 : {
1280 0 : int result = 0;
1281 : uint32_t sclk_frequency;
1282 0 : const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1283 0 : struct phm_ppt_v1_information *table_info =
1284 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1285 : SMIO_Pattern vol_level;
1286 : uint32_t mvdd;
1287 :
1288 0 : table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1289 :
1290 : /* Get MinVoltage and Frequency from DPM0,
1291 : * already converted to SMC_UL */
1292 0 : sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1293 0 : result = polaris10_get_dependency_volt_by_clk(hwmgr,
1294 : table_info->vdd_dep_on_sclk,
1295 : sclk_frequency,
1296 : &table->ACPILevel.MinVoltage, &mvdd);
1297 0 : PP_ASSERT_WITH_CODE((0 == result),
1298 : "Cannot find ACPI VDDC voltage value "
1299 : "in Clock Dependency Table",
1300 : );
1301 :
1302 0 : result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1303 0 : PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1304 :
1305 0 : table->ACPILevel.DeepSleepDivId = 0;
1306 0 : table->ACPILevel.CcPwrDynRm = 0;
1307 0 : table->ACPILevel.CcPwrDynRm1 = 0;
1308 :
1309 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1310 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1311 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1312 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1313 :
1314 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1315 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1316 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1317 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1318 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1319 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1320 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1321 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1322 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1323 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1324 :
1325 :
1326 : /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1327 0 : table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1328 0 : result = polaris10_get_dependency_volt_by_clk(hwmgr,
1329 : table_info->vdd_dep_on_mclk,
1330 : table->MemoryACPILevel.MclkFrequency,
1331 : &table->MemoryACPILevel.MinVoltage, &mvdd);
1332 0 : PP_ASSERT_WITH_CODE((0 == result),
1333 : "Cannot find ACPI VDDCI voltage value "
1334 : "in Clock Dependency Table",
1335 : );
1336 :
1337 0 : if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1338 0 : (data->mclk_dpm_key_disabled)))
1339 0 : polaris10_populate_mvdd_value(hwmgr,
1340 : data->dpm_table.mclk_table.dpm_levels[0].value,
1341 : &vol_level);
1342 :
1343 0 : if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1344 0 : table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1345 : else
1346 0 : table->MemoryACPILevel.MinMvdd = 0;
1347 :
1348 0 : table->MemoryACPILevel.StutterEnable = false;
1349 :
1350 0 : table->MemoryACPILevel.EnabledForThrottle = 0;
1351 0 : table->MemoryACPILevel.EnabledForActivity = 0;
1352 0 : table->MemoryACPILevel.UpHyst = 0;
1353 0 : table->MemoryACPILevel.DownHyst = 100;
1354 0 : table->MemoryACPILevel.VoltageDownHyst = 0;
1355 : /* To align with the settings from other OSes */
1356 0 : table->MemoryACPILevel.ActivityLevel =
1357 0 : PP_HOST_TO_SMC_US(data->current_profile_setting.sclk_activity);
1358 :
1359 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1360 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1361 :
1362 0 : return result;
1363 : }
1364 :
1365 0 : static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1366 : SMU74_Discrete_DpmTable *table)
1367 : {
1368 0 : int result = -EINVAL;
1369 : uint8_t count;
1370 : struct pp_atomctrl_clock_dividers_vi dividers;
1371 0 : struct phm_ppt_v1_information *table_info =
1372 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1373 0 : struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1374 : table_info->mm_dep_table;
1375 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1376 : uint32_t vddci;
1377 :
1378 0 : table->VceLevelCount = (uint8_t)(mm_table->count);
1379 0 : table->VceBootLevel = 0;
1380 :
1381 0 : for (count = 0; count < table->VceLevelCount; count++) {
1382 0 : table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1383 0 : table->VceLevel[count].MinVoltage = 0;
1384 0 : table->VceLevel[count].MinVoltage |=
1385 0 : (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1386 :
1387 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1388 0 : vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1389 0 : mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1390 0 : else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1391 0 : vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1392 : else
1393 0 : vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1394 :
1395 :
1396 0 : table->VceLevel[count].MinVoltage |=
1397 0 : (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1398 0 : table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1399 :
1400 : /*retrieve divider value for VBIOS */
1401 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1402 : table->VceLevel[count].Frequency, ÷rs);
1403 0 : PP_ASSERT_WITH_CODE((0 == result),
1404 : "can not find divide id for VCE engine clock",
1405 : return result);
1406 :
1407 0 : table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1408 :
1409 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1410 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1411 : }
1412 : return result;
1413 : }
1414 :
1415 0 : static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1416 : SMU74_Discrete_DpmTable *table)
1417 : {
1418 0 : int result = -EINVAL;
1419 : uint8_t count;
1420 : struct pp_atomctrl_clock_dividers_vi dividers;
1421 0 : struct phm_ppt_v1_information *table_info =
1422 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1423 0 : struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1424 : table_info->mm_dep_table;
1425 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1426 : uint32_t vddci;
1427 :
1428 0 : table->SamuLevelCount = (uint8_t)(mm_table->count);
1429 0 : table->SamuBootLevel = 0;
1430 :
1431 0 : for (count = 0; count < table->SamuLevelCount; count++) {
1432 0 : table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1433 0 : table->SamuLevel[count].MinVoltage |=
1434 0 : (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1435 :
1436 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1437 0 : vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1438 0 : mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1439 0 : else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1440 0 : vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1441 : else
1442 0 : vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1443 :
1444 :
1445 0 : table->SamuLevel[count].MinVoltage |=
1446 0 : (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1447 0 : table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1448 :
1449 : /*retrieve divider value for VBIOS */
1450 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1451 : table->SamuLevel[count].Frequency, ÷rs);
1452 0 : PP_ASSERT_WITH_CODE((0 == result),
1453 : "can not find divide id for VCE engine clock",
1454 : return result);
1455 :
1456 0 : table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1457 :
1458 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1459 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1460 : }
1461 : return result;
1462 : }
1463 :
1464 0 : static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1465 : int32_t eng_clock, int32_t mem_clock,
1466 : SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1467 : {
1468 : uint32_t dram_timing;
1469 : uint32_t dram_timing2;
1470 : uint32_t burst_time;
1471 : int result;
1472 :
1473 0 : result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1474 : eng_clock, mem_clock);
1475 0 : PP_ASSERT_WITH_CODE(result == 0,
1476 : "Error calling VBIOS to set DRAM_TIMING.", return result);
1477 :
1478 0 : dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1479 0 : dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1480 0 : burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1481 :
1482 :
1483 0 : arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1484 0 : arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1485 0 : arb_regs->McArbBurstTime = (uint8_t)burst_time;
1486 :
1487 0 : return 0;
1488 : }
1489 :
1490 0 : static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1491 : {
1492 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1493 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1494 : struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1495 : uint32_t i, j;
1496 0 : int result = 0;
1497 :
1498 0 : for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1499 0 : for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1500 0 : result = polaris10_populate_memory_timing_parameters(hwmgr,
1501 0 : hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1502 0 : hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1503 : &arb_regs.entries[i][j]);
1504 0 : if (result == 0 && i == 0)
1505 0 : result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1506 0 : if (result != 0)
1507 : return result;
1508 : }
1509 : }
1510 :
1511 0 : result = smu7_copy_bytes_to_smc(
1512 : hwmgr,
1513 : smu_data->smu7_data.arb_table_start,
1514 : (uint8_t *)&arb_regs,
1515 : sizeof(SMU74_Discrete_MCArbDramTimingTable),
1516 : SMC_RAM_END);
1517 0 : return result;
1518 : }
1519 :
1520 0 : static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1521 : struct SMU74_Discrete_DpmTable *table)
1522 : {
1523 0 : int result = -EINVAL;
1524 : uint8_t count;
1525 : struct pp_atomctrl_clock_dividers_vi dividers;
1526 0 : struct phm_ppt_v1_information *table_info =
1527 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1528 0 : struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1529 : table_info->mm_dep_table;
1530 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1531 : uint32_t vddci;
1532 :
1533 0 : table->UvdLevelCount = (uint8_t)(mm_table->count);
1534 0 : table->UvdBootLevel = 0;
1535 :
1536 0 : for (count = 0; count < table->UvdLevelCount; count++) {
1537 0 : table->UvdLevel[count].MinVoltage = 0;
1538 0 : table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1539 0 : table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1540 0 : table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1541 0 : VOLTAGE_SCALE) << VDDC_SHIFT;
1542 :
1543 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1544 0 : vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1545 0 : mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1546 0 : else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1547 0 : vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1548 : else
1549 0 : vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1550 :
1551 0 : table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1552 0 : table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1553 :
1554 : /* retrieve divider value for VBIOS */
1555 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1556 : table->UvdLevel[count].VclkFrequency, ÷rs);
1557 0 : PP_ASSERT_WITH_CODE((0 == result),
1558 : "can not find divide id for Vclk clock", return result);
1559 :
1560 0 : table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1561 :
1562 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1563 : table->UvdLevel[count].DclkFrequency, ÷rs);
1564 0 : PP_ASSERT_WITH_CODE((0 == result),
1565 : "can not find divide id for Dclk clock", return result);
1566 :
1567 0 : table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1568 :
1569 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1570 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1571 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1572 : }
1573 :
1574 : return result;
1575 : }
1576 :
1577 0 : static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1578 : struct SMU74_Discrete_DpmTable *table)
1579 : {
1580 0 : int result = 0;
1581 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1582 :
1583 0 : table->GraphicsBootLevel = 0;
1584 0 : table->MemoryBootLevel = 0;
1585 :
1586 : /* find boot level from dpm table */
1587 0 : result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1588 : data->vbios_boot_state.sclk_bootup_value,
1589 0 : (uint32_t *)&(table->GraphicsBootLevel));
1590 0 : if (result) {
1591 0 : table->GraphicsBootLevel = 0;
1592 0 : result = 0;
1593 : }
1594 :
1595 0 : result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1596 : data->vbios_boot_state.mclk_bootup_value,
1597 0 : (uint32_t *)&(table->MemoryBootLevel));
1598 0 : if (result) {
1599 0 : table->MemoryBootLevel = 0;
1600 0 : result = 0;
1601 : }
1602 :
1603 0 : table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1604 : VOLTAGE_SCALE;
1605 0 : table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1606 : VOLTAGE_SCALE;
1607 0 : table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1608 : VOLTAGE_SCALE;
1609 :
1610 0 : CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1611 0 : CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1612 0 : CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1613 :
1614 0 : return 0;
1615 : }
1616 :
1617 0 : static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1618 : {
1619 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1620 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1621 0 : struct phm_ppt_v1_information *table_info =
1622 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1623 : uint8_t count, level;
1624 :
1625 0 : count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1626 :
1627 0 : for (level = 0; level < count; level++) {
1628 0 : if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1629 0 : hw_data->vbios_boot_state.sclk_bootup_value) {
1630 0 : smu_data->smc_state_table.GraphicsBootLevel = level;
1631 0 : break;
1632 : }
1633 : }
1634 :
1635 0 : count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1636 0 : for (level = 0; level < count; level++) {
1637 0 : if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1638 0 : hw_data->vbios_boot_state.mclk_bootup_value) {
1639 0 : smu_data->smc_state_table.MemoryBootLevel = level;
1640 0 : break;
1641 : }
1642 : }
1643 :
1644 0 : return 0;
1645 : }
1646 :
1647 : #define STRAP_ASIC_RO_LSB 2168
1648 : #define STRAP_ASIC_RO_MSB 2175
1649 :
1650 0 : static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1651 : {
1652 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1653 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1654 0 : struct phm_ppt_v1_information *table_info =
1655 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1656 0 : struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1657 : table_info->vdd_dep_on_sclk;
1658 : uint32_t ro, efuse, volt_without_cks, volt_with_cks, value;
1659 0 : uint8_t i, stretch_amount, volt_offset = 0;
1660 :
1661 0 : stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1662 :
1663 : /* Read SMU_Eefuse to read and calculate RO and determine
1664 : * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1665 : */
1666 0 : atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB, &efuse);
1667 0 : ro = ((efuse * (data->ro_range_maximum - data->ro_range_minimum)) / 255) +
1668 : data->ro_range_minimum;
1669 :
1670 : /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1671 0 : for (i = 0; i < sclk_table->count; i++) {
1672 0 : smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1673 0 : sclk_table->entries[i].cks_enable << i;
1674 0 : if (hwmgr->chip_id == CHIP_POLARIS10) {
1675 0 : volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
1676 0 : (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1677 0 : volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1678 0 : (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1679 : } else {
1680 0 : volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
1681 0 : (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1682 0 : volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1683 0 : (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1684 : }
1685 :
1686 0 : if (volt_without_cks >= volt_with_cks)
1687 0 : volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1688 0 : sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1689 :
1690 0 : smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1691 : }
1692 :
1693 0 : smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1694 :
1695 : /* Populate CKS Lookup Table */
1696 0 : if (stretch_amount == 0 || stretch_amount > 5) {
1697 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1698 : PHM_PlatformCaps_ClockStretcher);
1699 0 : PP_ASSERT_WITH_CODE(false,
1700 : "Stretch Amount in PPTable not supported",
1701 : return -EINVAL);
1702 : }
1703 :
1704 0 : value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1705 0 : value &= 0xFFFFFFFE;
1706 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1707 :
1708 0 : return 0;
1709 : }
1710 :
1711 0 : static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1712 : struct SMU74_Discrete_DpmTable *table)
1713 : {
1714 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1715 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1716 : uint16_t config;
1717 :
1718 0 : config = VR_MERGED_WITH_VDDC;
1719 0 : table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1720 :
1721 : /* Set Vddc Voltage Controller */
1722 0 : if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1723 0 : config = VR_SVI2_PLANE_1;
1724 0 : table->VRConfig |= config;
1725 0 : } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
1726 0 : config = VR_SMIO_PATTERN_1;
1727 0 : table->VRConfig |= config;
1728 : } else {
1729 0 : PP_ASSERT_WITH_CODE(false,
1730 : "VDDC should be on SVI2 control in merged mode!",
1731 : );
1732 : }
1733 : /* Set Vddci Voltage Controller */
1734 0 : if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1735 0 : config = VR_SVI2_PLANE_2; /* only in merged mode */
1736 0 : table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1737 0 : } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1738 0 : config = VR_SMIO_PATTERN_1;
1739 0 : table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1740 : } else {
1741 0 : config = VR_STATIC_VOLTAGE;
1742 0 : table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1743 : }
1744 : /* Set Mvdd Voltage Controller */
1745 0 : if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1746 0 : if (config != VR_SVI2_PLANE_2) {
1747 0 : config = VR_SVI2_PLANE_2;
1748 0 : table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1749 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1750 : offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1751 : } else {
1752 0 : config = VR_STATIC_VOLTAGE;
1753 0 : table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1754 : }
1755 0 : } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1756 0 : config = VR_SMIO_PATTERN_2;
1757 0 : table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1758 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1759 : offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1760 : } else {
1761 0 : config = VR_STATIC_VOLTAGE;
1762 0 : table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1763 : }
1764 :
1765 0 : return 0;
1766 : }
1767 :
1768 :
1769 0 : static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1770 : {
1771 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1772 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1773 0 : struct amdgpu_device *adev = hwmgr->adev;
1774 :
1775 0 : SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1776 0 : int result = 0;
1777 0 : struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1778 0 : AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1779 0 : AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1780 : uint32_t tmp, i;
1781 :
1782 0 : struct phm_ppt_v1_information *table_info =
1783 : (struct phm_ppt_v1_information *)hwmgr->pptable;
1784 0 : struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1785 : table_info->vdd_dep_on_sclk;
1786 :
1787 :
1788 0 : if (!hwmgr->avfs_supported)
1789 : return 0;
1790 :
1791 :
1792 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
1793 0 : hwmgr->avfs_supported = 0;
1794 0 : return 0;
1795 : }
1796 :
1797 0 : result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1798 :
1799 0 : if (0 == result) {
1800 0 : if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1801 0 : ((hwmgr->chip_id == CHIP_POLARIS12) && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) ||
1802 0 : ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)) {
1803 0 : avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1804 0 : if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) ||
1805 0 : (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) {
1806 0 : if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) &&
1807 0 : (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) &&
1808 0 : (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) &&
1809 0 : (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) &&
1810 0 : (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) &&
1811 0 : (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) {
1812 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF718F1D4;
1813 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x323FD;
1814 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x1E455;
1815 0 : avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1816 0 : avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0;
1817 0 : avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x23;
1818 : }
1819 0 : } else if (hwmgr->chip_id == CHIP_POLARIS12 && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
1820 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF6B024DD;
1821 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x3005E;
1822 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x18A5F;
1823 0 : avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
1824 0 : avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
1825 0 : avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x3B;
1826 0 : } else if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision)) {
1827 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF843B66B;
1828 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x59CB5;
1829 0 : avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0xFFFF287F;
1830 0 : avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1831 0 : avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
1832 0 : avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x58;
1833 : }
1834 : }
1835 : }
1836 :
1837 0 : if (0 == result) {
1838 0 : table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1839 0 : table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1840 0 : table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1841 0 : table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1842 0 : table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1843 0 : table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1844 0 : table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1845 0 : table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1846 0 : table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1847 0 : table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1848 0 : table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1849 0 : table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1850 0 : table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1851 0 : table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1852 0 : table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1853 0 : table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1854 0 : table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1855 0 : AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1856 0 : AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1857 0 : AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1858 0 : AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1859 0 : AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1860 0 : AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1861 0 : AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1862 :
1863 0 : for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1864 0 : AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1865 0 : AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1866 : }
1867 :
1868 0 : result = smu7_read_smc_sram_dword(hwmgr,
1869 : SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1870 : &tmp, SMC_RAM_END);
1871 :
1872 0 : smu7_copy_bytes_to_smc(hwmgr,
1873 : tmp,
1874 : (uint8_t *)&AVFS_meanNsigma,
1875 : sizeof(AVFS_meanNsigma_t),
1876 : SMC_RAM_END);
1877 :
1878 0 : result = smu7_read_smc_sram_dword(hwmgr,
1879 : SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1880 : &tmp, SMC_RAM_END);
1881 0 : smu7_copy_bytes_to_smc(hwmgr,
1882 : tmp,
1883 : (uint8_t *)&AVFS_SclkOffset,
1884 : sizeof(AVFS_Sclk_Offset_t),
1885 : SMC_RAM_END);
1886 :
1887 0 : data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1888 0 : (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1889 0 : (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1890 0 : (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1891 0 : data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1892 : }
1893 : return result;
1894 : }
1895 :
1896 : static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1897 : {
1898 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1899 0 : struct phm_ppt_v1_information *table_info =
1900 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1901 :
1902 0 : if (table_info &&
1903 0 : table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
1904 : table_info->cac_dtp_table->usPowerTuneDataSetID)
1905 0 : smu_data->power_tune_defaults =
1906 0 : &polaris10_power_tune_data_set_array
1907 0 : [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
1908 : else
1909 0 : smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
1910 :
1911 : }
1912 :
1913 0 : static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1914 : {
1915 : int result;
1916 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1917 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1918 :
1919 0 : struct phm_ppt_v1_information *table_info =
1920 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1921 0 : struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1922 : uint8_t i;
1923 : struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1924 : pp_atomctrl_clock_dividers_vi dividers;
1925 0 : struct phm_ppt_v1_gpio_table *gpio_table = table_info->gpio_table;
1926 :
1927 0 : polaris10_initialize_power_tune_defaults(hwmgr);
1928 :
1929 0 : if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1930 0 : polaris10_populate_smc_voltage_tables(hwmgr, table);
1931 :
1932 0 : table->SystemFlags = 0;
1933 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1934 : PHM_PlatformCaps_AutomaticDCTransition))
1935 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1936 :
1937 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1938 : PHM_PlatformCaps_StepVddc))
1939 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1940 :
1941 0 : if (hw_data->is_memory_gddr5)
1942 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1943 :
1944 0 : if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1945 0 : result = polaris10_populate_ulv_state(hwmgr, table);
1946 0 : PP_ASSERT_WITH_CODE(0 == result,
1947 : "Failed to initialize ULV state!", return result);
1948 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1949 : ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1950 : }
1951 :
1952 0 : result = polaris10_populate_smc_link_level(hwmgr, table);
1953 0 : PP_ASSERT_WITH_CODE(0 == result,
1954 : "Failed to initialize Link Level!", return result);
1955 :
1956 0 : result = polaris10_populate_all_graphic_levels(hwmgr);
1957 0 : PP_ASSERT_WITH_CODE(0 == result,
1958 : "Failed to initialize Graphics Level!", return result);
1959 :
1960 0 : result = polaris10_populate_all_memory_levels(hwmgr);
1961 0 : PP_ASSERT_WITH_CODE(0 == result,
1962 : "Failed to initialize Memory Level!", return result);
1963 :
1964 0 : result = polaris10_populate_smc_acpi_level(hwmgr, table);
1965 0 : PP_ASSERT_WITH_CODE(0 == result,
1966 : "Failed to initialize ACPI Level!", return result);
1967 :
1968 0 : result = polaris10_populate_smc_vce_level(hwmgr, table);
1969 0 : PP_ASSERT_WITH_CODE(0 == result,
1970 : "Failed to initialize VCE Level!", return result);
1971 :
1972 0 : result = polaris10_populate_smc_samu_level(hwmgr, table);
1973 0 : PP_ASSERT_WITH_CODE(0 == result,
1974 : "Failed to initialize SAMU Level!", return result);
1975 :
1976 : /* Since only the initial state is completely set up at this point
1977 : * (the other states are just copies of the boot state) we only
1978 : * need to populate the ARB settings for the initial state.
1979 : */
1980 0 : result = polaris10_program_memory_timing_parameters(hwmgr);
1981 0 : PP_ASSERT_WITH_CODE(0 == result,
1982 : "Failed to Write ARB settings for the initial state.", return result);
1983 :
1984 0 : result = polaris10_populate_smc_uvd_level(hwmgr, table);
1985 0 : PP_ASSERT_WITH_CODE(0 == result,
1986 : "Failed to initialize UVD Level!", return result);
1987 :
1988 0 : result = polaris10_populate_smc_boot_level(hwmgr, table);
1989 0 : PP_ASSERT_WITH_CODE(0 == result,
1990 : "Failed to initialize Boot Level!", return result);
1991 :
1992 0 : result = polaris10_populate_smc_initailial_state(hwmgr);
1993 0 : PP_ASSERT_WITH_CODE(0 == result,
1994 : "Failed to initialize Boot State!", return result);
1995 :
1996 0 : result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
1997 0 : PP_ASSERT_WITH_CODE(0 == result,
1998 : "Failed to populate BAPM Parameters!", return result);
1999 :
2000 0 : polaris10_populate_zero_rpm_parameters(hwmgr);
2001 :
2002 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2003 : PHM_PlatformCaps_ClockStretcher)) {
2004 0 : result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2005 0 : PP_ASSERT_WITH_CODE(0 == result,
2006 : "Failed to populate Clock Stretcher Data Table!",
2007 : return result);
2008 : }
2009 :
2010 0 : result = polaris10_populate_avfs_parameters(hwmgr);
2011 0 : PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2012 :
2013 0 : table->CurrSclkPllRange = 0xff;
2014 0 : table->GraphicsVoltageChangeEnable = 1;
2015 0 : table->GraphicsThermThrottleEnable = 1;
2016 0 : table->GraphicsInterval = 1;
2017 0 : table->VoltageInterval = 1;
2018 0 : table->ThermalInterval = 1;
2019 0 : table->TemperatureLimitHigh =
2020 0 : table_info->cac_dtp_table->usTargetOperatingTemp *
2021 : SMU7_Q88_FORMAT_CONVERSION_UNIT;
2022 0 : table->TemperatureLimitLow =
2023 0 : (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2024 : SMU7_Q88_FORMAT_CONVERSION_UNIT;
2025 0 : table->MemoryVoltageChangeEnable = 1;
2026 0 : table->MemoryInterval = 1;
2027 0 : table->VoltageResponseTime = 0;
2028 0 : table->PhaseResponseTime = 0;
2029 0 : table->MemoryThermThrottleEnable = 1;
2030 0 : table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count;
2031 0 : table->PCIeGenInterval = 1;
2032 0 : table->VRConfig = 0;
2033 :
2034 0 : result = polaris10_populate_vr_config(hwmgr, table);
2035 0 : PP_ASSERT_WITH_CODE(0 == result,
2036 : "Failed to populate VRConfig setting!", return result);
2037 0 : hw_data->vr_config = table->VRConfig;
2038 0 : table->ThermGpio = 17;
2039 0 : table->SclkStepSize = 0x4000;
2040 :
2041 0 : if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2042 0 : table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2043 0 : if (gpio_table)
2044 0 : table->VRHotLevel = gpio_table->vrhot_triggered_sclk_dpm_index;
2045 : } else {
2046 0 : table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2047 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2048 : PHM_PlatformCaps_RegulatorHot);
2049 : }
2050 :
2051 0 : if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2052 : &gpio_pin)) {
2053 0 : table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2054 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2055 0 : PHM_PlatformCaps_AutomaticDCTransition) &&
2056 0 : !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
2057 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2058 : PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
2059 : } else {
2060 0 : table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2061 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2062 : PHM_PlatformCaps_AutomaticDCTransition);
2063 : }
2064 :
2065 : /* Thermal Output GPIO */
2066 0 : if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2067 : &gpio_pin)) {
2068 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2069 : PHM_PlatformCaps_ThermalOutGPIO);
2070 :
2071 0 : table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2072 :
2073 : /* For porlarity read GPIOPAD_A with assigned Gpio pin
2074 : * since VBIOS will program this register to set 'inactive state',
2075 : * driver can then determine 'active state' from this and
2076 : * program SMU with correct polarity
2077 : */
2078 0 : table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2079 0 : & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2080 0 : table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2081 :
2082 : /* if required, combine VRHot/PCC with thermal out GPIO */
2083 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2084 0 : && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2085 0 : table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2086 : } else {
2087 0 : table->ThermOutGpio = 17;
2088 0 : table->ThermOutPolarity = 1;
2089 0 : table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2090 : }
2091 :
2092 : /* Populate BIF_SCLK levels into SMC DPM table */
2093 0 : for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2094 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], ÷rs);
2095 0 : PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2096 :
2097 0 : if (i == 0)
2098 0 : table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2099 : else
2100 0 : table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2101 : }
2102 :
2103 0 : for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2104 0 : table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2105 :
2106 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2107 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2108 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2109 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2110 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2111 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2112 0 : CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2113 0 : CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2114 0 : CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2115 0 : CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2116 :
2117 : /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2118 0 : result = smu7_copy_bytes_to_smc(hwmgr,
2119 0 : smu_data->smu7_data.dpm_table_start +
2120 : offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2121 0 : (uint8_t *)&(table->SystemFlags),
2122 : sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2123 : SMC_RAM_END);
2124 0 : PP_ASSERT_WITH_CODE(0 == result,
2125 : "Failed to upload dpm data to SMC memory!", return result);
2126 :
2127 0 : result = polaris10_populate_pm_fuses(hwmgr);
2128 0 : PP_ASSERT_WITH_CODE(0 == result,
2129 : "Failed to populate PM fuses to SMC memory!", return result);
2130 :
2131 : return 0;
2132 : }
2133 :
2134 : static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2135 : {
2136 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2137 :
2138 0 : if (data->need_update_smu7_dpm_table &
2139 : (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2140 0 : return polaris10_program_memory_timing_parameters(hwmgr);
2141 :
2142 : return 0;
2143 : }
2144 :
2145 0 : static int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2146 : {
2147 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2148 :
2149 0 : if (!hwmgr->avfs_supported)
2150 : return 0;
2151 :
2152 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2153 : PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting,
2154 : NULL);
2155 :
2156 0 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2157 :
2158 : /* Apply avfs cks-off voltages to avoid the overshoot
2159 : * when switching to the highest sclk frequency
2160 : */
2161 0 : if (data->apply_avfs_cks_off_voltage)
2162 0 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage, NULL);
2163 :
2164 : return 0;
2165 : }
2166 :
2167 0 : static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2168 : {
2169 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2170 0 : SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2171 : uint32_t duty100;
2172 : uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2173 : uint16_t fdo_min, slope1, slope2;
2174 : uint32_t reference_clock;
2175 : int res;
2176 : uint64_t tmp64;
2177 :
2178 0 : if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2179 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2180 : PHM_PlatformCaps_MicrocodeFanControl);
2181 0 : return 0;
2182 : }
2183 :
2184 0 : if (smu_data->smu7_data.fan_table_start == 0) {
2185 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2186 : PHM_PlatformCaps_MicrocodeFanControl);
2187 0 : return 0;
2188 : }
2189 :
2190 0 : duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2191 : CG_FDO_CTRL1, FMAX_DUTY100);
2192 :
2193 0 : if (duty100 == 0) {
2194 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2195 : PHM_PlatformCaps_MicrocodeFanControl);
2196 0 : return 0;
2197 : }
2198 :
2199 : /* use hardware fan control */
2200 0 : if (hwmgr->thermal_controller.use_hw_fan_control)
2201 : return 0;
2202 :
2203 0 : tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2204 0 : usPWMMin * duty100;
2205 0 : do_div(tmp64, 10000);
2206 0 : fdo_min = (uint16_t)tmp64;
2207 :
2208 0 : t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2209 0 : hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2210 0 : t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2211 : hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2212 :
2213 0 : pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2214 0 : hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2215 0 : pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2216 : hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2217 :
2218 0 : slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2219 0 : slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2220 :
2221 0 : fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2222 : thermal_controller.advanceFanControlParameters.usTMin) / 100);
2223 0 : fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2224 : thermal_controller.advanceFanControlParameters.usTMed) / 100);
2225 0 : fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2226 : thermal_controller.advanceFanControlParameters.usTMax) / 100);
2227 :
2228 0 : fan_table.Slope1 = cpu_to_be16(slope1);
2229 0 : fan_table.Slope2 = cpu_to_be16(slope2);
2230 :
2231 0 : fan_table.FdoMin = cpu_to_be16(fdo_min);
2232 :
2233 0 : fan_table.HystDown = cpu_to_be16(hwmgr->
2234 : thermal_controller.advanceFanControlParameters.ucTHyst);
2235 :
2236 0 : fan_table.HystUp = cpu_to_be16(1);
2237 :
2238 0 : fan_table.HystSlope = cpu_to_be16(1);
2239 :
2240 0 : fan_table.TempRespLim = cpu_to_be16(5);
2241 :
2242 0 : reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2243 :
2244 0 : fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2245 : thermal_controller.advanceFanControlParameters.ulCycleDelay *
2246 : reference_clock) / 1600);
2247 :
2248 0 : fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2249 :
2250 0 : fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2251 : hwmgr->device, CGS_IND_REG__SMC,
2252 : CG_MULT_THERMAL_CTRL, TEMP_SEL);
2253 :
2254 0 : res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2255 : (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2256 : SMC_RAM_END);
2257 :
2258 0 : if (!res && hwmgr->thermal_controller.
2259 0 : advanceFanControlParameters.ucMinimumPWMLimit)
2260 0 : res = smum_send_msg_to_smc_with_parameter(hwmgr,
2261 : PPSMC_MSG_SetFanMinPwm,
2262 : hwmgr->thermal_controller.
2263 : advanceFanControlParameters.ucMinimumPWMLimit,
2264 : NULL);
2265 :
2266 0 : if (!res && hwmgr->thermal_controller.
2267 0 : advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2268 0 : res = smum_send_msg_to_smc_with_parameter(hwmgr,
2269 : PPSMC_MSG_SetFanSclkTarget,
2270 : hwmgr->thermal_controller.
2271 : advanceFanControlParameters.ulMinFanSCLKAcousticLimit,
2272 : NULL);
2273 :
2274 0 : if (res)
2275 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2276 : PHM_PlatformCaps_MicrocodeFanControl);
2277 :
2278 : return 0;
2279 : }
2280 :
2281 0 : static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2282 : {
2283 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2284 : uint32_t mm_boot_level_offset, mm_boot_level_value;
2285 0 : struct phm_ppt_v1_information *table_info =
2286 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
2287 :
2288 0 : smu_data->smc_state_table.UvdBootLevel = 0;
2289 0 : if (table_info->mm_dep_table->count > 0)
2290 0 : smu_data->smc_state_table.UvdBootLevel =
2291 0 : (uint8_t) (table_info->mm_dep_table->count - 1);
2292 0 : mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
2293 : UvdBootLevel);
2294 0 : mm_boot_level_offset /= 4;
2295 0 : mm_boot_level_offset *= 4;
2296 0 : mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2297 : CGS_IND_REG__SMC, mm_boot_level_offset);
2298 0 : mm_boot_level_value &= 0x00FFFFFF;
2299 0 : mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2300 0 : cgs_write_ind_register(hwmgr->device,
2301 : CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2302 :
2303 0 : if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2304 0 : PHM_PlatformCaps_UVDDPM) ||
2305 0 : phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2306 : PHM_PlatformCaps_StablePState))
2307 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2308 : PPSMC_MSG_UVDDPM_SetEnabledMask,
2309 0 : (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2310 : NULL);
2311 0 : return 0;
2312 : }
2313 :
2314 0 : static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2315 : {
2316 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2317 : uint32_t mm_boot_level_offset, mm_boot_level_value;
2318 0 : struct phm_ppt_v1_information *table_info =
2319 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
2320 :
2321 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2322 : PHM_PlatformCaps_StablePState))
2323 0 : smu_data->smc_state_table.VceBootLevel =
2324 0 : (uint8_t) (table_info->mm_dep_table->count - 1);
2325 : else
2326 0 : smu_data->smc_state_table.VceBootLevel = 0;
2327 :
2328 0 : mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2329 : offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2330 0 : mm_boot_level_offset /= 4;
2331 0 : mm_boot_level_offset *= 4;
2332 0 : mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2333 : CGS_IND_REG__SMC, mm_boot_level_offset);
2334 0 : mm_boot_level_value &= 0xFF00FFFF;
2335 0 : mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2336 0 : cgs_write_ind_register(hwmgr->device,
2337 : CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2338 :
2339 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2340 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
2341 : PPSMC_MSG_VCEDPM_SetEnabledMask,
2342 0 : (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
2343 : NULL);
2344 0 : return 0;
2345 : }
2346 :
2347 : static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2348 : {
2349 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2350 0 : struct phm_ppt_v1_information *table_info =
2351 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
2352 0 : struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2353 : int max_entry, i;
2354 :
2355 0 : max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
2356 0 : SMU74_MAX_LEVELS_LINK :
2357 0 : pcie_table->count;
2358 : /* Setup BIF_SCLK levels */
2359 0 : for (i = 0; i < max_entry; i++)
2360 0 : smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
2361 : return 0;
2362 : }
2363 :
2364 0 : static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2365 : {
2366 0 : switch (type) {
2367 : case SMU_UVD_TABLE:
2368 0 : polaris10_update_uvd_smc_table(hwmgr);
2369 0 : break;
2370 : case SMU_VCE_TABLE:
2371 0 : polaris10_update_vce_smc_table(hwmgr);
2372 0 : break;
2373 : case SMU_BIF_TABLE:
2374 0 : polaris10_update_bif_smc_table(hwmgr);
2375 : break;
2376 : default:
2377 : break;
2378 : }
2379 0 : return 0;
2380 : }
2381 :
2382 0 : static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2383 : {
2384 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2385 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2386 :
2387 0 : int result = 0;
2388 0 : uint32_t low_sclk_interrupt_threshold = 0;
2389 :
2390 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2391 : PHM_PlatformCaps_SclkThrottleLowNotification)
2392 0 : && (data->low_sclk_interrupt_threshold != 0)) {
2393 : low_sclk_interrupt_threshold =
2394 : data->low_sclk_interrupt_threshold;
2395 :
2396 0 : CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2397 :
2398 0 : result = smu7_copy_bytes_to_smc(
2399 : hwmgr,
2400 0 : smu_data->smu7_data.dpm_table_start +
2401 : offsetof(SMU74_Discrete_DpmTable,
2402 : LowSclkInterruptThreshold),
2403 : (uint8_t *)&low_sclk_interrupt_threshold,
2404 : sizeof(uint32_t),
2405 : SMC_RAM_END);
2406 : }
2407 0 : PP_ASSERT_WITH_CODE((result == 0),
2408 : "Failed to update SCLK threshold!", return result);
2409 :
2410 0 : result = polaris10_program_mem_timing_parameters(hwmgr);
2411 0 : PP_ASSERT_WITH_CODE((result == 0),
2412 : "Failed to program memory timing parameters!",
2413 : );
2414 :
2415 : return result;
2416 : }
2417 :
2418 0 : static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2419 : {
2420 0 : switch (type) {
2421 : case SMU_SoftRegisters:
2422 0 : switch (member) {
2423 : case HandshakeDisables:
2424 : return offsetof(SMU74_SoftRegisters, HandshakeDisables);
2425 : case VoltageChangeTimeout:
2426 0 : return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
2427 : case AverageGraphicsActivity:
2428 0 : return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
2429 : case AverageMemoryActivity:
2430 0 : return offsetof(SMU74_SoftRegisters, AverageMemoryActivity);
2431 : case PreVBlankGap:
2432 0 : return offsetof(SMU74_SoftRegisters, PreVBlankGap);
2433 : case VBlankTimeout:
2434 0 : return offsetof(SMU74_SoftRegisters, VBlankTimeout);
2435 : case UcodeLoadStatus:
2436 0 : return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
2437 : case DRAM_LOG_ADDR_H:
2438 0 : return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
2439 : case DRAM_LOG_ADDR_L:
2440 0 : return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
2441 : case DRAM_LOG_PHY_ADDR_H:
2442 0 : return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2443 : case DRAM_LOG_PHY_ADDR_L:
2444 0 : return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2445 : case DRAM_LOG_BUFF_SIZE:
2446 0 : return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2447 : }
2448 : break;
2449 : case SMU_Discrete_DpmTable:
2450 0 : switch (member) {
2451 : case UvdBootLevel:
2452 : return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2453 : case VceBootLevel:
2454 0 : return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2455 : case LowSclkInterruptThreshold:
2456 0 : return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
2457 : }
2458 : break;
2459 : }
2460 0 : pr_warn("can't get the offset of type %x member %x\n", type, member);
2461 0 : return 0;
2462 : }
2463 :
2464 0 : static uint32_t polaris10_get_mac_definition(uint32_t value)
2465 : {
2466 0 : switch (value) {
2467 : case SMU_MAX_LEVELS_GRAPHICS:
2468 : return SMU74_MAX_LEVELS_GRAPHICS;
2469 : case SMU_MAX_LEVELS_MEMORY:
2470 0 : return SMU74_MAX_LEVELS_MEMORY;
2471 : case SMU_MAX_LEVELS_LINK:
2472 : return SMU74_MAX_LEVELS_LINK;
2473 : case SMU_MAX_ENTRIES_SMIO:
2474 0 : return SMU74_MAX_ENTRIES_SMIO;
2475 : case SMU_MAX_LEVELS_VDDC:
2476 0 : return SMU74_MAX_LEVELS_VDDC;
2477 : case SMU_MAX_LEVELS_VDDGFX:
2478 0 : return SMU74_MAX_LEVELS_VDDGFX;
2479 : case SMU_MAX_LEVELS_VDDCI:
2480 : return SMU74_MAX_LEVELS_VDDCI;
2481 : case SMU_MAX_LEVELS_MVDD:
2482 0 : return SMU74_MAX_LEVELS_MVDD;
2483 : case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
2484 0 : return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
2485 : SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
2486 : }
2487 :
2488 0 : pr_warn("can't get the mac of %x\n", value);
2489 0 : return 0;
2490 : }
2491 :
2492 0 : static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2493 : {
2494 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2495 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2496 : uint32_t tmp;
2497 : int result;
2498 0 : bool error = false;
2499 :
2500 0 : result = smu7_read_smc_sram_dword(hwmgr,
2501 : SMU7_FIRMWARE_HEADER_LOCATION +
2502 : offsetof(SMU74_Firmware_Header, DpmTable),
2503 : &tmp, SMC_RAM_END);
2504 :
2505 0 : if (0 == result)
2506 0 : smu_data->smu7_data.dpm_table_start = tmp;
2507 :
2508 0 : error |= (0 != result);
2509 :
2510 0 : result = smu7_read_smc_sram_dword(hwmgr,
2511 : SMU7_FIRMWARE_HEADER_LOCATION +
2512 : offsetof(SMU74_Firmware_Header, SoftRegisters),
2513 : &tmp, SMC_RAM_END);
2514 :
2515 0 : if (!result) {
2516 0 : data->soft_regs_start = tmp;
2517 0 : smu_data->smu7_data.soft_regs_start = tmp;
2518 : }
2519 :
2520 0 : error |= (0 != result);
2521 :
2522 0 : result = smu7_read_smc_sram_dword(hwmgr,
2523 : SMU7_FIRMWARE_HEADER_LOCATION +
2524 : offsetof(SMU74_Firmware_Header, mcRegisterTable),
2525 : &tmp, SMC_RAM_END);
2526 :
2527 0 : if (!result)
2528 0 : smu_data->smu7_data.mc_reg_table_start = tmp;
2529 :
2530 0 : result = smu7_read_smc_sram_dword(hwmgr,
2531 : SMU7_FIRMWARE_HEADER_LOCATION +
2532 : offsetof(SMU74_Firmware_Header, FanTable),
2533 : &tmp, SMC_RAM_END);
2534 :
2535 0 : if (!result)
2536 0 : smu_data->smu7_data.fan_table_start = tmp;
2537 :
2538 0 : error |= (0 != result);
2539 :
2540 0 : result = smu7_read_smc_sram_dword(hwmgr,
2541 : SMU7_FIRMWARE_HEADER_LOCATION +
2542 : offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
2543 : &tmp, SMC_RAM_END);
2544 :
2545 0 : if (!result)
2546 0 : smu_data->smu7_data.arb_table_start = tmp;
2547 :
2548 0 : error |= (0 != result);
2549 :
2550 0 : result = smu7_read_smc_sram_dword(hwmgr,
2551 : SMU7_FIRMWARE_HEADER_LOCATION +
2552 : offsetof(SMU74_Firmware_Header, Version),
2553 : &tmp, SMC_RAM_END);
2554 :
2555 0 : if (!result)
2556 0 : hwmgr->microcode_version_info.SMC = tmp;
2557 :
2558 0 : error |= (0 != result);
2559 :
2560 0 : return error ? -1 : 0;
2561 : }
2562 :
2563 : static uint8_t polaris10_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2564 : {
2565 0 : return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2566 : }
2567 :
2568 0 : static int polaris10_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2569 : {
2570 : int result;
2571 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2572 0 : pp_atomctrl_mc_reg_table *mc_reg_table = &smu_data->mc_reg_table;
2573 0 : uint8_t module_index = polaris10_get_memory_modile_index(hwmgr);
2574 :
2575 0 : memset(mc_reg_table, 0, sizeof(pp_atomctrl_mc_reg_table));
2576 0 : result = atomctrl_initialize_mc_reg_table_v2_2(hwmgr, module_index, mc_reg_table);
2577 :
2578 0 : return result;
2579 : }
2580 :
2581 0 : static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2582 : {
2583 0 : return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2584 : CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2585 0 : ? true : false;
2586 : }
2587 :
2588 0 : static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
2589 : void *profile_setting)
2590 : {
2591 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2592 0 : struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2593 : (hwmgr->smu_backend);
2594 : struct profile_mode_setting *setting;
2595 0 : struct SMU74_Discrete_GraphicsLevel *levels =
2596 : smu_data->smc_state_table.GraphicsLevel;
2597 0 : uint32_t array = smu_data->smu7_data.dpm_table_start +
2598 : offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
2599 :
2600 0 : uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2601 : offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
2602 0 : struct SMU74_Discrete_MemoryLevel *mclk_levels =
2603 : smu_data->smc_state_table.MemoryLevel;
2604 : uint32_t i;
2605 : uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2606 :
2607 0 : if (profile_setting == NULL)
2608 : return -EINVAL;
2609 :
2610 0 : setting = (struct profile_mode_setting *)profile_setting;
2611 :
2612 0 : if (setting->bupdate_sclk) {
2613 0 : if (!data->sclk_dpm_key_disabled)
2614 0 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
2615 0 : for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2616 0 : if (levels[i].ActivityLevel !=
2617 0 : cpu_to_be16(setting->sclk_activity)) {
2618 0 : levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2619 :
2620 0 : clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2621 : + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
2622 0 : offset = clk_activity_offset & ~0x3;
2623 0 : tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2624 0 : tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2625 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2626 :
2627 : }
2628 0 : if (levels[i].UpHyst != setting->sclk_up_hyst ||
2629 0 : levels[i].DownHyst != setting->sclk_down_hyst) {
2630 0 : levels[i].UpHyst = setting->sclk_up_hyst;
2631 0 : levels[i].DownHyst = setting->sclk_down_hyst;
2632 0 : up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2633 : + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
2634 0 : down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2635 : + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
2636 0 : offset = up_hyst_offset & ~0x3;
2637 0 : tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2638 0 : tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2639 0 : tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2640 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2641 : }
2642 : }
2643 0 : if (!data->sclk_dpm_key_disabled)
2644 0 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
2645 : }
2646 :
2647 0 : if (setting->bupdate_mclk) {
2648 0 : if (!data->mclk_dpm_key_disabled)
2649 0 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
2650 0 : for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2651 0 : if (mclk_levels[i].ActivityLevel !=
2652 0 : cpu_to_be16(setting->mclk_activity)) {
2653 0 : mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2654 :
2655 0 : clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2656 : + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
2657 0 : offset = clk_activity_offset & ~0x3;
2658 0 : tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2659 0 : tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2660 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2661 :
2662 : }
2663 0 : if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2664 0 : mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2665 0 : mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2666 0 : mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2667 0 : up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2668 : + offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
2669 0 : down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2670 : + offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
2671 0 : offset = up_hyst_offset & ~0x3;
2672 0 : tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2673 0 : tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2674 0 : tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2675 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2676 : }
2677 : }
2678 0 : if (!data->mclk_dpm_key_disabled)
2679 0 : smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);
2680 : }
2681 : return 0;
2682 : }
2683 :
2684 : const struct pp_smumgr_func polaris10_smu_funcs = {
2685 : .name = "polaris10_smu",
2686 : .smu_init = polaris10_smu_init,
2687 : .smu_fini = smu7_smu_fini,
2688 : .start_smu = polaris10_start_smu,
2689 : .check_fw_load_finish = smu7_check_fw_load_finish,
2690 : .request_smu_load_fw = smu7_reload_firmware,
2691 : .request_smu_load_specific_fw = NULL,
2692 : .send_msg_to_smc = smu7_send_msg_to_smc,
2693 : .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2694 : .get_argument = smu7_get_argument,
2695 : .download_pptable_settings = NULL,
2696 : .upload_pptable_settings = NULL,
2697 : .update_smc_table = polaris10_update_smc_table,
2698 : .get_offsetof = polaris10_get_offsetof,
2699 : .process_firmware_header = polaris10_process_firmware_header,
2700 : .init_smc_table = polaris10_init_smc_table,
2701 : .update_sclk_threshold = polaris10_update_sclk_threshold,
2702 : .thermal_avfs_enable = polaris10_thermal_avfs_enable,
2703 : .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
2704 : .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
2705 : .populate_all_memory_levels = polaris10_populate_all_memory_levels,
2706 : .get_mac_definition = polaris10_get_mac_definition,
2707 : .initialize_mc_reg_table = polaris10_initialize_mc_reg_table,
2708 : .is_dpm_running = polaris10_is_dpm_running,
2709 : .is_hw_avfs_present = polaris10_is_hw_avfs_present,
2710 : .update_dpm_settings = polaris10_update_dpm_settings,
2711 : };
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