Line data Source code
1 : /*
2 : * Copyright 2017 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include "pp_debug.h"
24 : #include "smumgr.h"
25 : #include "smu_ucode_xfer_vi.h"
26 : #include "vegam_smumgr.h"
27 : #include "smu/smu_7_1_3_d.h"
28 : #include "smu/smu_7_1_3_sh_mask.h"
29 : #include "gmc/gmc_8_1_d.h"
30 : #include "gmc/gmc_8_1_sh_mask.h"
31 : #include "oss/oss_3_0_d.h"
32 : #include "gca/gfx_8_0_d.h"
33 : #include "bif/bif_5_0_d.h"
34 : #include "bif/bif_5_0_sh_mask.h"
35 : #include "ppatomctrl.h"
36 : #include "cgs_common.h"
37 : #include "smu7_ppsmc.h"
38 :
39 : #include "smu7_dyn_defaults.h"
40 :
41 : #include "smu7_hwmgr.h"
42 : #include "hardwaremanager.h"
43 : #include "atombios.h"
44 : #include "pppcielanes.h"
45 :
46 : #include "dce/dce_11_2_d.h"
47 : #include "dce/dce_11_2_sh_mask.h"
48 :
49 : #define PPVEGAM_TARGETACTIVITY_DFLT 50
50 :
51 : #define VOLTAGE_VID_OFFSET_SCALE1 625
52 : #define VOLTAGE_VID_OFFSET_SCALE2 100
53 : #define POWERTUNE_DEFAULT_SET_MAX 1
54 : #define VDDC_VDDCI_DELTA 200
55 : #define MC_CG_ARB_FREQ_F1 0x0b
56 :
57 : #define STRAP_ASIC_RO_LSB 2168
58 : #define STRAP_ASIC_RO_MSB 2175
59 :
60 : #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
61 : #define PPSMC_MSG_EnableModeSwitchRLCNotification ((uint16_t) 0x305)
62 :
63 : static const struct vegam_pt_defaults
64 : vegam_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
65 : /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
66 : * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
67 : { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
68 : { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
69 : { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
70 : };
71 :
72 : static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
73 : {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
74 : {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
75 : {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
76 : {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
77 : {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
78 : {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
79 : {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
80 : {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
81 :
82 0 : static int vegam_smu_init(struct pp_hwmgr *hwmgr)
83 : {
84 : struct vegam_smumgr *smu_data;
85 :
86 0 : smu_data = kzalloc(sizeof(struct vegam_smumgr), GFP_KERNEL);
87 0 : if (smu_data == NULL)
88 : return -ENOMEM;
89 :
90 0 : hwmgr->smu_backend = smu_data;
91 :
92 0 : if (smu7_init(hwmgr)) {
93 0 : kfree(smu_data);
94 0 : return -EINVAL;
95 : }
96 :
97 : return 0;
98 : }
99 :
100 0 : static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
101 : {
102 0 : int result = 0;
103 :
104 : /* Wait for smc boot up */
105 : /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
106 :
107 : /* Assert reset */
108 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
109 : SMC_SYSCON_RESET_CNTL, rst_reg, 1);
110 :
111 0 : result = smu7_upload_smu_firmware_image(hwmgr);
112 0 : if (result != 0)
113 : return result;
114 :
115 : /* Clear status */
116 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
117 :
118 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
119 : SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
120 :
121 : /* De-assert reset */
122 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
123 : SMC_SYSCON_RESET_CNTL, rst_reg, 0);
124 :
125 :
126 0 : PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
127 :
128 :
129 : /* Call Test SMU message with 0x20000 offset to trigger SMU start */
130 0 : smu7_send_msg_to_smc_offset(hwmgr);
131 :
132 : /* Wait done bit to be set */
133 : /* Check pass/failed indicator */
134 :
135 0 : PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
136 :
137 0 : if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
138 : SMU_STATUS, SMU_PASS))
139 0 : PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
140 :
141 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
142 :
143 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
144 : SMC_SYSCON_RESET_CNTL, rst_reg, 1);
145 :
146 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
147 : SMC_SYSCON_RESET_CNTL, rst_reg, 0);
148 :
149 : /* Wait for firmware to initialize */
150 0 : PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
151 :
152 0 : return result;
153 : }
154 :
155 0 : static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
156 : {
157 0 : int result = 0;
158 :
159 : /* wait for smc boot up */
160 0 : PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
161 :
162 : /* Clear firmware interrupt enable flag */
163 : /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
164 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
165 : ixFIRMWARE_FLAGS, 0);
166 :
167 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
168 : SMC_SYSCON_RESET_CNTL,
169 : rst_reg, 1);
170 :
171 0 : result = smu7_upload_smu_firmware_image(hwmgr);
172 0 : if (result != 0)
173 : return result;
174 :
175 : /* Set smc instruct start point at 0x0 */
176 0 : smu7_program_jump_on_start(hwmgr);
177 :
178 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
179 : SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
180 :
181 0 : PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
182 : SMC_SYSCON_RESET_CNTL, rst_reg, 0);
183 :
184 : /* Wait for firmware to initialize */
185 :
186 0 : PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
187 : FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
188 :
189 0 : return result;
190 : }
191 :
192 0 : static int vegam_start_smu(struct pp_hwmgr *hwmgr)
193 : {
194 0 : int result = 0;
195 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
196 :
197 : /* Only start SMC if SMC RAM is not running */
198 0 : if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
199 0 : smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
200 : CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
201 0 : smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
202 : hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
203 :
204 : /* Check if SMU is running in protected mode */
205 0 : if (smu_data->protected_mode == 0)
206 0 : result = vegam_start_smu_in_non_protection_mode(hwmgr);
207 : else
208 0 : result = vegam_start_smu_in_protection_mode(hwmgr);
209 :
210 0 : if (result != 0)
211 0 : PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
212 : }
213 :
214 : /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
215 0 : smu7_read_smc_sram_dword(hwmgr,
216 : SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU75_Firmware_Header, SoftRegisters),
217 : &(smu_data->smu7_data.soft_regs_start),
218 : 0x40000);
219 :
220 0 : result = smu7_request_smu_load_fw(hwmgr);
221 :
222 0 : return result;
223 : }
224 :
225 0 : static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr)
226 : {
227 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
228 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
229 : uint32_t tmp;
230 : int result;
231 0 : bool error = false;
232 :
233 0 : result = smu7_read_smc_sram_dword(hwmgr,
234 : SMU7_FIRMWARE_HEADER_LOCATION +
235 : offsetof(SMU75_Firmware_Header, DpmTable),
236 : &tmp, SMC_RAM_END);
237 :
238 0 : if (0 == result)
239 0 : smu_data->smu7_data.dpm_table_start = tmp;
240 :
241 0 : error |= (0 != result);
242 :
243 0 : result = smu7_read_smc_sram_dword(hwmgr,
244 : SMU7_FIRMWARE_HEADER_LOCATION +
245 : offsetof(SMU75_Firmware_Header, SoftRegisters),
246 : &tmp, SMC_RAM_END);
247 :
248 0 : if (!result) {
249 0 : data->soft_regs_start = tmp;
250 0 : smu_data->smu7_data.soft_regs_start = tmp;
251 : }
252 :
253 0 : error |= (0 != result);
254 :
255 0 : result = smu7_read_smc_sram_dword(hwmgr,
256 : SMU7_FIRMWARE_HEADER_LOCATION +
257 : offsetof(SMU75_Firmware_Header, mcRegisterTable),
258 : &tmp, SMC_RAM_END);
259 :
260 0 : if (!result)
261 0 : smu_data->smu7_data.mc_reg_table_start = tmp;
262 :
263 0 : result = smu7_read_smc_sram_dword(hwmgr,
264 : SMU7_FIRMWARE_HEADER_LOCATION +
265 : offsetof(SMU75_Firmware_Header, FanTable),
266 : &tmp, SMC_RAM_END);
267 :
268 0 : if (!result)
269 0 : smu_data->smu7_data.fan_table_start = tmp;
270 :
271 0 : error |= (0 != result);
272 :
273 0 : result = smu7_read_smc_sram_dword(hwmgr,
274 : SMU7_FIRMWARE_HEADER_LOCATION +
275 : offsetof(SMU75_Firmware_Header, mcArbDramTimingTable),
276 : &tmp, SMC_RAM_END);
277 :
278 0 : if (!result)
279 0 : smu_data->smu7_data.arb_table_start = tmp;
280 :
281 0 : error |= (0 != result);
282 :
283 0 : result = smu7_read_smc_sram_dword(hwmgr,
284 : SMU7_FIRMWARE_HEADER_LOCATION +
285 : offsetof(SMU75_Firmware_Header, Version),
286 : &tmp, SMC_RAM_END);
287 :
288 0 : if (!result)
289 0 : hwmgr->microcode_version_info.SMC = tmp;
290 :
291 0 : error |= (0 != result);
292 :
293 0 : return error ? -1 : 0;
294 : }
295 :
296 0 : static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
297 : {
298 0 : return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
299 : CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
300 0 : ? true : false;
301 : }
302 :
303 0 : static uint32_t vegam_get_mac_definition(uint32_t value)
304 : {
305 0 : switch (value) {
306 : case SMU_MAX_LEVELS_GRAPHICS:
307 : return SMU75_MAX_LEVELS_GRAPHICS;
308 : case SMU_MAX_LEVELS_MEMORY:
309 0 : return SMU75_MAX_LEVELS_MEMORY;
310 : case SMU_MAX_LEVELS_LINK:
311 : return SMU75_MAX_LEVELS_LINK;
312 : case SMU_MAX_ENTRIES_SMIO:
313 0 : return SMU75_MAX_ENTRIES_SMIO;
314 : case SMU_MAX_LEVELS_VDDC:
315 0 : return SMU75_MAX_LEVELS_VDDC;
316 : case SMU_MAX_LEVELS_VDDGFX:
317 0 : return SMU75_MAX_LEVELS_VDDGFX;
318 : case SMU_MAX_LEVELS_VDDCI:
319 : return SMU75_MAX_LEVELS_VDDCI;
320 : case SMU_MAX_LEVELS_MVDD:
321 0 : return SMU75_MAX_LEVELS_MVDD;
322 : case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
323 0 : return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
324 : SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
325 : }
326 :
327 0 : pr_warn("can't get the mac of %x\n", value);
328 0 : return 0;
329 : }
330 :
331 0 : static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
332 : {
333 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
334 : uint32_t mm_boot_level_offset, mm_boot_level_value;
335 0 : struct phm_ppt_v1_information *table_info =
336 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
337 :
338 0 : smu_data->smc_state_table.UvdBootLevel = 0;
339 0 : if (table_info->mm_dep_table->count > 0)
340 0 : smu_data->smc_state_table.UvdBootLevel =
341 0 : (uint8_t) (table_info->mm_dep_table->count - 1);
342 0 : mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
343 : UvdBootLevel);
344 0 : mm_boot_level_offset /= 4;
345 0 : mm_boot_level_offset *= 4;
346 0 : mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
347 : CGS_IND_REG__SMC, mm_boot_level_offset);
348 0 : mm_boot_level_value &= 0x00FFFFFF;
349 0 : mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
350 0 : cgs_write_ind_register(hwmgr->device,
351 : CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
352 :
353 0 : if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
354 0 : PHM_PlatformCaps_UVDDPM) ||
355 0 : phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
356 : PHM_PlatformCaps_StablePState))
357 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
358 : PPSMC_MSG_UVDDPM_SetEnabledMask,
359 0 : (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
360 : NULL);
361 0 : return 0;
362 : }
363 :
364 0 : static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
365 : {
366 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
367 : uint32_t mm_boot_level_offset, mm_boot_level_value;
368 0 : struct phm_ppt_v1_information *table_info =
369 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
370 :
371 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
372 : PHM_PlatformCaps_StablePState))
373 0 : smu_data->smc_state_table.VceBootLevel =
374 0 : (uint8_t) (table_info->mm_dep_table->count - 1);
375 : else
376 0 : smu_data->smc_state_table.VceBootLevel = 0;
377 :
378 0 : mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
379 : offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
380 0 : mm_boot_level_offset /= 4;
381 0 : mm_boot_level_offset *= 4;
382 0 : mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
383 : CGS_IND_REG__SMC, mm_boot_level_offset);
384 0 : mm_boot_level_value &= 0xFF00FFFF;
385 0 : mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
386 0 : cgs_write_ind_register(hwmgr->device,
387 : CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
388 :
389 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
390 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
391 : PPSMC_MSG_VCEDPM_SetEnabledMask,
392 0 : (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
393 : NULL);
394 0 : return 0;
395 : }
396 :
397 : static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
398 : {
399 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
400 0 : struct phm_ppt_v1_information *table_info =
401 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
402 0 : struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
403 : int max_entry, i;
404 :
405 0 : max_entry = (SMU75_MAX_LEVELS_LINK < pcie_table->count) ?
406 0 : SMU75_MAX_LEVELS_LINK :
407 0 : pcie_table->count;
408 : /* Setup BIF_SCLK levels */
409 0 : for (i = 0; i < max_entry; i++)
410 0 : smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
411 : return 0;
412 : }
413 :
414 0 : static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
415 : {
416 0 : switch (type) {
417 : case SMU_UVD_TABLE:
418 0 : vegam_update_uvd_smc_table(hwmgr);
419 0 : break;
420 : case SMU_VCE_TABLE:
421 0 : vegam_update_vce_smc_table(hwmgr);
422 0 : break;
423 : case SMU_BIF_TABLE:
424 0 : vegam_update_bif_smc_table(hwmgr);
425 : break;
426 : default:
427 : break;
428 : }
429 0 : return 0;
430 : }
431 :
432 : static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
433 : {
434 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
435 0 : struct phm_ppt_v1_information *table_info =
436 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
437 :
438 0 : if (table_info &&
439 0 : table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
440 : table_info->cac_dtp_table->usPowerTuneDataSetID)
441 0 : smu_data->power_tune_defaults =
442 0 : &vegam_power_tune_data_set_array
443 0 : [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
444 : else
445 0 : smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0];
446 :
447 : }
448 :
449 0 : static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
450 : SMU75_Discrete_DpmTable *table)
451 : {
452 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
453 : uint32_t count, level;
454 :
455 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
456 0 : count = data->mvdd_voltage_table.count;
457 0 : if (count > SMU_MAX_SMIO_LEVELS)
458 0 : count = SMU_MAX_SMIO_LEVELS;
459 0 : for (level = 0; level < count; level++) {
460 0 : table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
461 : data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
462 : /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
463 0 : table->SmioTable2.Pattern[level].Smio =
464 0 : (uint8_t) level;
465 0 : table->Smio[level] |=
466 0 : data->mvdd_voltage_table.entries[level].smio_low;
467 : }
468 0 : table->SmioMask2 = data->mvdd_voltage_table.mask_low;
469 :
470 0 : table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
471 : }
472 :
473 0 : return 0;
474 : }
475 :
476 0 : static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
477 : struct SMU75_Discrete_DpmTable *table)
478 : {
479 : uint32_t count, level;
480 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
481 :
482 0 : count = data->vddci_voltage_table.count;
483 :
484 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
485 0 : if (count > SMU_MAX_SMIO_LEVELS)
486 0 : count = SMU_MAX_SMIO_LEVELS;
487 0 : for (level = 0; level < count; ++level) {
488 0 : table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
489 : data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
490 0 : table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
491 :
492 0 : table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
493 : }
494 : }
495 :
496 0 : table->SmioMask1 = data->vddci_voltage_table.mask_low;
497 :
498 0 : return 0;
499 : }
500 :
501 0 : static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr,
502 : struct SMU75_Discrete_DpmTable *table)
503 : {
504 : uint32_t count;
505 : uint8_t index;
506 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
507 0 : struct phm_ppt_v1_information *table_info =
508 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
509 0 : struct phm_ppt_v1_voltage_lookup_table *lookup_table =
510 : table_info->vddc_lookup_table;
511 : /* tables is already swapped, so in order to use the value from it,
512 : * we need to swap it back.
513 : * We are populating vddc CAC data to BapmVddc table
514 : * in split and merged mode
515 : */
516 0 : for (count = 0; count < lookup_table->count; count++) {
517 0 : index = phm_get_voltage_index(lookup_table,
518 0 : data->vddc_voltage_table.entries[count].value);
519 0 : table->BapmVddcVidLoSidd[count] =
520 0 : convert_to_vid(lookup_table->entries[index].us_cac_low);
521 0 : table->BapmVddcVidHiSidd[count] =
522 0 : convert_to_vid(lookup_table->entries[index].us_cac_mid);
523 0 : table->BapmVddcVidHiSidd2[count] =
524 0 : convert_to_vid(lookup_table->entries[index].us_cac_high);
525 : }
526 :
527 0 : return 0;
528 : }
529 :
530 0 : static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
531 : struct SMU75_Discrete_DpmTable *table)
532 : {
533 0 : vegam_populate_smc_vddci_table(hwmgr, table);
534 0 : vegam_populate_smc_mvdd_table(hwmgr, table);
535 0 : vegam_populate_cac_table(hwmgr, table);
536 :
537 0 : return 0;
538 : }
539 :
540 : static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr,
541 : struct SMU75_Discrete_Ulv *state)
542 : {
543 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
544 0 : struct phm_ppt_v1_information *table_info =
545 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
546 :
547 0 : state->CcPwrDynRm = 0;
548 0 : state->CcPwrDynRm1 = 0;
549 :
550 0 : state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
551 0 : state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
552 0 : VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
553 :
554 0 : state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
555 :
556 : CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
557 : CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
558 0 : CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
559 :
560 : return 0;
561 : }
562 :
563 : static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr,
564 : struct SMU75_Discrete_DpmTable *table)
565 : {
566 0 : return vegam_populate_ulv_level(hwmgr, &table->Ulv);
567 : }
568 :
569 0 : static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr,
570 : struct SMU75_Discrete_DpmTable *table)
571 : {
572 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
573 0 : struct vegam_smumgr *smu_data =
574 : (struct vegam_smumgr *)(hwmgr->smu_backend);
575 0 : struct smu7_dpm_table *dpm_table = &data->dpm_table;
576 : int i;
577 :
578 : /* Index (dpm_table->pcie_speed_table.count)
579 : * is reserved for PCIE boot level. */
580 0 : for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
581 0 : table->LinkLevel[i].PcieGenSpeed =
582 0 : (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
583 0 : table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
584 : dpm_table->pcie_speed_table.dpm_levels[i].param1);
585 0 : table->LinkLevel[i].EnabledForActivity = 1;
586 0 : table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
587 0 : table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
588 0 : table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
589 : }
590 :
591 0 : smu_data->smc_state_table.LinkLevelCount =
592 0 : (uint8_t)dpm_table->pcie_speed_table.count;
593 :
594 : /* To Do move to hwmgr */
595 0 : data->dpm_level_enable_mask.pcie_dpm_enable_mask =
596 0 : phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
597 :
598 0 : return 0;
599 : }
600 :
601 0 : static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
602 : struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
603 : uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
604 : {
605 : uint32_t i;
606 : uint16_t vddci;
607 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
608 :
609 0 : *voltage = *mvdd = 0;
610 :
611 : /* clock - voltage dependency table is empty table */
612 0 : if (dep_table->count == 0)
613 : return -EINVAL;
614 :
615 0 : for (i = 0; i < dep_table->count; i++) {
616 : /* find first sclk bigger than request */
617 0 : if (dep_table->entries[i].clk >= clock) {
618 0 : *voltage |= (dep_table->entries[i].vddc *
619 0 : VOLTAGE_SCALE) << VDDC_SHIFT;
620 0 : if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
621 0 : *voltage |= (data->vbios_boot_state.vddci_bootup_value *
622 0 : VOLTAGE_SCALE) << VDDCI_SHIFT;
623 0 : else if (dep_table->entries[i].vddci)
624 0 : *voltage |= (dep_table->entries[i].vddci *
625 0 : VOLTAGE_SCALE) << VDDCI_SHIFT;
626 : else {
627 0 : vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
628 0 : (dep_table->entries[i].vddc -
629 : (uint16_t)VDDC_VDDCI_DELTA));
630 0 : *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
631 : }
632 :
633 0 : if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
634 0 : *mvdd = data->vbios_boot_state.mvdd_bootup_value *
635 : VOLTAGE_SCALE;
636 0 : else if (dep_table->entries[i].mvdd)
637 0 : *mvdd = (uint32_t) dep_table->entries[i].mvdd *
638 : VOLTAGE_SCALE;
639 :
640 0 : *voltage |= 1 << PHASES_SHIFT;
641 : return 0;
642 : }
643 : }
644 :
645 : /* sclk is bigger than max sclk in the dependence table */
646 0 : *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
647 :
648 0 : if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
649 0 : *voltage |= (data->vbios_boot_state.vddci_bootup_value *
650 0 : VOLTAGE_SCALE) << VDDCI_SHIFT;
651 0 : else if (dep_table->entries[i - 1].vddci)
652 0 : *voltage |= (dep_table->entries[i - 1].vddci *
653 0 : VOLTAGE_SCALE) << VDDC_SHIFT;
654 : else {
655 0 : vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
656 0 : (dep_table->entries[i - 1].vddc -
657 : (uint16_t)VDDC_VDDCI_DELTA));
658 :
659 0 : *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
660 : }
661 :
662 0 : if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
663 0 : *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
664 0 : else if (dep_table->entries[i].mvdd)
665 0 : *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
666 :
667 : return 0;
668 : }
669 :
670 0 : static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr,
671 : SMU75_Discrete_DpmTable *table)
672 : {
673 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
674 : uint32_t i, ref_clk;
675 :
676 0 : struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
677 :
678 0 : ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
679 :
680 0 : if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
681 0 : for (i = 0; i < NUM_SCLK_RANGE; i++) {
682 0 : table->SclkFcwRangeTable[i].vco_setting =
683 0 : range_table_from_vbios.entry[i].ucVco_setting;
684 0 : table->SclkFcwRangeTable[i].postdiv =
685 0 : range_table_from_vbios.entry[i].ucPostdiv;
686 0 : table->SclkFcwRangeTable[i].fcw_pcc =
687 0 : range_table_from_vbios.entry[i].usFcw_pcc;
688 :
689 0 : table->SclkFcwRangeTable[i].fcw_trans_upper =
690 0 : range_table_from_vbios.entry[i].usFcw_trans_upper;
691 0 : table->SclkFcwRangeTable[i].fcw_trans_lower =
692 0 : range_table_from_vbios.entry[i].usRcw_trans_lower;
693 :
694 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
695 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
696 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
697 : }
698 0 : return;
699 : }
700 :
701 0 : for (i = 0; i < NUM_SCLK_RANGE; i++) {
702 0 : smu_data->range_table[i].trans_lower_frequency =
703 0 : (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
704 0 : smu_data->range_table[i].trans_upper_frequency =
705 0 : (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
706 :
707 0 : table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
708 0 : table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
709 0 : table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
710 :
711 0 : table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
712 0 : table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
713 :
714 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
715 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
716 0 : CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
717 : }
718 : }
719 :
720 0 : static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr,
721 : uint32_t clock, SMU_SclkSetting *sclk_setting)
722 : {
723 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
724 0 : const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
725 : struct pp_atomctrl_clock_dividers_ai dividers;
726 : uint32_t ref_clock;
727 : uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
728 : uint8_t i;
729 : int result;
730 : uint64_t temp;
731 :
732 0 : sclk_setting->SclkFrequency = clock;
733 : /* get the engine clock dividers for this clock value */
734 0 : result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
735 0 : if (result == 0) {
736 0 : sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
737 0 : sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
738 0 : sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
739 0 : sclk_setting->PllRange = dividers.ucSclkPllRange;
740 0 : sclk_setting->Sclk_slew_rate = 0x400;
741 0 : sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
742 0 : sclk_setting->Pcc_down_slew_rate = 0xffff;
743 0 : sclk_setting->SSc_En = dividers.ucSscEnable;
744 0 : sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
745 0 : sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
746 0 : sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
747 0 : return result;
748 : }
749 :
750 0 : ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
751 :
752 0 : for (i = 0; i < NUM_SCLK_RANGE; i++) {
753 0 : if (clock > smu_data->range_table[i].trans_lower_frequency
754 0 : && clock <= smu_data->range_table[i].trans_upper_frequency) {
755 0 : sclk_setting->PllRange = i;
756 0 : break;
757 : }
758 : }
759 :
760 0 : sclk_setting->Fcw_int = (uint16_t)
761 0 : ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
762 : ref_clock);
763 0 : temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
764 0 : temp <<= 0x10;
765 0 : do_div(temp, ref_clock);
766 0 : sclk_setting->Fcw_frac = temp & 0xffff;
767 :
768 0 : pcc_target_percent = 10; /* Hardcode 10% for now. */
769 0 : pcc_target_freq = clock - (clock * pcc_target_percent / 100);
770 0 : sclk_setting->Pcc_fcw_int = (uint16_t)
771 0 : ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
772 : ref_clock);
773 :
774 0 : ss_target_percent = 2; /* Hardcode 2% for now. */
775 : sclk_setting->SSc_En = 0;
776 : if (ss_target_percent) {
777 0 : sclk_setting->SSc_En = 1;
778 0 : ss_target_freq = clock - (clock * ss_target_percent / 100);
779 0 : sclk_setting->Fcw1_int = (uint16_t)
780 0 : ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
781 : ref_clock);
782 0 : temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
783 0 : temp <<= 0x10;
784 0 : do_div(temp, ref_clock);
785 0 : sclk_setting->Fcw1_frac = temp & 0xffff;
786 : }
787 :
788 0 : return 0;
789 : }
790 :
791 0 : static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,
792 : uint32_t clock_insr)
793 : {
794 : uint8_t i;
795 : uint32_t temp;
796 0 : uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
797 :
798 0 : PP_ASSERT_WITH_CODE((clock >= min),
799 : "Engine clock can't satisfy stutter requirement!",
800 : return 0);
801 0 : for (i = 31; ; i--) {
802 0 : temp = clock / (i + 1);
803 :
804 0 : if (temp >= min || i == 0)
805 : break;
806 : }
807 : return i;
808 : }
809 :
810 0 : static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
811 : uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)
812 : {
813 : int result;
814 : /* PP_Clocks minClocks; */
815 : uint32_t mvdd;
816 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
817 0 : struct phm_ppt_v1_information *table_info =
818 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
819 0 : SMU_SclkSetting curr_sclk_setting = { 0 };
820 :
821 0 : result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
822 :
823 : /* populate graphics levels */
824 0 : result = vegam_get_dependency_volt_by_clk(hwmgr,
825 : table_info->vdd_dep_on_sclk, clock,
826 : &level->MinVoltage, &mvdd);
827 :
828 0 : PP_ASSERT_WITH_CODE((0 == result),
829 : "can not find VDDC voltage value for "
830 : "VDDC engine clock dependency table",
831 : return result);
832 0 : level->ActivityLevel = (uint16_t)(SclkDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
833 :
834 0 : level->CcPwrDynRm = 0;
835 0 : level->CcPwrDynRm1 = 0;
836 0 : level->EnabledForActivity = 0;
837 0 : level->EnabledForThrottle = 1;
838 0 : level->VoltageDownHyst = 0;
839 0 : level->PowerThrottle = 0;
840 0 : data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
841 :
842 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
843 0 : level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock,
844 0 : hwmgr->display_config->min_core_set_clock_in_sr);
845 :
846 0 : level->SclkSetting = curr_sclk_setting;
847 :
848 0 : CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
849 0 : CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
850 0 : CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
851 0 : CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
852 0 : CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
853 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
854 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
855 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
856 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
857 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
858 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
859 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
860 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
861 0 : CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
862 0 : return 0;
863 : }
864 :
865 0 : static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
866 : {
867 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
868 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
869 0 : struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
870 0 : struct phm_ppt_v1_information *table_info =
871 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
872 0 : struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
873 0 : uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
874 0 : int result = 0;
875 0 : uint32_t array = smu_data->smu7_data.dpm_table_start +
876 : offsetof(SMU75_Discrete_DpmTable, GraphicsLevel);
877 0 : uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) *
878 : SMU75_MAX_LEVELS_GRAPHICS;
879 0 : struct SMU75_Discrete_GraphicsLevel *levels =
880 : smu_data->smc_state_table.GraphicsLevel;
881 : uint32_t i, max_entry;
882 0 : uint8_t hightest_pcie_level_enabled = 0,
883 0 : lowest_pcie_level_enabled = 0,
884 0 : mid_pcie_level_enabled = 0,
885 0 : count = 0;
886 :
887 0 : vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
888 :
889 0 : for (i = 0; i < dpm_table->sclk_table.count; i++) {
890 :
891 0 : result = vegam_populate_single_graphic_level(hwmgr,
892 : dpm_table->sclk_table.dpm_levels[i].value,
893 0 : &(smu_data->smc_state_table.GraphicsLevel[i]));
894 0 : if (result)
895 : return result;
896 :
897 0 : levels[i].UpHyst = (uint8_t)
898 : (SclkDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
899 0 : levels[i].DownHyst = (uint8_t)
900 : (SclkDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
901 : /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
902 0 : if (i > 1)
903 0 : levels[i].DeepSleepDivId = 0;
904 : }
905 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
906 : PHM_PlatformCaps_SPLLShutdownSupport))
907 0 : smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
908 :
909 0 : smu_data->smc_state_table.GraphicsDpmLevelCount =
910 0 : (uint8_t)dpm_table->sclk_table.count;
911 0 : hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
912 0 : phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
913 :
914 0 : for (i = 0; i < dpm_table->sclk_table.count; i++)
915 0 : levels[i].EnabledForActivity =
916 0 : (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
917 :
918 0 : if (pcie_table != NULL) {
919 0 : PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
920 : "There must be 1 or more PCIE levels defined in PPTable.",
921 : return -EINVAL);
922 0 : max_entry = pcie_entry_cnt - 1;
923 0 : for (i = 0; i < dpm_table->sclk_table.count; i++)
924 0 : levels[i].pcieDpmLevel =
925 0 : (uint8_t) ((i < max_entry) ? i : max_entry);
926 : } else {
927 0 : while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
928 0 : ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
929 0 : (1 << (hightest_pcie_level_enabled + 1))) != 0))
930 0 : hightest_pcie_level_enabled++;
931 :
932 0 : while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
933 0 : ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
934 0 : (1 << lowest_pcie_level_enabled)) == 0))
935 0 : lowest_pcie_level_enabled++;
936 :
937 0 : while ((count < hightest_pcie_level_enabled) &&
938 0 : ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
939 0 : (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
940 0 : count++;
941 :
942 0 : mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
943 : hightest_pcie_level_enabled ?
944 0 : (lowest_pcie_level_enabled + 1 + count) :
945 : hightest_pcie_level_enabled;
946 :
947 : /* set pcieDpmLevel to hightest_pcie_level_enabled */
948 0 : for (i = 2; i < dpm_table->sclk_table.count; i++)
949 0 : levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
950 :
951 : /* set pcieDpmLevel to lowest_pcie_level_enabled */
952 0 : levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
953 :
954 : /* set pcieDpmLevel to mid_pcie_level_enabled */
955 0 : levels[1].pcieDpmLevel = mid_pcie_level_enabled;
956 : }
957 : /* level count will send to smc once at init smc table and never change */
958 0 : result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
959 : (uint32_t)array_size, SMC_RAM_END);
960 :
961 0 : return result;
962 : }
963 :
964 0 : static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr,
965 : uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
966 : {
967 : struct pp_atomctrl_memory_clock_param_ai mpll_param;
968 :
969 0 : PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
970 : clock, &mpll_param),
971 : "Failed to retrieve memory pll parameter.",
972 : return -EINVAL);
973 :
974 0 : mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
975 0 : mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
976 0 : mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
977 0 : mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
978 :
979 0 : return 0;
980 : }
981 :
982 0 : static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr,
983 : uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
984 : {
985 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
986 0 : struct phm_ppt_v1_information *table_info =
987 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
988 0 : int result = 0;
989 0 : uint32_t mclk_stutter_mode_threshold = 60000;
990 :
991 :
992 0 : if (table_info->vdd_dep_on_mclk) {
993 0 : result = vegam_get_dependency_volt_by_clk(hwmgr,
994 : table_info->vdd_dep_on_mclk, clock,
995 : &mem_level->MinVoltage, &mem_level->MinMvdd);
996 0 : PP_ASSERT_WITH_CODE(!result,
997 : "can not find MinVddc voltage value from memory "
998 : "VDDC voltage dependency table", return result);
999 : }
1000 :
1001 0 : result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
1002 0 : PP_ASSERT_WITH_CODE(!result,
1003 : "Failed to calculate mclk params.",
1004 : return -EINVAL);
1005 :
1006 0 : mem_level->EnabledForThrottle = 1;
1007 0 : mem_level->EnabledForActivity = 0;
1008 0 : mem_level->VoltageDownHyst = 0;
1009 0 : mem_level->ActivityLevel = (uint16_t)
1010 : (MemoryDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
1011 0 : mem_level->StutterEnable = false;
1012 0 : mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1013 :
1014 0 : data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1015 0 : data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1016 :
1017 0 : if (mclk_stutter_mode_threshold &&
1018 0 : (clock <= mclk_stutter_mode_threshold) &&
1019 0 : (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1020 0 : STUTTER_ENABLE) & 0x1))
1021 0 : mem_level->StutterEnable = true;
1022 :
1023 : if (!result) {
1024 0 : CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1025 0 : CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1026 0 : CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_int);
1027 0 : CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_frac);
1028 0 : CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1029 0 : CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1030 : }
1031 :
1032 0 : return result;
1033 : }
1034 :
1035 0 : static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1036 : {
1037 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1038 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1039 0 : struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1040 : int result;
1041 : /* populate MCLK dpm table to SMU7 */
1042 0 : uint32_t array = smu_data->smu7_data.dpm_table_start +
1043 : offsetof(SMU75_Discrete_DpmTable, MemoryLevel);
1044 0 : uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) *
1045 : SMU75_MAX_LEVELS_MEMORY;
1046 0 : struct SMU75_Discrete_MemoryLevel *levels =
1047 : smu_data->smc_state_table.MemoryLevel;
1048 : uint32_t i;
1049 :
1050 0 : for (i = 0; i < dpm_table->mclk_table.count; i++) {
1051 0 : PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1052 : "can not populate memory level as memory clock is zero",
1053 : return -EINVAL);
1054 0 : result = vegam_populate_single_memory_level(hwmgr,
1055 : dpm_table->mclk_table.dpm_levels[i].value,
1056 0 : &levels[i]);
1057 :
1058 0 : if (result)
1059 : return result;
1060 :
1061 0 : levels[i].UpHyst = (uint8_t)
1062 : (MemoryDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
1063 0 : levels[i].DownHyst = (uint8_t)
1064 : (MemoryDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
1065 : }
1066 :
1067 0 : smu_data->smc_state_table.MemoryDpmLevelCount =
1068 0 : (uint8_t)dpm_table->mclk_table.count;
1069 0 : hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1070 0 : phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1071 :
1072 0 : for (i = 0; i < dpm_table->mclk_table.count; i++)
1073 0 : levels[i].EnabledForActivity =
1074 0 : (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1;
1075 :
1076 0 : levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
1077 : PPSMC_DISPLAY_WATERMARK_HIGH;
1078 :
1079 : /* level count will send to smc once at init smc table and never change */
1080 0 : result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1081 : (uint32_t)array_size, SMC_RAM_END);
1082 :
1083 0 : return result;
1084 : }
1085 :
1086 0 : static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1087 : uint32_t mclk, SMIO_Pattern *smio_pat)
1088 : {
1089 0 : const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1090 0 : struct phm_ppt_v1_information *table_info =
1091 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1092 0 : uint32_t i = 0;
1093 :
1094 0 : if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1095 : /* find mvdd value which clock is more than request */
1096 0 : for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1097 0 : if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1098 0 : smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1099 : break;
1100 : }
1101 : }
1102 0 : PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1103 : "MVDD Voltage is outside the supported range.",
1104 : return -EINVAL);
1105 : } else
1106 : return -EINVAL;
1107 :
1108 : return 0;
1109 : }
1110 :
1111 0 : static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1112 : SMU75_Discrete_DpmTable *table)
1113 : {
1114 0 : int result = 0;
1115 : uint32_t sclk_frequency;
1116 0 : const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1117 0 : struct phm_ppt_v1_information *table_info =
1118 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1119 : SMIO_Pattern vol_level;
1120 : uint32_t mvdd;
1121 :
1122 0 : table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1123 :
1124 : /* Get MinVoltage and Frequency from DPM0,
1125 : * already converted to SMC_UL */
1126 0 : sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1127 0 : result = vegam_get_dependency_volt_by_clk(hwmgr,
1128 : table_info->vdd_dep_on_sclk,
1129 : sclk_frequency,
1130 : &table->ACPILevel.MinVoltage, &mvdd);
1131 0 : PP_ASSERT_WITH_CODE(!result,
1132 : "Cannot find ACPI VDDC voltage value "
1133 : "in Clock Dependency Table",
1134 : );
1135 :
1136 0 : result = vegam_calculate_sclk_params(hwmgr, sclk_frequency,
1137 : &(table->ACPILevel.SclkSetting));
1138 0 : PP_ASSERT_WITH_CODE(!result,
1139 : "Error retrieving Engine Clock dividers from VBIOS.",
1140 : return result);
1141 :
1142 0 : table->ACPILevel.DeepSleepDivId = 0;
1143 0 : table->ACPILevel.CcPwrDynRm = 0;
1144 0 : table->ACPILevel.CcPwrDynRm1 = 0;
1145 :
1146 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1147 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1148 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1149 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1150 :
1151 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1152 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1153 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1154 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1155 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1156 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1157 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1158 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1159 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1160 0 : CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1161 :
1162 :
1163 : /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1164 0 : table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1165 0 : result = vegam_get_dependency_volt_by_clk(hwmgr,
1166 : table_info->vdd_dep_on_mclk,
1167 : table->MemoryACPILevel.MclkFrequency,
1168 : &table->MemoryACPILevel.MinVoltage, &mvdd);
1169 0 : PP_ASSERT_WITH_CODE((0 == result),
1170 : "Cannot find ACPI VDDCI voltage value "
1171 : "in Clock Dependency Table",
1172 : );
1173 :
1174 0 : if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
1175 0 : table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1176 : else
1177 0 : table->MemoryACPILevel.MinMvdd = 0;
1178 :
1179 0 : table->MemoryACPILevel.StutterEnable = false;
1180 :
1181 0 : table->MemoryACPILevel.EnabledForThrottle = 0;
1182 0 : table->MemoryACPILevel.EnabledForActivity = 0;
1183 0 : table->MemoryACPILevel.UpHyst = 0;
1184 0 : table->MemoryACPILevel.DownHyst = 100;
1185 0 : table->MemoryACPILevel.VoltageDownHyst = 0;
1186 0 : table->MemoryACPILevel.ActivityLevel =
1187 0 : PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1188 :
1189 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1190 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1191 :
1192 0 : return result;
1193 : }
1194 :
1195 0 : static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1196 : SMU75_Discrete_DpmTable *table)
1197 : {
1198 0 : int result = -EINVAL;
1199 : uint8_t count;
1200 : struct pp_atomctrl_clock_dividers_vi dividers;
1201 0 : struct phm_ppt_v1_information *table_info =
1202 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1203 0 : struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1204 : table_info->mm_dep_table;
1205 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1206 : uint32_t vddci;
1207 :
1208 0 : table->VceLevelCount = (uint8_t)(mm_table->count);
1209 0 : table->VceBootLevel = 0;
1210 :
1211 0 : for (count = 0; count < table->VceLevelCount; count++) {
1212 0 : table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1213 0 : table->VceLevel[count].MinVoltage = 0;
1214 0 : table->VceLevel[count].MinVoltage |=
1215 0 : (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1216 :
1217 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1218 0 : vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1219 0 : mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1220 0 : else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1221 0 : vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1222 : else
1223 0 : vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1224 :
1225 :
1226 0 : table->VceLevel[count].MinVoltage |=
1227 0 : (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1228 0 : table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1229 :
1230 : /*retrieve divider value for VBIOS */
1231 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1232 : table->VceLevel[count].Frequency, ÷rs);
1233 0 : PP_ASSERT_WITH_CODE((0 == result),
1234 : "can not find divide id for VCE engine clock",
1235 : return result);
1236 :
1237 0 : table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1238 :
1239 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1240 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1241 : }
1242 : return result;
1243 : }
1244 :
1245 0 : static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1246 : int32_t eng_clock, int32_t mem_clock,
1247 : SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs)
1248 : {
1249 : uint32_t dram_timing;
1250 : uint32_t dram_timing2;
1251 : uint32_t burst_time;
1252 : uint32_t rfsh_rate;
1253 : uint32_t misc3;
1254 :
1255 : int result;
1256 :
1257 0 : result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1258 : eng_clock, mem_clock);
1259 0 : PP_ASSERT_WITH_CODE(result == 0,
1260 : "Error calling VBIOS to set DRAM_TIMING.",
1261 : return result);
1262 :
1263 0 : dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1264 0 : dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1265 0 : burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
1266 0 : rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
1267 0 : misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
1268 :
1269 0 : arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1270 0 : arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1271 0 : arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time);
1272 0 : arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);
1273 0 : arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);
1274 :
1275 0 : return 0;
1276 : }
1277 :
1278 0 : static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1279 : {
1280 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1281 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1282 : struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
1283 : uint32_t i, j;
1284 0 : int result = 0;
1285 :
1286 0 : memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
1287 :
1288 0 : for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1289 0 : for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1290 0 : result = vegam_populate_memory_timing_parameters(hwmgr,
1291 0 : hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1292 0 : hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1293 : &arb_regs.entries[i][j]);
1294 0 : if (result)
1295 : return result;
1296 : }
1297 : }
1298 :
1299 0 : result = smu7_copy_bytes_to_smc(
1300 : hwmgr,
1301 : smu_data->smu7_data.arb_table_start,
1302 : (uint8_t *)&arb_regs,
1303 : sizeof(SMU75_Discrete_MCArbDramTimingTable),
1304 : SMC_RAM_END);
1305 0 : return result;
1306 : }
1307 :
1308 0 : static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1309 : struct SMU75_Discrete_DpmTable *table)
1310 : {
1311 0 : int result = -EINVAL;
1312 : uint8_t count;
1313 : struct pp_atomctrl_clock_dividers_vi dividers;
1314 0 : struct phm_ppt_v1_information *table_info =
1315 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1316 0 : struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1317 : table_info->mm_dep_table;
1318 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1319 : uint32_t vddci;
1320 :
1321 0 : table->UvdLevelCount = (uint8_t)(mm_table->count);
1322 0 : table->UvdBootLevel = 0;
1323 :
1324 0 : for (count = 0; count < table->UvdLevelCount; count++) {
1325 0 : table->UvdLevel[count].MinVoltage = 0;
1326 0 : table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1327 0 : table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1328 0 : table->UvdLevel[count].MinVoltage |=
1329 0 : (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1330 :
1331 0 : if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1332 0 : vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1333 0 : mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1334 0 : else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1335 0 : vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1336 : else
1337 0 : vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1338 :
1339 0 : table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1340 0 : table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1341 :
1342 : /* retrieve divider value for VBIOS */
1343 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1344 : table->UvdLevel[count].VclkFrequency, ÷rs);
1345 0 : PP_ASSERT_WITH_CODE((0 == result),
1346 : "can not find divide id for Vclk clock", return result);
1347 :
1348 0 : table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1349 :
1350 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1351 : table->UvdLevel[count].DclkFrequency, ÷rs);
1352 0 : PP_ASSERT_WITH_CODE((0 == result),
1353 : "can not find divide id for Dclk clock", return result);
1354 :
1355 0 : table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1356 :
1357 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1358 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1359 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1360 : }
1361 :
1362 : return result;
1363 : }
1364 :
1365 0 : static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1366 : struct SMU75_Discrete_DpmTable *table)
1367 : {
1368 0 : int result = 0;
1369 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1370 :
1371 0 : table->GraphicsBootLevel = 0;
1372 0 : table->MemoryBootLevel = 0;
1373 :
1374 : /* find boot level from dpm table */
1375 0 : result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1376 : data->vbios_boot_state.sclk_bootup_value,
1377 0 : (uint32_t *)&(table->GraphicsBootLevel));
1378 0 : if (result)
1379 : return result;
1380 :
1381 0 : result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1382 : data->vbios_boot_state.mclk_bootup_value,
1383 0 : (uint32_t *)&(table->MemoryBootLevel));
1384 :
1385 0 : if (result)
1386 : return result;
1387 :
1388 0 : table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1389 : VOLTAGE_SCALE;
1390 0 : table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1391 : VOLTAGE_SCALE;
1392 0 : table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1393 : VOLTAGE_SCALE;
1394 :
1395 0 : CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1396 0 : CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1397 0 : CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1398 :
1399 : return 0;
1400 : }
1401 :
1402 0 : static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1403 : {
1404 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1405 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1406 0 : struct phm_ppt_v1_information *table_info =
1407 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1408 : uint8_t count, level;
1409 :
1410 0 : count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1411 :
1412 0 : for (level = 0; level < count; level++) {
1413 0 : if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1414 0 : hw_data->vbios_boot_state.sclk_bootup_value) {
1415 0 : smu_data->smc_state_table.GraphicsBootLevel = level;
1416 0 : break;
1417 : }
1418 : }
1419 :
1420 0 : count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1421 0 : for (level = 0; level < count; level++) {
1422 0 : if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1423 0 : hw_data->vbios_boot_state.mclk_bootup_value) {
1424 0 : smu_data->smc_state_table.MemoryBootLevel = level;
1425 0 : break;
1426 : }
1427 : }
1428 :
1429 0 : return 0;
1430 : }
1431 :
1432 : static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
1433 : {
1434 : uint32_t tmp;
1435 0 : tmp = raw_setting * 4096 / 100;
1436 0 : return (uint16_t)tmp;
1437 : }
1438 :
1439 0 : static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1440 : {
1441 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1442 :
1443 0 : const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1444 0 : SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1445 0 : struct phm_ppt_v1_information *table_info =
1446 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1447 0 : struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
1448 0 : struct pp_advance_fan_control_parameters *fan_table =
1449 : &hwmgr->thermal_controller.advanceFanControlParameters;
1450 : int i, j, k;
1451 : const uint16_t *pdef1;
1452 : const uint16_t *pdef2;
1453 :
1454 0 : table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1455 0 : table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1456 :
1457 0 : PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
1458 : "Target Operating Temp is out of Range!",
1459 : );
1460 :
1461 0 : table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
1462 : cac_dtp_table->usTargetOperatingTemp * 256);
1463 0 : table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
1464 : cac_dtp_table->usTemperatureLimitHotspot * 256);
1465 0 : table->FanGainEdge = PP_HOST_TO_SMC_US(
1466 : scale_fan_gain_settings(fan_table->usFanGainEdge));
1467 0 : table->FanGainHotspot = PP_HOST_TO_SMC_US(
1468 : scale_fan_gain_settings(fan_table->usFanGainHotspot));
1469 :
1470 0 : pdef1 = defaults->BAPMTI_R;
1471 0 : pdef2 = defaults->BAPMTI_RC;
1472 :
1473 0 : for (i = 0; i < SMU75_DTE_ITERATIONS; i++) {
1474 0 : for (j = 0; j < SMU75_DTE_SOURCES; j++) {
1475 0 : for (k = 0; k < SMU75_DTE_SINKS; k++) {
1476 0 : table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
1477 0 : table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
1478 0 : pdef1++;
1479 0 : pdef2++;
1480 : }
1481 : }
1482 : }
1483 :
1484 0 : return 0;
1485 : }
1486 :
1487 0 : static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1488 : {
1489 : uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1490 0 : struct vegam_smumgr *smu_data =
1491 : (struct vegam_smumgr *)(hwmgr->smu_backend);
1492 :
1493 0 : uint8_t i, stretch_amount, volt_offset = 0;
1494 0 : struct phm_ppt_v1_information *table_info =
1495 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1496 0 : struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1497 : table_info->vdd_dep_on_sclk;
1498 :
1499 0 : stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1500 :
1501 0 : atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
1502 : &efuse);
1503 :
1504 0 : min = 1200;
1505 0 : max = 2500;
1506 :
1507 0 : ro = efuse * (max - min) / 255 + min;
1508 :
1509 : /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1510 0 : for (i = 0; i < sclk_table->count; i++) {
1511 0 : smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1512 0 : sclk_table->entries[i].cks_enable << i;
1513 0 : volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) *
1514 0 : 136418 - (ro - 70) * 1000000) /
1515 0 : (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1516 0 : volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 *
1517 0 : 3232 - (ro - 65) * 1000000) /
1518 0 : (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1519 :
1520 0 : if (volt_without_cks >= volt_with_cks)
1521 0 : volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1522 0 : sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1523 :
1524 0 : smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1525 : }
1526 :
1527 0 : smu_data->smc_state_table.LdoRefSel =
1528 0 : (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ?
1529 : table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1530 : /* Populate CKS Lookup Table */
1531 0 : if (!(stretch_amount == 1 || stretch_amount == 2 ||
1532 0 : stretch_amount == 5 || stretch_amount == 3 ||
1533 : stretch_amount == 4)) {
1534 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1535 : PHM_PlatformCaps_ClockStretcher);
1536 0 : PP_ASSERT_WITH_CODE(false,
1537 : "Stretch Amount in PPTable not supported\n",
1538 : return -EINVAL);
1539 : }
1540 :
1541 0 : value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1542 0 : value &= 0xFFFFFFFE;
1543 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1544 :
1545 0 : return 0;
1546 : }
1547 :
1548 0 : static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
1549 : {
1550 : uint32_t efuse;
1551 :
1552 0 : efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1553 : ixSMU_EFUSE_0 + (49 * 4));
1554 0 : efuse &= 0x00000001;
1555 :
1556 0 : if (efuse)
1557 : return true;
1558 :
1559 0 : return false;
1560 : }
1561 :
1562 0 : static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1563 : {
1564 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1565 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1566 :
1567 0 : SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1568 0 : int result = 0;
1569 0 : struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1570 0 : AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1571 0 : AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1572 : uint32_t tmp, i;
1573 :
1574 0 : struct phm_ppt_v1_information *table_info =
1575 : (struct phm_ppt_v1_information *)hwmgr->pptable;
1576 0 : struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1577 : table_info->vdd_dep_on_sclk;
1578 :
1579 0 : if (!hwmgr->avfs_supported)
1580 : return 0;
1581 :
1582 0 : result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1583 :
1584 0 : if (0 == result) {
1585 0 : table->BTCGB_VDROOP_TABLE[0].a0 =
1586 0 : PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1587 0 : table->BTCGB_VDROOP_TABLE[0].a1 =
1588 0 : PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1589 0 : table->BTCGB_VDROOP_TABLE[0].a2 =
1590 0 : PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1591 0 : table->BTCGB_VDROOP_TABLE[1].a0 =
1592 0 : PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1593 0 : table->BTCGB_VDROOP_TABLE[1].a1 =
1594 0 : PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1595 0 : table->BTCGB_VDROOP_TABLE[1].a2 =
1596 0 : PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1597 0 : table->AVFSGB_FUSE_TABLE[0].m1 =
1598 0 : PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1599 0 : table->AVFSGB_FUSE_TABLE[0].m2 =
1600 0 : PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1601 0 : table->AVFSGB_FUSE_TABLE[0].b =
1602 0 : PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1603 0 : table->AVFSGB_FUSE_TABLE[0].m1_shift = 24;
1604 0 : table->AVFSGB_FUSE_TABLE[0].m2_shift = 12;
1605 0 : table->AVFSGB_FUSE_TABLE[1].m1 =
1606 0 : PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1607 0 : table->AVFSGB_FUSE_TABLE[1].m2 =
1608 0 : PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1609 0 : table->AVFSGB_FUSE_TABLE[1].b =
1610 0 : PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1611 0 : table->AVFSGB_FUSE_TABLE[1].m1_shift = 24;
1612 0 : table->AVFSGB_FUSE_TABLE[1].m2_shift = 12;
1613 0 : table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1614 0 : AVFS_meanNsigma.Aconstant[0] =
1615 0 : PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1616 0 : AVFS_meanNsigma.Aconstant[1] =
1617 0 : PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1618 0 : AVFS_meanNsigma.Aconstant[2] =
1619 0 : PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1620 0 : AVFS_meanNsigma.DC_tol_sigma =
1621 0 : PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1622 0 : AVFS_meanNsigma.Platform_mean =
1623 0 : PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1624 0 : AVFS_meanNsigma.PSM_Age_CompFactor =
1625 0 : PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1626 0 : AVFS_meanNsigma.Platform_sigma =
1627 0 : PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1628 :
1629 0 : for (i = 0; i < sclk_table->count; i++) {
1630 0 : AVFS_meanNsigma.Static_Voltage_Offset[i] =
1631 0 : (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1632 0 : AVFS_SclkOffset.Sclk_Offset[i] =
1633 0 : PP_HOST_TO_SMC_US((uint16_t)
1634 : (sclk_table->entries[i].sclk_offset) / 100);
1635 : }
1636 :
1637 0 : result = smu7_read_smc_sram_dword(hwmgr,
1638 : SMU7_FIRMWARE_HEADER_LOCATION +
1639 : offsetof(SMU75_Firmware_Header, AvfsMeanNSigma),
1640 : &tmp, SMC_RAM_END);
1641 0 : smu7_copy_bytes_to_smc(hwmgr,
1642 : tmp,
1643 : (uint8_t *)&AVFS_meanNsigma,
1644 : sizeof(AVFS_meanNsigma_t),
1645 : SMC_RAM_END);
1646 :
1647 0 : result = smu7_read_smc_sram_dword(hwmgr,
1648 : SMU7_FIRMWARE_HEADER_LOCATION +
1649 : offsetof(SMU75_Firmware_Header, AvfsSclkOffsetTable),
1650 : &tmp, SMC_RAM_END);
1651 0 : smu7_copy_bytes_to_smc(hwmgr,
1652 : tmp,
1653 : (uint8_t *)&AVFS_SclkOffset,
1654 : sizeof(AVFS_Sclk_Offset_t),
1655 : SMC_RAM_END);
1656 :
1657 0 : data->avfs_vdroop_override_setting =
1658 0 : (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1659 0 : (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1660 0 : (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1661 0 : (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1662 0 : data->apply_avfs_cks_off_voltage =
1663 0 : (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1664 : }
1665 : return result;
1666 : }
1667 :
1668 0 : static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr,
1669 : struct SMU75_Discrete_DpmTable *table)
1670 : {
1671 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1672 0 : struct vegam_smumgr *smu_data =
1673 : (struct vegam_smumgr *)(hwmgr->smu_backend);
1674 : uint16_t config;
1675 :
1676 0 : config = VR_MERGED_WITH_VDDC;
1677 0 : table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1678 :
1679 : /* Set Vddc Voltage Controller */
1680 0 : if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1681 0 : config = VR_SVI2_PLANE_1;
1682 0 : table->VRConfig |= config;
1683 : } else {
1684 0 : PP_ASSERT_WITH_CODE(false,
1685 : "VDDC should be on SVI2 control in merged mode!",
1686 : );
1687 : }
1688 : /* Set Vddci Voltage Controller */
1689 0 : if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1690 0 : config = VR_SVI2_PLANE_2; /* only in merged mode */
1691 0 : table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1692 0 : } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1693 0 : config = VR_SMIO_PATTERN_1;
1694 0 : table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1695 : } else {
1696 0 : config = VR_STATIC_VOLTAGE;
1697 0 : table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1698 : }
1699 : /* Set Mvdd Voltage Controller */
1700 0 : if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1701 0 : if (config != VR_SVI2_PLANE_2) {
1702 0 : config = VR_SVI2_PLANE_2;
1703 0 : table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1704 0 : cgs_write_ind_register(hwmgr->device,
1705 : CGS_IND_REG__SMC,
1706 : smu_data->smu7_data.soft_regs_start +
1707 : offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1708 : 0x1);
1709 : } else {
1710 0 : PP_ASSERT_WITH_CODE(false,
1711 : "SVI2 Plane 2 is already taken, set MVDD as Static",);
1712 0 : config = VR_STATIC_VOLTAGE;
1713 0 : table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1714 : }
1715 0 : } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1716 0 : config = VR_SMIO_PATTERN_2;
1717 0 : table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1718 0 : cgs_write_ind_register(hwmgr->device,
1719 : CGS_IND_REG__SMC,
1720 : smu_data->smu7_data.soft_regs_start +
1721 : offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1722 : 0x1);
1723 : } else {
1724 0 : config = VR_STATIC_VOLTAGE;
1725 0 : table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1726 : }
1727 :
1728 0 : return 0;
1729 : }
1730 :
1731 : static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1732 : {
1733 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1734 0 : const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1735 :
1736 0 : smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
1737 0 : smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
1738 0 : smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
1739 0 : smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
1740 :
1741 : return 0;
1742 : }
1743 :
1744 : static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1745 : {
1746 : uint16_t tdc_limit;
1747 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1748 0 : struct phm_ppt_v1_information *table_info =
1749 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1750 0 : const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1751 :
1752 0 : tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
1753 0 : smu_data->power_tune_table.TDC_VDDC_PkgLimit =
1754 0 : CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
1755 0 : smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
1756 0 : defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
1757 0 : smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
1758 :
1759 : return 0;
1760 : }
1761 :
1762 0 : static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1763 : {
1764 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1765 0 : const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1766 : uint32_t temp;
1767 :
1768 0 : if (smu7_read_smc_sram_dword(hwmgr,
1769 : fuse_table_offset +
1770 : offsetof(SMU75_Discrete_PmFuses, TdcWaterfallCtl),
1771 : (uint32_t *)&temp, SMC_RAM_END))
1772 0 : PP_ASSERT_WITH_CODE(false,
1773 : "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
1774 : return -EINVAL);
1775 : else {
1776 0 : smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
1777 0 : smu_data->power_tune_table.LPMLTemperatureMin =
1778 0 : (uint8_t)((temp >> 16) & 0xff);
1779 0 : smu_data->power_tune_table.LPMLTemperatureMax =
1780 0 : (uint8_t)((temp >> 8) & 0xff);
1781 0 : smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
1782 : }
1783 0 : return 0;
1784 : }
1785 :
1786 : static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1787 : {
1788 : int i;
1789 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1790 :
1791 : /* Currently not used. Set all to zero. */
1792 0 : for (i = 0; i < 16; i++)
1793 0 : smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
1794 :
1795 : return 0;
1796 : }
1797 :
1798 : static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1799 : {
1800 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1801 :
1802 : /* TO DO move to hwmgr */
1803 0 : if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
1804 0 : || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
1805 0 : hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
1806 0 : hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
1807 :
1808 0 : smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
1809 : hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
1810 : return 0;
1811 : }
1812 :
1813 : static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1814 : {
1815 : int i;
1816 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1817 :
1818 : /* Currently not used. Set all to zero. */
1819 0 : for (i = 0; i < 16; i++)
1820 0 : smu_data->power_tune_table.GnbLPML[i] = 0;
1821 :
1822 : return 0;
1823 : }
1824 :
1825 : static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1826 : {
1827 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1828 0 : struct phm_ppt_v1_information *table_info =
1829 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1830 0 : uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
1831 0 : uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
1832 0 : struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
1833 :
1834 0 : hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
1835 0 : lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
1836 :
1837 0 : smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
1838 0 : CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
1839 0 : smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
1840 0 : CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
1841 :
1842 : return 0;
1843 : }
1844 :
1845 0 : static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1846 : {
1847 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1848 : uint32_t pm_fuse_table_offset;
1849 :
1850 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1851 : PHM_PlatformCaps_PowerContainment)) {
1852 0 : if (smu7_read_smc_sram_dword(hwmgr,
1853 : SMU7_FIRMWARE_HEADER_LOCATION +
1854 : offsetof(SMU75_Firmware_Header, PmFuseTable),
1855 : &pm_fuse_table_offset, SMC_RAM_END))
1856 0 : PP_ASSERT_WITH_CODE(false,
1857 : "Attempt to get pm_fuse_table_offset Failed!",
1858 : return -EINVAL);
1859 :
1860 0 : if (vegam_populate_svi_load_line(hwmgr))
1861 : PP_ASSERT_WITH_CODE(false,
1862 : "Attempt to populate SviLoadLine Failed!",
1863 : return -EINVAL);
1864 :
1865 0 : if (vegam_populate_tdc_limit(hwmgr))
1866 : PP_ASSERT_WITH_CODE(false,
1867 : "Attempt to populate TDCLimit Failed!", return -EINVAL);
1868 :
1869 0 : if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset))
1870 0 : PP_ASSERT_WITH_CODE(false,
1871 : "Attempt to populate TdcWaterfallCtl, "
1872 : "LPMLTemperature Min and Max Failed!",
1873 : return -EINVAL);
1874 :
1875 0 : if (0 != vegam_populate_temperature_scaler(hwmgr))
1876 : PP_ASSERT_WITH_CODE(false,
1877 : "Attempt to populate LPMLTemperatureScaler Failed!",
1878 : return -EINVAL);
1879 :
1880 0 : if (vegam_populate_fuzzy_fan(hwmgr))
1881 : PP_ASSERT_WITH_CODE(false,
1882 : "Attempt to populate Fuzzy Fan Control parameters Failed!",
1883 : return -EINVAL);
1884 :
1885 0 : if (vegam_populate_gnb_lpml(hwmgr))
1886 : PP_ASSERT_WITH_CODE(false,
1887 : "Attempt to populate GnbLPML Failed!",
1888 : return -EINVAL);
1889 :
1890 0 : if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr))
1891 : PP_ASSERT_WITH_CODE(false,
1892 : "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
1893 : "Sidd Failed!", return -EINVAL);
1894 :
1895 0 : if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
1896 0 : (uint8_t *)&smu_data->power_tune_table,
1897 : (sizeof(struct SMU75_Discrete_PmFuses) - PMFUSES_AVFSSIZE),
1898 : SMC_RAM_END))
1899 0 : PP_ASSERT_WITH_CODE(false,
1900 : "Attempt to download PmFuseTable Failed!",
1901 : return -EINVAL);
1902 : }
1903 : return 0;
1904 : }
1905 :
1906 : static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr)
1907 : {
1908 0 : struct amdgpu_device *adev = hwmgr->adev;
1909 :
1910 0 : smum_send_msg_to_smc_with_parameter(hwmgr,
1911 : PPSMC_MSG_EnableModeSwitchRLCNotification,
1912 : adev->gfx.cu_info.number,
1913 : NULL);
1914 :
1915 : return 0;
1916 : }
1917 :
1918 0 : static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
1919 : {
1920 : int result;
1921 0 : struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1922 0 : struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1923 :
1924 0 : struct phm_ppt_v1_information *table_info =
1925 : (struct phm_ppt_v1_information *)(hwmgr->pptable);
1926 0 : struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1927 : uint8_t i;
1928 : struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1929 0 : struct phm_ppt_v1_gpio_table *gpio_table =
1930 : (struct phm_ppt_v1_gpio_table *)table_info->gpio_table;
1931 : pp_atomctrl_clock_dividers_vi dividers;
1932 :
1933 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1934 : PHM_PlatformCaps_AutomaticDCTransition);
1935 :
1936 0 : vegam_initialize_power_tune_defaults(hwmgr);
1937 :
1938 0 : if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1939 0 : vegam_populate_smc_voltage_tables(hwmgr, table);
1940 :
1941 0 : table->SystemFlags = 0;
1942 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1943 : PHM_PlatformCaps_AutomaticDCTransition))
1944 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1945 :
1946 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1947 : PHM_PlatformCaps_StepVddc))
1948 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1949 :
1950 0 : if (hw_data->is_memory_gddr5)
1951 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1952 :
1953 0 : if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1954 0 : result = vegam_populate_ulv_state(hwmgr, table);
1955 : PP_ASSERT_WITH_CODE(!result,
1956 : "Failed to initialize ULV state!", return result);
1957 0 : cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1958 : ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1959 : }
1960 :
1961 0 : result = vegam_populate_smc_link_level(hwmgr, table);
1962 0 : PP_ASSERT_WITH_CODE(!result,
1963 : "Failed to initialize Link Level!", return result);
1964 :
1965 0 : result = vegam_populate_all_graphic_levels(hwmgr);
1966 0 : PP_ASSERT_WITH_CODE(!result,
1967 : "Failed to initialize Graphics Level!", return result);
1968 :
1969 0 : result = vegam_populate_all_memory_levels(hwmgr);
1970 0 : PP_ASSERT_WITH_CODE(!result,
1971 : "Failed to initialize Memory Level!", return result);
1972 :
1973 0 : result = vegam_populate_smc_acpi_level(hwmgr, table);
1974 0 : PP_ASSERT_WITH_CODE(!result,
1975 : "Failed to initialize ACPI Level!", return result);
1976 :
1977 0 : result = vegam_populate_smc_vce_level(hwmgr, table);
1978 0 : PP_ASSERT_WITH_CODE(!result,
1979 : "Failed to initialize VCE Level!", return result);
1980 :
1981 : /* Since only the initial state is completely set up at this point
1982 : * (the other states are just copies of the boot state) we only
1983 : * need to populate the ARB settings for the initial state.
1984 : */
1985 0 : result = vegam_program_memory_timing_parameters(hwmgr);
1986 0 : PP_ASSERT_WITH_CODE(!result,
1987 : "Failed to Write ARB settings for the initial state.", return result);
1988 :
1989 0 : result = vegam_populate_smc_uvd_level(hwmgr, table);
1990 0 : PP_ASSERT_WITH_CODE(!result,
1991 : "Failed to initialize UVD Level!", return result);
1992 :
1993 0 : result = vegam_populate_smc_boot_level(hwmgr, table);
1994 0 : PP_ASSERT_WITH_CODE(!result,
1995 : "Failed to initialize Boot Level!", return result);
1996 :
1997 0 : result = vegam_populate_smc_initial_state(hwmgr);
1998 0 : PP_ASSERT_WITH_CODE(!result,
1999 : "Failed to initialize Boot State!", return result);
2000 :
2001 0 : result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr);
2002 0 : PP_ASSERT_WITH_CODE(!result,
2003 : "Failed to populate BAPM Parameters!", return result);
2004 :
2005 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2006 : PHM_PlatformCaps_ClockStretcher)) {
2007 0 : result = vegam_populate_clock_stretcher_data_table(hwmgr);
2008 0 : PP_ASSERT_WITH_CODE(!result,
2009 : "Failed to populate Clock Stretcher Data Table!",
2010 : return result);
2011 : }
2012 :
2013 0 : result = vegam_populate_avfs_parameters(hwmgr);
2014 0 : PP_ASSERT_WITH_CODE(!result,
2015 : "Failed to populate AVFS Parameters!", return result;);
2016 :
2017 0 : table->CurrSclkPllRange = 0xff;
2018 0 : table->GraphicsVoltageChangeEnable = 1;
2019 0 : table->GraphicsThermThrottleEnable = 1;
2020 0 : table->GraphicsInterval = 1;
2021 0 : table->VoltageInterval = 1;
2022 0 : table->ThermalInterval = 1;
2023 0 : table->TemperatureLimitHigh =
2024 0 : table_info->cac_dtp_table->usTargetOperatingTemp *
2025 : SMU7_Q88_FORMAT_CONVERSION_UNIT;
2026 0 : table->TemperatureLimitLow =
2027 0 : (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2028 : SMU7_Q88_FORMAT_CONVERSION_UNIT;
2029 0 : table->MemoryVoltageChangeEnable = 1;
2030 0 : table->MemoryInterval = 1;
2031 0 : table->VoltageResponseTime = 0;
2032 0 : table->PhaseResponseTime = 0;
2033 0 : table->MemoryThermThrottleEnable = 1;
2034 :
2035 0 : PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
2036 : "There must be 1 or more PCIE levels defined in PPTable.",
2037 : return -EINVAL);
2038 0 : table->PCIeBootLinkLevel =
2039 : hw_data->dpm_table.pcie_speed_table.count;
2040 0 : table->PCIeGenInterval = 1;
2041 0 : table->VRConfig = 0;
2042 :
2043 0 : result = vegam_populate_vr_config(hwmgr, table);
2044 0 : PP_ASSERT_WITH_CODE(!result,
2045 : "Failed to populate VRConfig setting!", return result);
2046 :
2047 0 : table->ThermGpio = 17;
2048 0 : table->SclkStepSize = 0x4000;
2049 :
2050 0 : if (atomctrl_get_pp_assign_pin(hwmgr,
2051 : VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2052 0 : table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2053 0 : if (gpio_table)
2054 0 : table->VRHotLevel =
2055 0 : table_info->gpio_table->vrhot_triggered_sclk_dpm_index;
2056 : } else {
2057 0 : table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2058 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2059 : PHM_PlatformCaps_RegulatorHot);
2060 : }
2061 :
2062 0 : if (atomctrl_get_pp_assign_pin(hwmgr,
2063 : PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin)) {
2064 0 : table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2065 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2066 0 : PHM_PlatformCaps_AutomaticDCTransition) &&
2067 0 : !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
2068 0 : phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2069 : PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
2070 : } else {
2071 0 : table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2072 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2073 : PHM_PlatformCaps_AutomaticDCTransition);
2074 : }
2075 :
2076 : /* Thermal Output GPIO */
2077 0 : if (atomctrl_get_pp_assign_pin(hwmgr,
2078 : THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin)) {
2079 0 : table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2080 :
2081 : /* For porlarity read GPIOPAD_A with assigned Gpio pin
2082 : * since VBIOS will program this register to set 'inactive state',
2083 : * driver can then determine 'active state' from this and
2084 : * program SMU with correct polarity
2085 : */
2086 0 : table->ThermOutPolarity =
2087 0 : (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2088 0 : (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2089 0 : table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2090 :
2091 : /* if required, combine VRHot/PCC with thermal out GPIO */
2092 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2093 0 : PHM_PlatformCaps_RegulatorHot) &&
2094 0 : phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2095 : PHM_PlatformCaps_CombinePCCWithThermalSignal))
2096 0 : table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2097 : } else {
2098 0 : table->ThermOutGpio = 17;
2099 0 : table->ThermOutPolarity = 1;
2100 0 : table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2101 : }
2102 :
2103 : /* Populate BIF_SCLK levels into SMC DPM table */
2104 0 : for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2105 0 : result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2106 : smu_data->bif_sclk_table[i], ÷rs);
2107 0 : PP_ASSERT_WITH_CODE(!result,
2108 : "Can not find DFS divide id for Sclk",
2109 : return result);
2110 :
2111 0 : if (i == 0)
2112 0 : table->Ulv.BifSclkDfs =
2113 0 : PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2114 : else
2115 0 : table->LinkLevel[i - 1].BifSclkDfs =
2116 0 : PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2117 : }
2118 :
2119 0 : for (i = 0; i < SMU75_MAX_ENTRIES_SMIO; i++)
2120 0 : table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2121 :
2122 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2123 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2124 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2125 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2126 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2127 0 : CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2128 0 : CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2129 0 : CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2130 0 : CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2131 0 : CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2132 :
2133 : /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2134 0 : result = smu7_copy_bytes_to_smc(hwmgr,
2135 0 : smu_data->smu7_data.dpm_table_start +
2136 : offsetof(SMU75_Discrete_DpmTable, SystemFlags),
2137 0 : (uint8_t *)&(table->SystemFlags),
2138 : sizeof(SMU75_Discrete_DpmTable) - 3 * sizeof(SMU75_PIDController),
2139 : SMC_RAM_END);
2140 0 : PP_ASSERT_WITH_CODE(!result,
2141 : "Failed to upload dpm data to SMC memory!", return result);
2142 :
2143 0 : result = vegam_populate_pm_fuses(hwmgr);
2144 0 : PP_ASSERT_WITH_CODE(!result,
2145 : "Failed to populate PM fuses to SMC memory!", return result);
2146 :
2147 0 : result = vegam_enable_reconfig_cus(hwmgr);
2148 : PP_ASSERT_WITH_CODE(!result,
2149 : "Failed to enable reconfigurable CUs!", return result);
2150 :
2151 0 : return 0;
2152 : }
2153 :
2154 0 : static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member)
2155 : {
2156 0 : switch (type) {
2157 : case SMU_SoftRegisters:
2158 0 : switch (member) {
2159 : case HandshakeDisables:
2160 : return offsetof(SMU75_SoftRegisters, HandshakeDisables);
2161 : case VoltageChangeTimeout:
2162 0 : return offsetof(SMU75_SoftRegisters, VoltageChangeTimeout);
2163 : case AverageGraphicsActivity:
2164 0 : return offsetof(SMU75_SoftRegisters, AverageGraphicsActivity);
2165 : case AverageMemoryActivity:
2166 0 : return offsetof(SMU75_SoftRegisters, AverageMemoryActivity);
2167 : case PreVBlankGap:
2168 0 : return offsetof(SMU75_SoftRegisters, PreVBlankGap);
2169 : case VBlankTimeout:
2170 0 : return offsetof(SMU75_SoftRegisters, VBlankTimeout);
2171 : case UcodeLoadStatus:
2172 0 : return offsetof(SMU75_SoftRegisters, UcodeLoadStatus);
2173 : case DRAM_LOG_ADDR_H:
2174 0 : return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_H);
2175 : case DRAM_LOG_ADDR_L:
2176 0 : return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_L);
2177 : case DRAM_LOG_PHY_ADDR_H:
2178 0 : return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2179 : case DRAM_LOG_PHY_ADDR_L:
2180 0 : return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2181 : case DRAM_LOG_BUFF_SIZE:
2182 0 : return offsetof(SMU75_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2183 : }
2184 : break;
2185 : case SMU_Discrete_DpmTable:
2186 0 : switch (member) {
2187 : case UvdBootLevel:
2188 : return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);
2189 : case VceBootLevel:
2190 0 : return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
2191 : case LowSclkInterruptThreshold:
2192 0 : return offsetof(SMU75_Discrete_DpmTable, LowSclkInterruptThreshold);
2193 : }
2194 : break;
2195 : }
2196 0 : pr_warn("can't get the offset of type %x member %x\n", type, member);
2197 0 : return 0;
2198 : }
2199 :
2200 : static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2201 : {
2202 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2203 :
2204 0 : if (data->need_update_smu7_dpm_table &
2205 : (DPMTABLE_OD_UPDATE_SCLK +
2206 : DPMTABLE_UPDATE_SCLK +
2207 : DPMTABLE_UPDATE_MCLK))
2208 0 : return vegam_program_memory_timing_parameters(hwmgr);
2209 :
2210 : return 0;
2211 : }
2212 :
2213 0 : static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2214 : {
2215 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2216 0 : struct vegam_smumgr *smu_data =
2217 : (struct vegam_smumgr *)(hwmgr->smu_backend);
2218 0 : int result = 0;
2219 0 : uint32_t low_sclk_interrupt_threshold = 0;
2220 :
2221 0 : if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2222 : PHM_PlatformCaps_SclkThrottleLowNotification)
2223 0 : && (data->low_sclk_interrupt_threshold != 0)) {
2224 : low_sclk_interrupt_threshold =
2225 : data->low_sclk_interrupt_threshold;
2226 :
2227 0 : CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2228 :
2229 0 : result = smu7_copy_bytes_to_smc(
2230 : hwmgr,
2231 0 : smu_data->smu7_data.dpm_table_start +
2232 : offsetof(SMU75_Discrete_DpmTable,
2233 : LowSclkInterruptThreshold),
2234 : (uint8_t *)&low_sclk_interrupt_threshold,
2235 : sizeof(uint32_t),
2236 : SMC_RAM_END);
2237 : }
2238 0 : PP_ASSERT_WITH_CODE((result == 0),
2239 : "Failed to update SCLK threshold!", return result);
2240 :
2241 0 : result = vegam_program_mem_timing_parameters(hwmgr);
2242 0 : PP_ASSERT_WITH_CODE((result == 0),
2243 : "Failed to program memory timing parameters!",
2244 : );
2245 :
2246 : return result;
2247 : }
2248 :
2249 0 : static int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2250 : {
2251 0 : struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2252 : int ret;
2253 :
2254 0 : if (!hwmgr->avfs_supported)
2255 : return 0;
2256 :
2257 0 : ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2258 0 : if (!ret) {
2259 0 : if (data->apply_avfs_cks_off_voltage)
2260 0 : ret = smum_send_msg_to_smc(hwmgr,
2261 : PPSMC_MSG_ApplyAvfsCksOffVoltage,
2262 : NULL);
2263 : }
2264 :
2265 : return ret;
2266 : }
2267 :
2268 0 : static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2269 : {
2270 0 : PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
2271 : "VBIOS fan info is not correct!",
2272 : );
2273 0 : phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2274 : PHM_PlatformCaps_MicrocodeFanControl);
2275 0 : return 0;
2276 : }
2277 :
2278 : const struct pp_smumgr_func vegam_smu_funcs = {
2279 : .name = "vegam_smu",
2280 : .smu_init = vegam_smu_init,
2281 : .smu_fini = smu7_smu_fini,
2282 : .start_smu = vegam_start_smu,
2283 : .check_fw_load_finish = smu7_check_fw_load_finish,
2284 : .request_smu_load_fw = smu7_reload_firmware,
2285 : .request_smu_load_specific_fw = NULL,
2286 : .send_msg_to_smc = smu7_send_msg_to_smc,
2287 : .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2288 : .get_argument = smu7_get_argument,
2289 : .process_firmware_header = vegam_process_firmware_header,
2290 : .is_dpm_running = vegam_is_dpm_running,
2291 : .get_mac_definition = vegam_get_mac_definition,
2292 : .update_smc_table = vegam_update_smc_table,
2293 : .init_smc_table = vegam_init_smc_table,
2294 : .get_offsetof = vegam_get_offsetof,
2295 : .populate_all_graphic_levels = vegam_populate_all_graphic_levels,
2296 : .populate_all_memory_levels = vegam_populate_all_memory_levels,
2297 : .update_sclk_threshold = vegam_update_sclk_threshold,
2298 : .is_hw_avfs_present = vegam_is_hw_avfs_present,
2299 : .thermal_avfs_enable = vegam_thermal_avfs_enable,
2300 : .thermal_setup_fan_table = vegam_thermal_setup_fan_table,
2301 : };
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