Line data Source code
1 : /*
2 : * Copyright 2019 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #define SWSMU_CODE_LAYER_L2
25 :
26 : #include <linux/firmware.h>
27 : #include <linux/pci.h>
28 : #include <linux/i2c.h>
29 : #include "amdgpu.h"
30 : #include "amdgpu_dpm.h"
31 : #include "amdgpu_smu.h"
32 : #include "atomfirmware.h"
33 : #include "amdgpu_atomfirmware.h"
34 : #include "amdgpu_atombios.h"
35 : #include "smu_v11_0.h"
36 : #include "smu11_driver_if_sienna_cichlid.h"
37 : #include "soc15_common.h"
38 : #include "atom.h"
39 : #include "sienna_cichlid_ppt.h"
40 : #include "smu_v11_0_7_pptable.h"
41 : #include "smu_v11_0_7_ppsmc.h"
42 : #include "nbio/nbio_2_3_offset.h"
43 : #include "nbio/nbio_2_3_sh_mask.h"
44 : #include "thm/thm_11_0_2_offset.h"
45 : #include "thm/thm_11_0_2_sh_mask.h"
46 : #include "mp/mp_11_0_offset.h"
47 : #include "mp/mp_11_0_sh_mask.h"
48 :
49 : #include "asic_reg/mp/mp_11_0_sh_mask.h"
50 : #include "amdgpu_ras.h"
51 : #include "smu_cmn.h"
52 :
53 : /*
54 : * DO NOT use these for err/warn/info/debug messages.
55 : * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 : * They are more MGPU friendly.
57 : */
58 : #undef pr_err
59 : #undef pr_warn
60 : #undef pr_info
61 : #undef pr_debug
62 :
63 : #define FEATURE_MASK(feature) (1ULL << feature)
64 : #define SMC_DPM_FEATURE ( \
65 : FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 : FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 : FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 : FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 : FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 : FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 : FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 : FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
73 :
74 : #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75 :
76 : #define GET_PPTABLE_MEMBER(field, member) do {\
77 : if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
78 : (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 : else\
80 : (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81 : } while(0)
82 :
83 : /* STB FIFO depth is in 64bit units */
84 : #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
85 :
86 : /*
87 : * SMU support ECCTABLE since version 58.70.0,
88 : * use this to check whether ECCTABLE feature is supported.
89 : */
90 : #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
91 :
92 : static int get_table_size(struct smu_context *smu)
93 : {
94 0 : if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
95 : return sizeof(PPTable_beige_goby_t);
96 : else
97 : return sizeof(PPTable_t);
98 : }
99 :
100 : static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
101 : MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
102 : MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
103 : MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
104 : MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
105 : MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
106 : MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 : MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
108 : MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
109 : MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
110 : MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
111 : MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
112 : MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
113 : MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
114 : MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
115 : MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
116 : MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
117 : MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
118 : MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
119 : MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
120 : MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
121 : MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
122 : MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
123 : MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
124 : MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
125 : MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
126 : MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
127 : MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
128 : MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
129 : MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
130 : MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
131 : MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
132 : MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
133 : MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
134 : MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
135 : MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
136 : MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
137 : MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
138 : MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
139 : MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
140 : MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
141 : MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
142 : MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
143 : MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
144 : MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
145 : MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
146 : MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
147 : MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
148 : MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
149 : MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
150 : MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
151 : MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
152 : MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
153 : MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
154 : MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
155 : MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
156 : MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
157 : MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
158 : };
159 :
160 : static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
161 : CLK_MAP(GFXCLK, PPCLK_GFXCLK),
162 : CLK_MAP(SCLK, PPCLK_GFXCLK),
163 : CLK_MAP(SOCCLK, PPCLK_SOCCLK),
164 : CLK_MAP(FCLK, PPCLK_FCLK),
165 : CLK_MAP(UCLK, PPCLK_UCLK),
166 : CLK_MAP(MCLK, PPCLK_UCLK),
167 : CLK_MAP(DCLK, PPCLK_DCLK_0),
168 : CLK_MAP(DCLK1, PPCLK_DCLK_1),
169 : CLK_MAP(VCLK, PPCLK_VCLK_0),
170 : CLK_MAP(VCLK1, PPCLK_VCLK_1),
171 : CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
172 : CLK_MAP(DISPCLK, PPCLK_DISPCLK),
173 : CLK_MAP(PIXCLK, PPCLK_PIXCLK),
174 : CLK_MAP(PHYCLK, PPCLK_PHYCLK),
175 : };
176 :
177 : static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
178 : FEA_MAP(DPM_PREFETCHER),
179 : FEA_MAP(DPM_GFXCLK),
180 : FEA_MAP(DPM_GFX_GPO),
181 : FEA_MAP(DPM_UCLK),
182 : FEA_MAP(DPM_FCLK),
183 : FEA_MAP(DPM_SOCCLK),
184 : FEA_MAP(DPM_MP0CLK),
185 : FEA_MAP(DPM_LINK),
186 : FEA_MAP(DPM_DCEFCLK),
187 : FEA_MAP(DPM_XGMI),
188 : FEA_MAP(MEM_VDDCI_SCALING),
189 : FEA_MAP(MEM_MVDD_SCALING),
190 : FEA_MAP(DS_GFXCLK),
191 : FEA_MAP(DS_SOCCLK),
192 : FEA_MAP(DS_FCLK),
193 : FEA_MAP(DS_LCLK),
194 : FEA_MAP(DS_DCEFCLK),
195 : FEA_MAP(DS_UCLK),
196 : FEA_MAP(GFX_ULV),
197 : FEA_MAP(FW_DSTATE),
198 : FEA_MAP(GFXOFF),
199 : FEA_MAP(BACO),
200 : FEA_MAP(MM_DPM_PG),
201 : FEA_MAP(RSMU_SMN_CG),
202 : FEA_MAP(PPT),
203 : FEA_MAP(TDC),
204 : FEA_MAP(APCC_PLUS),
205 : FEA_MAP(GTHR),
206 : FEA_MAP(ACDC),
207 : FEA_MAP(VR0HOT),
208 : FEA_MAP(VR1HOT),
209 : FEA_MAP(FW_CTF),
210 : FEA_MAP(FAN_CONTROL),
211 : FEA_MAP(THERMAL),
212 : FEA_MAP(GFX_DCS),
213 : FEA_MAP(RM),
214 : FEA_MAP(LED_DISPLAY),
215 : FEA_MAP(GFX_SS),
216 : FEA_MAP(OUT_OF_BAND_MONITOR),
217 : FEA_MAP(TEMP_DEPENDENT_VMIN),
218 : FEA_MAP(MMHUB_PG),
219 : FEA_MAP(ATHUB_PG),
220 : FEA_MAP(APCC_DFLL),
221 : };
222 :
223 : static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
224 : TAB_MAP(PPTABLE),
225 : TAB_MAP(WATERMARKS),
226 : TAB_MAP(AVFS_PSM_DEBUG),
227 : TAB_MAP(AVFS_FUSE_OVERRIDE),
228 : TAB_MAP(PMSTATUSLOG),
229 : TAB_MAP(SMU_METRICS),
230 : TAB_MAP(DRIVER_SMU_CONFIG),
231 : TAB_MAP(ACTIVITY_MONITOR_COEFF),
232 : TAB_MAP(OVERDRIVE),
233 : TAB_MAP(I2C_COMMANDS),
234 : TAB_MAP(PACE),
235 : TAB_MAP(ECCINFO),
236 : };
237 :
238 : static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
239 : PWR_MAP(AC),
240 : PWR_MAP(DC),
241 : };
242 :
243 : static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
244 : WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
245 : WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
246 : WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
247 : WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
248 : WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
249 : WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
250 : WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
251 : };
252 :
253 : static const uint8_t sienna_cichlid_throttler_map[] = {
254 : [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
255 : [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
256 : [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
257 : [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
258 : [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
259 : [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
260 : [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
261 : [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
262 : [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
263 : [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
264 : [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
265 : [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
266 : [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
267 : [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
268 : [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
269 : [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
270 : [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
271 : [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
272 : };
273 :
274 : static int
275 0 : sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
276 : uint32_t *feature_mask, uint32_t num)
277 : {
278 0 : struct amdgpu_device *adev = smu->adev;
279 :
280 0 : if (num > 2)
281 : return -EINVAL;
282 :
283 0 : memset(feature_mask, 0, sizeof(uint32_t) * num);
284 :
285 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
286 : | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
287 : | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
288 : | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
289 : | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
290 : | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
291 : | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
292 : | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
293 : | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
294 : | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
295 : | FEATURE_MASK(FEATURE_GFX_SS_BIT)
296 : | FEATURE_MASK(FEATURE_VR0HOT_BIT)
297 : | FEATURE_MASK(FEATURE_PPT_BIT)
298 : | FEATURE_MASK(FEATURE_TDC_BIT)
299 : | FEATURE_MASK(FEATURE_BACO_BIT)
300 : | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
301 : | FEATURE_MASK(FEATURE_FW_CTF_BIT)
302 : | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
303 : | FEATURE_MASK(FEATURE_THERMAL_BIT)
304 : | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
305 :
306 0 : if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
307 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
308 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
309 : }
310 :
311 0 : if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
312 0 : (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
313 0 : !(adev->flags & AMD_IS_APU))
314 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
315 :
316 0 : if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
317 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
318 : | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
319 : | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
320 :
321 0 : if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
322 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
323 :
324 0 : if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
325 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
326 :
327 0 : if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
328 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
329 :
330 0 : if (adev->pm.pp_feature & PP_ULV_MASK)
331 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
332 :
333 0 : if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
334 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
335 :
336 0 : if (adev->pm.pp_feature & PP_GFXOFF_MASK)
337 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
338 :
339 0 : if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
340 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
341 :
342 0 : if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
343 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
344 :
345 0 : if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
346 : smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
347 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
348 :
349 0 : if (smu->dc_controlled_by_gpio)
350 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
351 :
352 0 : if (amdgpu_device_should_use_aspm(adev))
353 0 : *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
354 :
355 : return 0;
356 : }
357 :
358 0 : static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
359 : {
360 0 : struct smu_table_context *table_context = &smu->smu_table;
361 0 : struct smu_11_0_7_powerplay_table *powerplay_table =
362 : table_context->power_play_table;
363 0 : struct smu_baco_context *smu_baco = &smu->smu_baco;
364 0 : struct amdgpu_device *adev = smu->adev;
365 : uint32_t val;
366 :
367 0 : if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
368 0 : val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
369 0 : smu_baco->platform_support =
370 0 : (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
371 : false;
372 :
373 : /*
374 : * Disable BACO entry/exit completely on below SKUs to
375 : * avoid hardware intermittent failures.
376 : */
377 0 : if (((adev->pdev->device == 0x73A1) &&
378 0 : (adev->pdev->revision == 0x00)) ||
379 0 : ((adev->pdev->device == 0x73BF) &&
380 0 : (adev->pdev->revision == 0xCF)))
381 0 : smu_baco->platform_support = false;
382 :
383 : }
384 0 : }
385 :
386 0 : static void sienna_cichlid_check_fan_support(struct smu_context *smu)
387 : {
388 0 : struct smu_table_context *table_context = &smu->smu_table;
389 0 : PPTable_t *pptable = table_context->driver_pptable;
390 0 : uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
391 :
392 : /* Fan control is not possible if PPTable has it disabled */
393 0 : smu->adev->pm.no_fan =
394 0 : !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
395 0 : if (smu->adev->pm.no_fan)
396 0 : dev_info_once(smu->adev->dev,
397 : "PMFW based fan control disabled");
398 0 : }
399 :
400 0 : static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
401 : {
402 0 : struct smu_table_context *table_context = &smu->smu_table;
403 0 : struct smu_11_0_7_powerplay_table *powerplay_table =
404 : table_context->power_play_table;
405 :
406 0 : if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
407 0 : smu->dc_controlled_by_gpio = true;
408 :
409 0 : sienna_cichlid_check_bxco_support(smu);
410 0 : sienna_cichlid_check_fan_support(smu);
411 :
412 0 : table_context->thermal_controller_type =
413 0 : powerplay_table->thermal_controller_type;
414 :
415 : /*
416 : * Instead of having its own buffer space and get overdrive_table copied,
417 : * smu->od_settings just points to the actual overdrive_table
418 : */
419 0 : smu->od_settings = &powerplay_table->overdrive_table;
420 :
421 0 : return 0;
422 : }
423 :
424 0 : static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
425 : {
426 : struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
427 : int index, ret;
428 : I2cControllerConfig_t *table_member;
429 :
430 0 : index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
431 : smc_dpm_info);
432 :
433 0 : ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
434 : (uint8_t **)&smc_dpm_table);
435 0 : if (ret)
436 : return ret;
437 0 : GET_PPTABLE_MEMBER(I2cControllers, &table_member);
438 0 : memcpy(table_member, smc_dpm_table->I2cControllers,
439 : sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
440 :
441 : return 0;
442 : }
443 :
444 : static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
445 : {
446 0 : struct smu_table_context *table_context = &smu->smu_table;
447 0 : struct smu_11_0_7_powerplay_table *powerplay_table =
448 : table_context->power_play_table;
449 : int table_size;
450 :
451 0 : table_size = get_table_size(smu);
452 0 : memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
453 : table_size);
454 :
455 : return 0;
456 : }
457 :
458 0 : static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
459 : {
460 0 : struct amdgpu_device *adev = smu->adev;
461 : uint32_t *board_reserved;
462 : uint16_t *freq_table_gfx;
463 : uint32_t i;
464 :
465 : /* Fix some OEM SKU specific stability issues */
466 0 : GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
467 0 : if ((adev->pdev->device == 0x73DF) &&
468 0 : (adev->pdev->revision == 0XC3) &&
469 0 : (adev->pdev->subsystem_device == 0x16C2) &&
470 : (adev->pdev->subsystem_vendor == 0x1043))
471 0 : board_reserved[0] = 1387;
472 :
473 0 : GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
474 0 : if ((adev->pdev->device == 0x73DF) &&
475 0 : (adev->pdev->revision == 0XC3) &&
476 0 : ((adev->pdev->subsystem_device == 0x16C2) ||
477 0 : (adev->pdev->subsystem_device == 0x133C)) &&
478 0 : (adev->pdev->subsystem_vendor == 0x1043)) {
479 0 : for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
480 0 : if (freq_table_gfx[i] > 2500)
481 0 : freq_table_gfx[i] = 2500;
482 : }
483 : }
484 :
485 0 : return 0;
486 : }
487 :
488 0 : static int sienna_cichlid_setup_pptable(struct smu_context *smu)
489 : {
490 0 : int ret = 0;
491 :
492 0 : ret = smu_v11_0_setup_pptable(smu);
493 0 : if (ret)
494 : return ret;
495 :
496 0 : ret = sienna_cichlid_store_powerplay_table(smu);
497 : if (ret)
498 : return ret;
499 :
500 0 : ret = sienna_cichlid_append_powerplay_table(smu);
501 0 : if (ret)
502 : return ret;
503 :
504 0 : ret = sienna_cichlid_check_powerplay_table(smu);
505 0 : if (ret)
506 : return ret;
507 :
508 0 : return sienna_cichlid_patch_pptable_quirk(smu);
509 : }
510 :
511 0 : static int sienna_cichlid_tables_init(struct smu_context *smu)
512 : {
513 0 : struct smu_table_context *smu_table = &smu->smu_table;
514 0 : struct smu_table *tables = smu_table->tables;
515 : int table_size;
516 :
517 0 : table_size = get_table_size(smu);
518 0 : SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
519 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
520 0 : SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
521 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
522 0 : SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
523 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
524 0 : SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
525 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
526 0 : SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
527 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
528 0 : SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
529 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
530 0 : SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
531 : sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
532 : AMDGPU_GEM_DOMAIN_VRAM);
533 0 : SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
534 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
535 0 : SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
536 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
537 :
538 0 : smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
539 0 : if (!smu_table->metrics_table)
540 : goto err0_out;
541 0 : smu_table->metrics_time = 0;
542 :
543 0 : smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
544 0 : smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
545 0 : if (!smu_table->gpu_metrics_table)
546 : goto err1_out;
547 :
548 0 : smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
549 0 : if (!smu_table->watermarks_table)
550 : goto err2_out;
551 :
552 0 : smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
553 0 : if (!smu_table->ecc_table)
554 : goto err3_out;
555 :
556 0 : smu_table->driver_smu_config_table =
557 0 : kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
558 0 : if (!smu_table->driver_smu_config_table)
559 : goto err4_out;
560 :
561 : return 0;
562 :
563 : err4_out:
564 0 : kfree(smu_table->ecc_table);
565 : err3_out:
566 0 : kfree(smu_table->watermarks_table);
567 : err2_out:
568 0 : kfree(smu_table->gpu_metrics_table);
569 : err1_out:
570 0 : kfree(smu_table->metrics_table);
571 : err0_out:
572 : return -ENOMEM;
573 : }
574 :
575 0 : static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
576 : {
577 0 : struct smu_table_context *smu_table= &smu->smu_table;
578 0 : SmuMetricsExternal_t *metrics_ext =
579 : (SmuMetricsExternal_t *)(smu_table->metrics_table);
580 0 : uint32_t throttler_status = 0;
581 : int i;
582 :
583 0 : if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
584 0 : (smu->smc_fw_version >= 0x3A4900)) {
585 0 : for (i = 0; i < THROTTLER_COUNT; i++)
586 0 : throttler_status |=
587 0 : (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
588 0 : } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
589 0 : (smu->smc_fw_version >= 0x3A4300)) {
590 0 : for (i = 0; i < THROTTLER_COUNT; i++)
591 0 : throttler_status |=
592 0 : (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
593 : } else {
594 0 : throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
595 : }
596 :
597 0 : return throttler_status;
598 : }
599 :
600 0 : static int sienna_cichlid_get_power_limit(struct smu_context *smu,
601 : uint32_t *current_power_limit,
602 : uint32_t *default_power_limit,
603 : uint32_t *max_power_limit)
604 : {
605 0 : struct smu_11_0_7_powerplay_table *powerplay_table =
606 : (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
607 : uint32_t power_limit, od_percent;
608 : uint16_t *table_member;
609 :
610 0 : GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
611 :
612 0 : if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
613 0 : power_limit =
614 0 : table_member[PPT_THROTTLER_PPT0];
615 : }
616 :
617 0 : if (current_power_limit)
618 0 : *current_power_limit = power_limit;
619 0 : if (default_power_limit)
620 0 : *default_power_limit = power_limit;
621 :
622 0 : if (max_power_limit) {
623 0 : if (smu->od_enabled) {
624 0 : od_percent =
625 : le32_to_cpu(powerplay_table->overdrive_table.max[
626 : SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
627 :
628 : dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
629 : od_percent, power_limit);
630 :
631 0 : power_limit *= (100 + od_percent);
632 0 : power_limit /= 100;
633 : }
634 0 : *max_power_limit = power_limit;
635 : }
636 :
637 0 : return 0;
638 : }
639 :
640 0 : static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
641 : uint32_t *apu_percent,
642 : uint32_t *dgpu_percent)
643 : {
644 0 : struct smu_table_context *smu_table = &smu->smu_table;
645 0 : SmuMetrics_V4_t *metrics_v4 =
646 0 : &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
647 0 : uint16_t powerRatio = 0;
648 0 : uint16_t apu_power_limit = 0;
649 0 : uint16_t dgpu_power_limit = 0;
650 0 : uint32_t apu_boost = 0;
651 0 : uint32_t dgpu_boost = 0;
652 : uint32_t cur_power_limit;
653 :
654 0 : if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
655 0 : sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
656 0 : apu_power_limit = metrics_v4->ApuSTAPMLimit;
657 0 : dgpu_power_limit = cur_power_limit;
658 0 : powerRatio = (((apu_power_limit +
659 0 : dgpu_power_limit) * 100) /
660 0 : metrics_v4->ApuSTAPMSmartShiftLimit);
661 0 : if (powerRatio > 100) {
662 0 : apu_power_limit = (apu_power_limit * 100) /
663 : powerRatio;
664 0 : dgpu_power_limit = (dgpu_power_limit * 100) /
665 : powerRatio;
666 : }
667 0 : if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
668 : apu_power_limit != 0) {
669 0 : apu_boost = ((metrics_v4->AverageApuSocketPower -
670 0 : apu_power_limit) * 100) /
671 : apu_power_limit;
672 0 : if (apu_boost > 100)
673 0 : apu_boost = 100;
674 : }
675 :
676 0 : if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
677 : dgpu_power_limit != 0) {
678 0 : dgpu_boost = ((metrics_v4->AverageSocketPower -
679 0 : dgpu_power_limit) * 100) /
680 : dgpu_power_limit;
681 0 : if (dgpu_boost > 100)
682 0 : dgpu_boost = 100;
683 : }
684 :
685 0 : if (dgpu_boost >= apu_boost)
686 : apu_boost = 0;
687 : else
688 0 : dgpu_boost = 0;
689 : }
690 0 : *apu_percent = apu_boost;
691 0 : *dgpu_percent = dgpu_boost;
692 0 : }
693 :
694 0 : static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
695 : MetricsMember_t member,
696 : uint32_t *value)
697 : {
698 0 : struct smu_table_context *smu_table= &smu->smu_table;
699 0 : SmuMetrics_t *metrics =
700 0 : &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
701 0 : SmuMetrics_V2_t *metrics_v2 =
702 : &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
703 0 : SmuMetrics_V3_t *metrics_v3 =
704 : &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
705 0 : bool use_metrics_v2 = false;
706 0 : bool use_metrics_v3 = false;
707 : uint16_t average_gfx_activity;
708 0 : int ret = 0;
709 0 : uint32_t apu_percent = 0;
710 0 : uint32_t dgpu_percent = 0;
711 :
712 0 : switch (smu->adev->ip_versions[MP1_HWIP][0]) {
713 : case IP_VERSION(11, 0, 7):
714 0 : if (smu->smc_fw_version >= 0x3A4900)
715 : use_metrics_v3 = true;
716 0 : else if (smu->smc_fw_version >= 0x3A4300)
717 0 : use_metrics_v2 = true;
718 : break;
719 : case IP_VERSION(11, 0, 11):
720 0 : if (smu->smc_fw_version >= 0x412D00)
721 0 : use_metrics_v2 = true;
722 : break;
723 : case IP_VERSION(11, 0, 12):
724 0 : if (smu->smc_fw_version >= 0x3B2300)
725 0 : use_metrics_v2 = true;
726 : break;
727 : case IP_VERSION(11, 0, 13):
728 0 : if (smu->smc_fw_version >= 0x491100)
729 0 : use_metrics_v2 = true;
730 : break;
731 : default:
732 : break;
733 : }
734 :
735 0 : ret = smu_cmn_get_metrics_table(smu,
736 : NULL,
737 : false);
738 0 : if (ret)
739 : return ret;
740 :
741 0 : switch (member) {
742 : case METRICS_CURR_GFXCLK:
743 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
744 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
745 : metrics->CurrClock[PPCLK_GFXCLK];
746 0 : break;
747 : case METRICS_CURR_SOCCLK:
748 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
749 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
750 : metrics->CurrClock[PPCLK_SOCCLK];
751 0 : break;
752 : case METRICS_CURR_UCLK:
753 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
754 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
755 : metrics->CurrClock[PPCLK_UCLK];
756 0 : break;
757 : case METRICS_CURR_VCLK:
758 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
759 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
760 : metrics->CurrClock[PPCLK_VCLK_0];
761 0 : break;
762 : case METRICS_CURR_VCLK1:
763 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
764 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
765 : metrics->CurrClock[PPCLK_VCLK_1];
766 0 : break;
767 : case METRICS_CURR_DCLK:
768 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
769 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
770 : metrics->CurrClock[PPCLK_DCLK_0];
771 0 : break;
772 : case METRICS_CURR_DCLK1:
773 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
774 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
775 : metrics->CurrClock[PPCLK_DCLK_1];
776 0 : break;
777 : case METRICS_CURR_DCEFCLK:
778 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
779 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
780 : metrics->CurrClock[PPCLK_DCEFCLK];
781 0 : break;
782 : case METRICS_CURR_FCLK:
783 0 : *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
784 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
785 : metrics->CurrClock[PPCLK_FCLK];
786 0 : break;
787 : case METRICS_AVERAGE_GFXCLK:
788 0 : average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
789 : use_metrics_v2 ? metrics_v2->AverageGfxActivity :
790 : metrics->AverageGfxActivity;
791 0 : if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
792 0 : *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
793 0 : use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
794 0 : metrics->AverageGfxclkFrequencyPostDs;
795 : else
796 0 : *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
797 0 : use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
798 0 : metrics->AverageGfxclkFrequencyPreDs;
799 : break;
800 : case METRICS_AVERAGE_FCLK:
801 0 : *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
802 0 : use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
803 0 : metrics->AverageFclkFrequencyPostDs;
804 0 : break;
805 : case METRICS_AVERAGE_UCLK:
806 0 : *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
807 0 : use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
808 0 : metrics->AverageUclkFrequencyPostDs;
809 0 : break;
810 : case METRICS_AVERAGE_GFXACTIVITY:
811 0 : *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
812 0 : use_metrics_v2 ? metrics_v2->AverageGfxActivity :
813 0 : metrics->AverageGfxActivity;
814 0 : break;
815 : case METRICS_AVERAGE_MEMACTIVITY:
816 0 : *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
817 0 : use_metrics_v2 ? metrics_v2->AverageUclkActivity :
818 0 : metrics->AverageUclkActivity;
819 0 : break;
820 : case METRICS_AVERAGE_SOCKETPOWER:
821 0 : *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
822 0 : use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
823 0 : metrics->AverageSocketPower << 8;
824 0 : break;
825 : case METRICS_TEMPERATURE_EDGE:
826 0 : *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
827 0 : use_metrics_v2 ? metrics_v2->TemperatureEdge :
828 0 : metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
829 0 : break;
830 : case METRICS_TEMPERATURE_HOTSPOT:
831 0 : *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
832 0 : use_metrics_v2 ? metrics_v2->TemperatureHotspot :
833 0 : metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
834 0 : break;
835 : case METRICS_TEMPERATURE_MEM:
836 0 : *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
837 0 : use_metrics_v2 ? metrics_v2->TemperatureMem :
838 0 : metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
839 0 : break;
840 : case METRICS_TEMPERATURE_VRGFX:
841 0 : *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
842 0 : use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
843 0 : metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
844 0 : break;
845 : case METRICS_TEMPERATURE_VRSOC:
846 0 : *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
847 0 : use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
848 0 : metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
849 0 : break;
850 : case METRICS_THROTTLER_STATUS:
851 0 : *value = sienna_cichlid_get_throttler_status_locked(smu);
852 0 : break;
853 : case METRICS_CURR_FANSPEED:
854 0 : *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
855 0 : use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
856 0 : break;
857 : case METRICS_UNIQUE_ID_UPPER32:
858 : /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
859 0 : *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
860 0 : break;
861 : case METRICS_UNIQUE_ID_LOWER32:
862 : /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
863 0 : *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
864 0 : break;
865 : case METRICS_SS_APU_SHARE:
866 0 : sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
867 0 : *value = apu_percent;
868 0 : break;
869 : case METRICS_SS_DGPU_SHARE:
870 0 : sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
871 0 : *value = dgpu_percent;
872 0 : break;
873 :
874 : default:
875 0 : *value = UINT_MAX;
876 0 : break;
877 : }
878 :
879 : return ret;
880 :
881 : }
882 :
883 : static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
884 : {
885 0 : struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
886 :
887 0 : smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
888 : GFP_KERNEL);
889 0 : if (!smu_dpm->dpm_context)
890 : return -ENOMEM;
891 :
892 0 : smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
893 :
894 : return 0;
895 : }
896 :
897 : static void sienna_cichlid_stb_init(struct smu_context *smu);
898 :
899 0 : static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
900 : {
901 0 : struct amdgpu_device *adev = smu->adev;
902 0 : int ret = 0;
903 :
904 0 : ret = sienna_cichlid_tables_init(smu);
905 0 : if (ret)
906 : return ret;
907 :
908 0 : ret = sienna_cichlid_allocate_dpm_context(smu);
909 0 : if (ret)
910 : return ret;
911 :
912 0 : if (!amdgpu_sriov_vf(adev))
913 0 : sienna_cichlid_stb_init(smu);
914 :
915 0 : return smu_v11_0_init_smc_tables(smu);
916 : }
917 :
918 0 : static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
919 : {
920 0 : struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
921 : struct smu_11_0_dpm_table *dpm_table;
922 0 : struct amdgpu_device *adev = smu->adev;
923 0 : int i, ret = 0;
924 : DpmDescriptor_t *table_member;
925 :
926 : /* socclk dpm table setup */
927 0 : dpm_table = &dpm_context->dpm_tables.soc_table;
928 0 : GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
929 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
930 0 : ret = smu_v11_0_set_single_dpm_table(smu,
931 : SMU_SOCCLK,
932 : dpm_table);
933 0 : if (ret)
934 : return ret;
935 0 : dpm_table->is_fine_grained =
936 0 : !table_member[PPCLK_SOCCLK].SnapToDiscrete;
937 : } else {
938 0 : dpm_table->count = 1;
939 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
940 0 : dpm_table->dpm_levels[0].enabled = true;
941 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
942 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
943 : }
944 :
945 : /* gfxclk dpm table setup */
946 0 : dpm_table = &dpm_context->dpm_tables.gfx_table;
947 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
948 0 : ret = smu_v11_0_set_single_dpm_table(smu,
949 : SMU_GFXCLK,
950 : dpm_table);
951 0 : if (ret)
952 : return ret;
953 0 : dpm_table->is_fine_grained =
954 0 : !table_member[PPCLK_GFXCLK].SnapToDiscrete;
955 : } else {
956 0 : dpm_table->count = 1;
957 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
958 0 : dpm_table->dpm_levels[0].enabled = true;
959 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
960 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
961 : }
962 :
963 : /* uclk dpm table setup */
964 0 : dpm_table = &dpm_context->dpm_tables.uclk_table;
965 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
966 0 : ret = smu_v11_0_set_single_dpm_table(smu,
967 : SMU_UCLK,
968 : dpm_table);
969 0 : if (ret)
970 : return ret;
971 0 : dpm_table->is_fine_grained =
972 0 : !table_member[PPCLK_UCLK].SnapToDiscrete;
973 : } else {
974 0 : dpm_table->count = 1;
975 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
976 0 : dpm_table->dpm_levels[0].enabled = true;
977 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
978 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
979 : }
980 :
981 : /* fclk dpm table setup */
982 0 : dpm_table = &dpm_context->dpm_tables.fclk_table;
983 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
984 0 : ret = smu_v11_0_set_single_dpm_table(smu,
985 : SMU_FCLK,
986 : dpm_table);
987 0 : if (ret)
988 : return ret;
989 0 : dpm_table->is_fine_grained =
990 0 : !table_member[PPCLK_FCLK].SnapToDiscrete;
991 : } else {
992 0 : dpm_table->count = 1;
993 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
994 0 : dpm_table->dpm_levels[0].enabled = true;
995 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
996 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
997 : }
998 :
999 : /* vclk0/1 dpm table setup */
1000 0 : for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1001 0 : if (adev->vcn.harvest_config & (1 << i))
1002 0 : continue;
1003 :
1004 0 : dpm_table = &dpm_context->dpm_tables.vclk_table;
1005 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1006 0 : ret = smu_v11_0_set_single_dpm_table(smu,
1007 : i ? SMU_VCLK1 : SMU_VCLK,
1008 : dpm_table);
1009 0 : if (ret)
1010 : return ret;
1011 0 : dpm_table->is_fine_grained =
1012 0 : !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1013 : } else {
1014 0 : dpm_table->count = 1;
1015 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1016 0 : dpm_table->dpm_levels[0].enabled = true;
1017 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
1018 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
1019 : }
1020 : }
1021 :
1022 : /* dclk0/1 dpm table setup */
1023 0 : for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1024 0 : if (adev->vcn.harvest_config & (1 << i))
1025 0 : continue;
1026 0 : dpm_table = &dpm_context->dpm_tables.dclk_table;
1027 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1028 0 : ret = smu_v11_0_set_single_dpm_table(smu,
1029 : i ? SMU_DCLK1 : SMU_DCLK,
1030 : dpm_table);
1031 0 : if (ret)
1032 : return ret;
1033 0 : dpm_table->is_fine_grained =
1034 0 : !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1035 : } else {
1036 0 : dpm_table->count = 1;
1037 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1038 0 : dpm_table->dpm_levels[0].enabled = true;
1039 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
1040 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
1041 : }
1042 : }
1043 :
1044 : /* dcefclk dpm table setup */
1045 0 : dpm_table = &dpm_context->dpm_tables.dcef_table;
1046 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1047 0 : ret = smu_v11_0_set_single_dpm_table(smu,
1048 : SMU_DCEFCLK,
1049 : dpm_table);
1050 0 : if (ret)
1051 : return ret;
1052 0 : dpm_table->is_fine_grained =
1053 0 : !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1054 : } else {
1055 0 : dpm_table->count = 1;
1056 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1057 0 : dpm_table->dpm_levels[0].enabled = true;
1058 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
1059 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
1060 : }
1061 :
1062 : /* pixelclk dpm table setup */
1063 0 : dpm_table = &dpm_context->dpm_tables.pixel_table;
1064 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1065 0 : ret = smu_v11_0_set_single_dpm_table(smu,
1066 : SMU_PIXCLK,
1067 : dpm_table);
1068 0 : if (ret)
1069 : return ret;
1070 0 : dpm_table->is_fine_grained =
1071 0 : !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1072 : } else {
1073 0 : dpm_table->count = 1;
1074 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1075 0 : dpm_table->dpm_levels[0].enabled = true;
1076 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
1077 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
1078 : }
1079 :
1080 : /* displayclk dpm table setup */
1081 0 : dpm_table = &dpm_context->dpm_tables.display_table;
1082 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1083 0 : ret = smu_v11_0_set_single_dpm_table(smu,
1084 : SMU_DISPCLK,
1085 : dpm_table);
1086 0 : if (ret)
1087 : return ret;
1088 0 : dpm_table->is_fine_grained =
1089 0 : !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1090 : } else {
1091 0 : dpm_table->count = 1;
1092 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1093 0 : dpm_table->dpm_levels[0].enabled = true;
1094 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
1095 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
1096 : }
1097 :
1098 : /* phyclk dpm table setup */
1099 0 : dpm_table = &dpm_context->dpm_tables.phy_table;
1100 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1101 0 : ret = smu_v11_0_set_single_dpm_table(smu,
1102 : SMU_PHYCLK,
1103 : dpm_table);
1104 0 : if (ret)
1105 : return ret;
1106 0 : dpm_table->is_fine_grained =
1107 0 : !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1108 : } else {
1109 0 : dpm_table->count = 1;
1110 0 : dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1111 0 : dpm_table->dpm_levels[0].enabled = true;
1112 0 : dpm_table->min = dpm_table->dpm_levels[0].value;
1113 0 : dpm_table->max = dpm_table->dpm_levels[0].value;
1114 : }
1115 :
1116 : return 0;
1117 : }
1118 :
1119 0 : static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1120 : {
1121 0 : struct amdgpu_device *adev = smu->adev;
1122 0 : int i, ret = 0;
1123 :
1124 0 : for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1125 0 : if (adev->vcn.harvest_config & (1 << i))
1126 0 : continue;
1127 : /* vcn dpm on is a prerequisite for vcn power gate messages */
1128 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1129 0 : ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1130 : SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1131 0 : 0x10000 * i, NULL);
1132 0 : if (ret)
1133 : return ret;
1134 : }
1135 : }
1136 :
1137 : return ret;
1138 : }
1139 :
1140 0 : static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1141 : {
1142 0 : int ret = 0;
1143 :
1144 0 : if (enable) {
1145 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1146 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1147 0 : if (ret)
1148 : return ret;
1149 : }
1150 : } else {
1151 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1152 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1153 0 : if (ret)
1154 : return ret;
1155 : }
1156 : }
1157 :
1158 : return ret;
1159 : }
1160 :
1161 0 : static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1162 : enum smu_clk_type clk_type,
1163 : uint32_t *value)
1164 : {
1165 : MetricsMember_t member_type;
1166 0 : int clk_id = 0;
1167 :
1168 0 : clk_id = smu_cmn_to_asic_specific_index(smu,
1169 : CMN2ASIC_MAPPING_CLK,
1170 : clk_type);
1171 0 : if (clk_id < 0)
1172 : return clk_id;
1173 :
1174 0 : switch (clk_id) {
1175 : case PPCLK_GFXCLK:
1176 : member_type = METRICS_CURR_GFXCLK;
1177 : break;
1178 : case PPCLK_UCLK:
1179 0 : member_type = METRICS_CURR_UCLK;
1180 0 : break;
1181 : case PPCLK_SOCCLK:
1182 0 : member_type = METRICS_CURR_SOCCLK;
1183 0 : break;
1184 : case PPCLK_FCLK:
1185 0 : member_type = METRICS_CURR_FCLK;
1186 0 : break;
1187 : case PPCLK_VCLK_0:
1188 0 : member_type = METRICS_CURR_VCLK;
1189 0 : break;
1190 : case PPCLK_VCLK_1:
1191 0 : member_type = METRICS_CURR_VCLK1;
1192 0 : break;
1193 : case PPCLK_DCLK_0:
1194 0 : member_type = METRICS_CURR_DCLK;
1195 0 : break;
1196 : case PPCLK_DCLK_1:
1197 0 : member_type = METRICS_CURR_DCLK1;
1198 0 : break;
1199 : case PPCLK_DCEFCLK:
1200 0 : member_type = METRICS_CURR_DCEFCLK;
1201 0 : break;
1202 : default:
1203 : return -EINVAL;
1204 : }
1205 :
1206 0 : return sienna_cichlid_get_smu_metrics_data(smu,
1207 : member_type,
1208 : value);
1209 :
1210 : }
1211 :
1212 0 : static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1213 : {
1214 0 : DpmDescriptor_t *dpm_desc = NULL;
1215 : DpmDescriptor_t *table_member;
1216 0 : uint32_t clk_index = 0;
1217 :
1218 0 : GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1219 0 : clk_index = smu_cmn_to_asic_specific_index(smu,
1220 : CMN2ASIC_MAPPING_CLK,
1221 : clk_type);
1222 0 : dpm_desc = &table_member[clk_index];
1223 :
1224 : /* 0 - Fine grained DPM, 1 - Discrete DPM */
1225 0 : return dpm_desc->SnapToDiscrete == 0;
1226 : }
1227 :
1228 : static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1229 : enum SMU_11_0_7_ODFEATURE_CAP cap)
1230 : {
1231 0 : return od_table->cap[cap];
1232 : }
1233 :
1234 : static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1235 : enum SMU_11_0_7_ODSETTING_ID setting,
1236 : uint32_t *min, uint32_t *max)
1237 : {
1238 : if (min)
1239 0 : *min = od_table->min[setting];
1240 : if (max)
1241 0 : *max = od_table->max[setting];
1242 : }
1243 :
1244 0 : static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1245 : enum smu_clk_type clk_type, char *buf)
1246 : {
1247 0 : struct amdgpu_device *adev = smu->adev;
1248 0 : struct smu_table_context *table_context = &smu->smu_table;
1249 0 : struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1250 0 : struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1251 : uint16_t *table_member;
1252 :
1253 0 : struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1254 0 : OverDriveTable_t *od_table =
1255 : (OverDriveTable_t *)table_context->overdrive_table;
1256 0 : int i, size = 0, ret = 0;
1257 0 : uint32_t cur_value = 0, value = 0, count = 0;
1258 0 : uint32_t freq_values[3] = {0};
1259 0 : uint32_t mark_index = 0;
1260 : uint32_t gen_speed, lane_width;
1261 : uint32_t min_value, max_value;
1262 : uint32_t smu_version;
1263 :
1264 0 : smu_cmn_get_sysfs_buf(&buf, &size);
1265 :
1266 0 : switch (clk_type) {
1267 : case SMU_GFXCLK:
1268 : case SMU_SCLK:
1269 : case SMU_SOCCLK:
1270 : case SMU_MCLK:
1271 : case SMU_UCLK:
1272 : case SMU_FCLK:
1273 : case SMU_VCLK:
1274 : case SMU_VCLK1:
1275 : case SMU_DCLK:
1276 : case SMU_DCLK1:
1277 : case SMU_DCEFCLK:
1278 0 : ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1279 0 : if (ret)
1280 : goto print_clk_out;
1281 :
1282 0 : ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1283 0 : if (ret)
1284 : goto print_clk_out;
1285 :
1286 0 : if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1287 0 : for (i = 0; i < count; i++) {
1288 0 : ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1289 0 : if (ret)
1290 : goto print_clk_out;
1291 :
1292 0 : size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1293 0 : cur_value == value ? "*" : "");
1294 : }
1295 : } else {
1296 0 : ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1297 0 : if (ret)
1298 : goto print_clk_out;
1299 0 : ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1300 0 : if (ret)
1301 : goto print_clk_out;
1302 :
1303 0 : freq_values[1] = cur_value;
1304 0 : mark_index = cur_value == freq_values[0] ? 0 :
1305 0 : cur_value == freq_values[2] ? 2 : 1;
1306 :
1307 0 : count = 3;
1308 0 : if (mark_index != 1) {
1309 0 : count = 2;
1310 0 : freq_values[1] = freq_values[2];
1311 : }
1312 :
1313 0 : for (i = 0; i < count; i++) {
1314 0 : size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1315 0 : cur_value == freq_values[i] ? "*" : "");
1316 : }
1317 :
1318 : }
1319 : break;
1320 : case SMU_PCIE:
1321 0 : gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1322 0 : lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1323 0 : GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1324 0 : for (i = 0; i < NUM_LINK_LEVELS; i++)
1325 0 : size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1326 : (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1327 0 : (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1328 0 : (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1329 0 : (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1330 0 : (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1331 0 : (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1332 0 : (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1333 0 : (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1334 0 : (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1335 0 : (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1336 0 : table_member[i],
1337 0 : (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1338 0 : (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1339 : "*" : "");
1340 : break;
1341 : case SMU_OD_SCLK:
1342 0 : if (!smu->od_enabled || !od_table || !od_settings)
1343 : break;
1344 :
1345 0 : if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1346 : break;
1347 :
1348 0 : size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1349 0 : size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1350 0 : break;
1351 :
1352 : case SMU_OD_MCLK:
1353 0 : if (!smu->od_enabled || !od_table || !od_settings)
1354 : break;
1355 :
1356 0 : if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1357 : break;
1358 :
1359 0 : size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1360 0 : size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1361 0 : break;
1362 :
1363 : case SMU_OD_VDDGFX_OFFSET:
1364 0 : if (!smu->od_enabled || !od_table || !od_settings)
1365 : break;
1366 :
1367 : /*
1368 : * OD GFX Voltage Offset functionality is supported only by 58.41.0
1369 : * and onwards SMU firmwares.
1370 : */
1371 0 : smu_cmn_get_smc_version(smu, NULL, &smu_version);
1372 0 : if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
1373 0 : (smu_version < 0x003a2900))
1374 : break;
1375 :
1376 0 : size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1377 0 : size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1378 0 : break;
1379 :
1380 : case SMU_OD_RANGE:
1381 0 : if (!smu->od_enabled || !od_table || !od_settings)
1382 : break;
1383 :
1384 0 : size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1385 :
1386 0 : if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1387 0 : sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1388 : &min_value, NULL);
1389 0 : sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1390 : NULL, &max_value);
1391 0 : size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1392 : min_value, max_value);
1393 : }
1394 :
1395 0 : if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1396 0 : sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1397 : &min_value, NULL);
1398 0 : sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1399 : NULL, &max_value);
1400 0 : size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1401 : min_value, max_value);
1402 : }
1403 : break;
1404 :
1405 : default:
1406 : break;
1407 : }
1408 :
1409 : print_clk_out:
1410 0 : return size;
1411 : }
1412 :
1413 0 : static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1414 : enum smu_clk_type clk_type, uint32_t mask)
1415 : {
1416 0 : int ret = 0;
1417 0 : uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1418 :
1419 0 : soft_min_level = mask ? (ffs(mask) - 1) : 0;
1420 0 : soft_max_level = mask ? (fls(mask) - 1) : 0;
1421 :
1422 : switch (clk_type) {
1423 : case SMU_GFXCLK:
1424 : case SMU_SCLK:
1425 : case SMU_SOCCLK:
1426 : case SMU_MCLK:
1427 : case SMU_UCLK:
1428 : case SMU_FCLK:
1429 : /* There is only 2 levels for fine grained DPM */
1430 0 : if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1431 0 : soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1432 0 : soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1433 : }
1434 :
1435 0 : ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1436 0 : if (ret)
1437 : goto forec_level_out;
1438 :
1439 0 : ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1440 0 : if (ret)
1441 : goto forec_level_out;
1442 :
1443 0 : ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1444 : if (ret)
1445 : goto forec_level_out;
1446 : break;
1447 : case SMU_DCEFCLK:
1448 0 : dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1449 0 : break;
1450 : default:
1451 : break;
1452 : }
1453 :
1454 : forec_level_out:
1455 0 : return 0;
1456 : }
1457 :
1458 0 : static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1459 : {
1460 0 : struct smu_11_0_dpm_context *dpm_context =
1461 : smu->smu_dpm.dpm_context;
1462 0 : struct smu_11_0_dpm_table *gfx_table =
1463 : &dpm_context->dpm_tables.gfx_table;
1464 0 : struct smu_11_0_dpm_table *mem_table =
1465 : &dpm_context->dpm_tables.uclk_table;
1466 0 : struct smu_11_0_dpm_table *soc_table =
1467 : &dpm_context->dpm_tables.soc_table;
1468 0 : struct smu_umd_pstate_table *pstate_table =
1469 : &smu->pstate_table;
1470 0 : struct amdgpu_device *adev = smu->adev;
1471 :
1472 0 : pstate_table->gfxclk_pstate.min = gfx_table->min;
1473 0 : pstate_table->gfxclk_pstate.peak = gfx_table->max;
1474 :
1475 0 : pstate_table->uclk_pstate.min = mem_table->min;
1476 0 : pstate_table->uclk_pstate.peak = mem_table->max;
1477 :
1478 0 : pstate_table->socclk_pstate.min = soc_table->min;
1479 0 : pstate_table->socclk_pstate.peak = soc_table->max;
1480 :
1481 0 : switch (adev->ip_versions[MP1_HWIP][0]) {
1482 : case IP_VERSION(11, 0, 7):
1483 : case IP_VERSION(11, 0, 11):
1484 0 : pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1485 0 : pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1486 0 : pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1487 0 : break;
1488 : case IP_VERSION(11, 0, 12):
1489 0 : pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1490 0 : pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1491 0 : pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1492 0 : break;
1493 : case IP_VERSION(11, 0, 13):
1494 0 : pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1495 0 : pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1496 0 : pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1497 0 : break;
1498 : default:
1499 : break;
1500 : }
1501 :
1502 0 : return 0;
1503 : }
1504 :
1505 0 : static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1506 : {
1507 0 : int ret = 0;
1508 0 : uint32_t max_freq = 0;
1509 :
1510 : /* Sienna_Cichlid do not support to change display num currently */
1511 : return 0;
1512 : #if 0
1513 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1514 : if (ret)
1515 : return ret;
1516 : #endif
1517 :
1518 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1519 : ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1520 : if (ret)
1521 : return ret;
1522 : ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1523 : if (ret)
1524 : return ret;
1525 : }
1526 :
1527 : return ret;
1528 : }
1529 :
1530 0 : static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1531 : {
1532 0 : int ret = 0;
1533 :
1534 0 : if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1535 0 : smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1536 0 : smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1537 : #if 0
1538 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1539 : smu->display_config->num_display,
1540 : NULL);
1541 : #endif
1542 : if (ret)
1543 : return ret;
1544 : }
1545 :
1546 : return ret;
1547 : }
1548 :
1549 0 : static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1550 : {
1551 0 : int ret = 0;
1552 : uint64_t feature_enabled;
1553 :
1554 0 : ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1555 0 : if (ret)
1556 : return false;
1557 :
1558 0 : return !!(feature_enabled & SMC_DPM_FEATURE);
1559 : }
1560 :
1561 0 : static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1562 : uint32_t *speed)
1563 : {
1564 0 : if (!speed)
1565 : return -EINVAL;
1566 :
1567 : /*
1568 : * For Sienna_Cichlid and later, the fan speed(rpm) reported
1569 : * by pmfw is always trustable(even when the fan control feature
1570 : * disabled or 0 RPM kicked in).
1571 : */
1572 0 : return sienna_cichlid_get_smu_metrics_data(smu,
1573 : METRICS_CURR_FANSPEED,
1574 : speed);
1575 : }
1576 :
1577 0 : static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1578 : {
1579 : uint16_t *table_member;
1580 :
1581 0 : GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1582 0 : smu->fan_max_rpm = *table_member;
1583 :
1584 0 : return 0;
1585 : }
1586 :
1587 0 : static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1588 : {
1589 : DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1590 0 : DpmActivityMonitorCoeffInt_t *activity_monitor =
1591 : &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1592 0 : uint32_t i, size = 0;
1593 0 : int16_t workload_type = 0;
1594 : static const char *title[] = {
1595 : "PROFILE_INDEX(NAME)",
1596 : "CLOCK_TYPE(NAME)",
1597 : "FPS",
1598 : "MinFreqType",
1599 : "MinActiveFreqType",
1600 : "MinActiveFreq",
1601 : "BoosterFreqType",
1602 : "BoosterFreq",
1603 : "PD_Data_limit_c",
1604 : "PD_Data_error_coeff",
1605 : "PD_Data_error_rate_coeff"};
1606 0 : int result = 0;
1607 :
1608 0 : if (!buf)
1609 : return -EINVAL;
1610 :
1611 0 : size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1612 : title[0], title[1], title[2], title[3], title[4], title[5],
1613 : title[6], title[7], title[8], title[9], title[10]);
1614 :
1615 0 : for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1616 : /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1617 0 : workload_type = smu_cmn_to_asic_specific_index(smu,
1618 : CMN2ASIC_MAPPING_WORKLOAD,
1619 : i);
1620 0 : if (workload_type < 0)
1621 : return -EINVAL;
1622 :
1623 0 : result = smu_cmn_update_table(smu,
1624 : SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1625 : (void *)(&activity_monitor_external), false);
1626 0 : if (result) {
1627 0 : dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1628 0 : return result;
1629 : }
1630 :
1631 0 : size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1632 0 : i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1633 :
1634 0 : size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1635 : " ",
1636 : 0,
1637 : "GFXCLK",
1638 0 : activity_monitor->Gfx_FPS,
1639 0 : activity_monitor->Gfx_MinFreqStep,
1640 0 : activity_monitor->Gfx_MinActiveFreqType,
1641 0 : activity_monitor->Gfx_MinActiveFreq,
1642 0 : activity_monitor->Gfx_BoosterFreqType,
1643 0 : activity_monitor->Gfx_BoosterFreq,
1644 : activity_monitor->Gfx_PD_Data_limit_c,
1645 : activity_monitor->Gfx_PD_Data_error_coeff,
1646 : activity_monitor->Gfx_PD_Data_error_rate_coeff);
1647 :
1648 0 : size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1649 : " ",
1650 : 1,
1651 : "SOCCLK",
1652 0 : activity_monitor->Fclk_FPS,
1653 0 : activity_monitor->Fclk_MinFreqStep,
1654 0 : activity_monitor->Fclk_MinActiveFreqType,
1655 0 : activity_monitor->Fclk_MinActiveFreq,
1656 0 : activity_monitor->Fclk_BoosterFreqType,
1657 0 : activity_monitor->Fclk_BoosterFreq,
1658 : activity_monitor->Fclk_PD_Data_limit_c,
1659 : activity_monitor->Fclk_PD_Data_error_coeff,
1660 : activity_monitor->Fclk_PD_Data_error_rate_coeff);
1661 :
1662 0 : size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1663 : " ",
1664 : 2,
1665 : "MEMLK",
1666 0 : activity_monitor->Mem_FPS,
1667 0 : activity_monitor->Mem_MinFreqStep,
1668 0 : activity_monitor->Mem_MinActiveFreqType,
1669 0 : activity_monitor->Mem_MinActiveFreq,
1670 0 : activity_monitor->Mem_BoosterFreqType,
1671 0 : activity_monitor->Mem_BoosterFreq,
1672 : activity_monitor->Mem_PD_Data_limit_c,
1673 : activity_monitor->Mem_PD_Data_error_coeff,
1674 : activity_monitor->Mem_PD_Data_error_rate_coeff);
1675 : }
1676 :
1677 0 : return size;
1678 : }
1679 :
1680 0 : static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1681 : {
1682 :
1683 : DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1684 0 : DpmActivityMonitorCoeffInt_t *activity_monitor =
1685 : &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1686 0 : int workload_type, ret = 0;
1687 :
1688 0 : smu->power_profile_mode = input[size];
1689 :
1690 0 : if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1691 0 : dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1692 0 : return -EINVAL;
1693 : }
1694 :
1695 0 : if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1696 :
1697 0 : ret = smu_cmn_update_table(smu,
1698 : SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1699 : (void *)(&activity_monitor_external), false);
1700 0 : if (ret) {
1701 0 : dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1702 0 : return ret;
1703 : }
1704 :
1705 0 : switch (input[0]) {
1706 : case 0: /* Gfxclk */
1707 0 : activity_monitor->Gfx_FPS = input[1];
1708 0 : activity_monitor->Gfx_MinFreqStep = input[2];
1709 0 : activity_monitor->Gfx_MinActiveFreqType = input[3];
1710 0 : activity_monitor->Gfx_MinActiveFreq = input[4];
1711 0 : activity_monitor->Gfx_BoosterFreqType = input[5];
1712 0 : activity_monitor->Gfx_BoosterFreq = input[6];
1713 0 : activity_monitor->Gfx_PD_Data_limit_c = input[7];
1714 0 : activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1715 0 : activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1716 0 : break;
1717 : case 1: /* Socclk */
1718 0 : activity_monitor->Fclk_FPS = input[1];
1719 0 : activity_monitor->Fclk_MinFreqStep = input[2];
1720 0 : activity_monitor->Fclk_MinActiveFreqType = input[3];
1721 0 : activity_monitor->Fclk_MinActiveFreq = input[4];
1722 0 : activity_monitor->Fclk_BoosterFreqType = input[5];
1723 0 : activity_monitor->Fclk_BoosterFreq = input[6];
1724 0 : activity_monitor->Fclk_PD_Data_limit_c = input[7];
1725 0 : activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1726 0 : activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1727 0 : break;
1728 : case 2: /* Memlk */
1729 0 : activity_monitor->Mem_FPS = input[1];
1730 0 : activity_monitor->Mem_MinFreqStep = input[2];
1731 0 : activity_monitor->Mem_MinActiveFreqType = input[3];
1732 0 : activity_monitor->Mem_MinActiveFreq = input[4];
1733 0 : activity_monitor->Mem_BoosterFreqType = input[5];
1734 0 : activity_monitor->Mem_BoosterFreq = input[6];
1735 0 : activity_monitor->Mem_PD_Data_limit_c = input[7];
1736 0 : activity_monitor->Mem_PD_Data_error_coeff = input[8];
1737 0 : activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1738 0 : break;
1739 : }
1740 :
1741 0 : ret = smu_cmn_update_table(smu,
1742 : SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1743 : (void *)(&activity_monitor_external), true);
1744 0 : if (ret) {
1745 0 : dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1746 0 : return ret;
1747 : }
1748 : }
1749 :
1750 : /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1751 0 : workload_type = smu_cmn_to_asic_specific_index(smu,
1752 : CMN2ASIC_MAPPING_WORKLOAD,
1753 : smu->power_profile_mode);
1754 0 : if (workload_type < 0)
1755 : return -EINVAL;
1756 0 : smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1757 0 : 1 << workload_type, NULL);
1758 :
1759 0 : return ret;
1760 : }
1761 :
1762 0 : static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1763 : {
1764 0 : struct smu_clocks min_clocks = {0};
1765 : struct pp_display_clock_request clock_req;
1766 0 : int ret = 0;
1767 :
1768 0 : min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1769 0 : min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1770 0 : min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1771 :
1772 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1773 0 : clock_req.clock_type = amd_pp_dcef_clock;
1774 0 : clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1775 :
1776 0 : ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1777 0 : if (!ret) {
1778 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1779 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
1780 : SMU_MSG_SetMinDeepSleepDcefclk,
1781 : min_clocks.dcef_clock_in_sr/100,
1782 : NULL);
1783 0 : if (ret) {
1784 0 : dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1785 0 : return ret;
1786 : }
1787 : }
1788 : } else {
1789 0 : dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1790 : }
1791 : }
1792 :
1793 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1794 0 : ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1795 0 : if (ret) {
1796 0 : dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1797 0 : return ret;
1798 : }
1799 : }
1800 :
1801 : return 0;
1802 : }
1803 :
1804 0 : static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1805 : struct pp_smu_wm_range_sets *clock_ranges)
1806 : {
1807 0 : Watermarks_t *table = smu->smu_table.watermarks_table;
1808 0 : int ret = 0;
1809 : int i;
1810 :
1811 0 : if (clock_ranges) {
1812 0 : if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1813 0 : clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1814 : return -EINVAL;
1815 :
1816 0 : for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1817 0 : table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1818 0 : clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1819 0 : table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1820 0 : clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1821 0 : table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1822 0 : clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1823 0 : table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1824 0 : clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1825 :
1826 0 : table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1827 0 : clock_ranges->reader_wm_sets[i].wm_inst;
1828 : }
1829 :
1830 0 : for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1831 0 : table->WatermarkRow[WM_SOCCLK][i].MinClock =
1832 0 : clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1833 0 : table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1834 0 : clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1835 0 : table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1836 0 : clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1837 0 : table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1838 0 : clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1839 :
1840 0 : table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1841 0 : clock_ranges->writer_wm_sets[i].wm_inst;
1842 : }
1843 :
1844 0 : smu->watermarks_bitmap |= WATERMARKS_EXIST;
1845 : }
1846 :
1847 0 : if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1848 : !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1849 0 : ret = smu_cmn_write_watermarks_table(smu);
1850 0 : if (ret) {
1851 0 : dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1852 0 : return ret;
1853 : }
1854 0 : smu->watermarks_bitmap |= WATERMARKS_LOADED;
1855 : }
1856 :
1857 : return 0;
1858 : }
1859 :
1860 0 : static int sienna_cichlid_read_sensor(struct smu_context *smu,
1861 : enum amd_pp_sensors sensor,
1862 : void *data, uint32_t *size)
1863 : {
1864 0 : int ret = 0;
1865 : uint16_t *temp;
1866 0 : struct amdgpu_device *adev = smu->adev;
1867 :
1868 0 : if(!data || !size)
1869 : return -EINVAL;
1870 :
1871 0 : switch (sensor) {
1872 : case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1873 0 : GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1874 0 : *(uint16_t *)data = *temp;
1875 0 : *size = 4;
1876 0 : break;
1877 : case AMDGPU_PP_SENSOR_MEM_LOAD:
1878 0 : ret = sienna_cichlid_get_smu_metrics_data(smu,
1879 : METRICS_AVERAGE_MEMACTIVITY,
1880 : (uint32_t *)data);
1881 0 : *size = 4;
1882 0 : break;
1883 : case AMDGPU_PP_SENSOR_GPU_LOAD:
1884 0 : ret = sienna_cichlid_get_smu_metrics_data(smu,
1885 : METRICS_AVERAGE_GFXACTIVITY,
1886 : (uint32_t *)data);
1887 0 : *size = 4;
1888 0 : break;
1889 : case AMDGPU_PP_SENSOR_GPU_POWER:
1890 0 : ret = sienna_cichlid_get_smu_metrics_data(smu,
1891 : METRICS_AVERAGE_SOCKETPOWER,
1892 : (uint32_t *)data);
1893 0 : *size = 4;
1894 0 : break;
1895 : case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1896 0 : ret = sienna_cichlid_get_smu_metrics_data(smu,
1897 : METRICS_TEMPERATURE_HOTSPOT,
1898 : (uint32_t *)data);
1899 0 : *size = 4;
1900 0 : break;
1901 : case AMDGPU_PP_SENSOR_EDGE_TEMP:
1902 0 : ret = sienna_cichlid_get_smu_metrics_data(smu,
1903 : METRICS_TEMPERATURE_EDGE,
1904 : (uint32_t *)data);
1905 0 : *size = 4;
1906 0 : break;
1907 : case AMDGPU_PP_SENSOR_MEM_TEMP:
1908 0 : ret = sienna_cichlid_get_smu_metrics_data(smu,
1909 : METRICS_TEMPERATURE_MEM,
1910 : (uint32_t *)data);
1911 0 : *size = 4;
1912 0 : break;
1913 : case AMDGPU_PP_SENSOR_GFX_MCLK:
1914 0 : ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1915 0 : *(uint32_t *)data *= 100;
1916 0 : *size = 4;
1917 0 : break;
1918 : case AMDGPU_PP_SENSOR_GFX_SCLK:
1919 0 : ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1920 0 : *(uint32_t *)data *= 100;
1921 0 : *size = 4;
1922 0 : break;
1923 : case AMDGPU_PP_SENSOR_VDDGFX:
1924 0 : ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1925 0 : *size = 4;
1926 0 : break;
1927 : case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1928 0 : if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1929 0 : ret = sienna_cichlid_get_smu_metrics_data(smu,
1930 : METRICS_SS_APU_SHARE, (uint32_t *)data);
1931 0 : *size = 4;
1932 : } else {
1933 : ret = -EOPNOTSUPP;
1934 : }
1935 : break;
1936 : case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1937 0 : if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1938 0 : ret = sienna_cichlid_get_smu_metrics_data(smu,
1939 : METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1940 0 : *size = 4;
1941 : } else {
1942 : ret = -EOPNOTSUPP;
1943 : }
1944 : break;
1945 : default:
1946 : ret = -EOPNOTSUPP;
1947 : break;
1948 : }
1949 :
1950 : return ret;
1951 : }
1952 :
1953 0 : static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1954 : {
1955 0 : struct amdgpu_device *adev = smu->adev;
1956 0 : uint32_t upper32 = 0, lower32 = 0;
1957 :
1958 : /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1959 0 : if (smu->smc_fw_version < 0x3A5300 ||
1960 0 : smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1961 0 : return;
1962 :
1963 0 : if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1964 : goto out;
1965 0 : if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1966 : goto out;
1967 :
1968 : out:
1969 :
1970 0 : adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1971 0 : if (adev->serial[0] == '\0')
1972 0 : sprintf(adev->serial, "%016llx", adev->unique_id);
1973 : }
1974 :
1975 0 : static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1976 : {
1977 0 : uint32_t num_discrete_levels = 0;
1978 0 : uint16_t *dpm_levels = NULL;
1979 0 : uint16_t i = 0;
1980 0 : struct smu_table_context *table_context = &smu->smu_table;
1981 : DpmDescriptor_t *table_member1;
1982 : uint16_t *table_member2;
1983 :
1984 0 : if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1985 : return -EINVAL;
1986 :
1987 0 : GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1988 0 : num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1989 0 : GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1990 0 : dpm_levels = table_member2;
1991 :
1992 0 : if (num_discrete_levels == 0 || dpm_levels == NULL)
1993 : return -EINVAL;
1994 :
1995 0 : *num_states = num_discrete_levels;
1996 0 : for (i = 0; i < num_discrete_levels; i++) {
1997 : /* convert to khz */
1998 0 : *clocks_in_khz = (*dpm_levels) * 1000;
1999 0 : clocks_in_khz++;
2000 0 : dpm_levels++;
2001 : }
2002 :
2003 : return 0;
2004 : }
2005 :
2006 0 : static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2007 : struct smu_temperature_range *range)
2008 : {
2009 0 : struct smu_table_context *table_context = &smu->smu_table;
2010 0 : struct smu_11_0_7_powerplay_table *powerplay_table =
2011 : table_context->power_play_table;
2012 : uint16_t *table_member;
2013 : uint16_t temp_edge, temp_hotspot, temp_mem;
2014 :
2015 0 : if (!range)
2016 : return -EINVAL;
2017 :
2018 0 : memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2019 :
2020 0 : GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2021 0 : temp_edge = table_member[TEMP_EDGE];
2022 0 : temp_hotspot = table_member[TEMP_HOTSPOT];
2023 0 : temp_mem = table_member[TEMP_MEM];
2024 :
2025 0 : range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2026 0 : range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2027 : SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2028 0 : range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2029 0 : range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2030 : SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2031 0 : range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2032 0 : range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2033 : SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2034 :
2035 0 : range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2036 :
2037 0 : return 0;
2038 : }
2039 :
2040 0 : static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2041 : bool disable_memory_clock_switch)
2042 : {
2043 0 : int ret = 0;
2044 0 : struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2045 : (struct smu_11_0_max_sustainable_clocks *)
2046 : smu->smu_table.max_sustainable_clocks;
2047 0 : uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2048 0 : uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2049 :
2050 0 : if(smu->disable_uclk_switch == disable_memory_clock_switch)
2051 : return 0;
2052 :
2053 0 : if(disable_memory_clock_switch)
2054 0 : ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2055 : else
2056 0 : ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2057 :
2058 0 : if(!ret)
2059 0 : smu->disable_uclk_switch = disable_memory_clock_switch;
2060 :
2061 : return ret;
2062 : }
2063 :
2064 0 : static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2065 : uint32_t pcie_gen_cap,
2066 : uint32_t pcie_width_cap)
2067 : {
2068 0 : struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2069 :
2070 : uint32_t smu_pcie_arg;
2071 : uint8_t *table_member1, *table_member2;
2072 : int ret, i;
2073 :
2074 0 : GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2075 0 : GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2076 :
2077 : /* lclk dpm table setup */
2078 0 : for (i = 0; i < MAX_PCIE_CONF; i++) {
2079 0 : dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
2080 0 : dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
2081 : }
2082 :
2083 0 : for (i = 0; i < NUM_LINK_LEVELS; i++) {
2084 0 : smu_pcie_arg = (i << 16) |
2085 0 : ((table_member1[i] <= pcie_gen_cap) ?
2086 0 : (table_member1[i] << 8) :
2087 : (pcie_gen_cap << 8)) |
2088 : ((table_member2[i] <= pcie_width_cap) ?
2089 0 : table_member2[i] :
2090 : pcie_width_cap);
2091 :
2092 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
2093 : SMU_MSG_OverridePcieParameters,
2094 : smu_pcie_arg,
2095 : NULL);
2096 0 : if (ret)
2097 : return ret;
2098 :
2099 0 : if (table_member1[i] > pcie_gen_cap)
2100 0 : dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2101 0 : if (table_member2[i] > pcie_width_cap)
2102 0 : dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2103 : }
2104 :
2105 : return 0;
2106 : }
2107 :
2108 0 : static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2109 : enum smu_clk_type clk_type,
2110 : uint32_t *min, uint32_t *max)
2111 : {
2112 0 : return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2113 : }
2114 :
2115 : static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2116 : OverDriveTable_t *od_table)
2117 : {
2118 0 : struct amdgpu_device *adev = smu->adev;
2119 : uint32_t smu_version;
2120 :
2121 : dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2122 : od_table->GfxclkFmax);
2123 : dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2124 : od_table->UclkFmax);
2125 :
2126 0 : smu_cmn_get_smc_version(smu, NULL, &smu_version);
2127 : if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2128 : (smu_version < 0x003a2900)))
2129 : dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2130 : }
2131 :
2132 0 : static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2133 : {
2134 0 : OverDriveTable_t *od_table =
2135 : (OverDriveTable_t *)smu->smu_table.overdrive_table;
2136 0 : OverDriveTable_t *boot_od_table =
2137 : (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2138 0 : OverDriveTable_t *user_od_table =
2139 : (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2140 0 : int ret = 0;
2141 :
2142 : /*
2143 : * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2144 : * - either they already have the default OD settings got during cold bootup
2145 : * - or they have some user customized OD settings which cannot be overwritten
2146 : */
2147 0 : if (smu->adev->in_suspend)
2148 : return 0;
2149 :
2150 0 : ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2151 : 0, (void *)boot_od_table, false);
2152 0 : if (ret) {
2153 0 : dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2154 0 : return ret;
2155 : }
2156 :
2157 0 : sienna_cichlid_dump_od_table(smu, boot_od_table);
2158 :
2159 0 : memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2160 0 : memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2161 :
2162 0 : return 0;
2163 : }
2164 :
2165 0 : static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2166 : struct smu_11_0_7_overdrive_table *od_table,
2167 : enum SMU_11_0_7_ODSETTING_ID setting,
2168 : uint32_t value)
2169 : {
2170 0 : if (value < od_table->min[setting]) {
2171 0 : dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2172 : setting, value, od_table->min[setting]);
2173 : return -EINVAL;
2174 : }
2175 0 : if (value > od_table->max[setting]) {
2176 0 : dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2177 : setting, value, od_table->max[setting]);
2178 : return -EINVAL;
2179 : }
2180 :
2181 : return 0;
2182 : }
2183 :
2184 0 : static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2185 : enum PP_OD_DPM_TABLE_COMMAND type,
2186 : long input[], uint32_t size)
2187 : {
2188 0 : struct smu_table_context *table_context = &smu->smu_table;
2189 0 : OverDriveTable_t *od_table =
2190 : (OverDriveTable_t *)table_context->overdrive_table;
2191 0 : struct smu_11_0_7_overdrive_table *od_settings =
2192 : (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2193 0 : struct amdgpu_device *adev = smu->adev;
2194 : enum SMU_11_0_7_ODSETTING_ID freq_setting;
2195 : uint16_t *freq_ptr;
2196 0 : int i, ret = 0;
2197 : uint32_t smu_version;
2198 :
2199 0 : if (!smu->od_enabled) {
2200 0 : dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2201 0 : return -EINVAL;
2202 : }
2203 :
2204 0 : if (!smu->od_settings) {
2205 0 : dev_err(smu->adev->dev, "OD board limits are not set!\n");
2206 0 : return -ENOENT;
2207 : }
2208 :
2209 0 : if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2210 0 : dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2211 0 : return -EINVAL;
2212 : }
2213 :
2214 0 : switch (type) {
2215 : case PP_OD_EDIT_SCLK_VDDC_TABLE:
2216 0 : if (!sienna_cichlid_is_od_feature_supported(od_settings,
2217 : SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2218 0 : dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2219 0 : return -ENOTSUPP;
2220 : }
2221 :
2222 0 : for (i = 0; i < size; i += 2) {
2223 0 : if (i + 2 > size) {
2224 0 : dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2225 0 : return -EINVAL;
2226 : }
2227 :
2228 0 : switch (input[i]) {
2229 : case 0:
2230 0 : if (input[i + 1] > od_table->GfxclkFmax) {
2231 0 : dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2232 : input[i + 1], od_table->GfxclkFmax);
2233 0 : return -EINVAL;
2234 : }
2235 :
2236 0 : freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2237 0 : freq_ptr = &od_table->GfxclkFmin;
2238 0 : break;
2239 :
2240 : case 1:
2241 0 : if (input[i + 1] < od_table->GfxclkFmin) {
2242 0 : dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2243 : input[i + 1], od_table->GfxclkFmin);
2244 0 : return -EINVAL;
2245 : }
2246 :
2247 0 : freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2248 0 : freq_ptr = &od_table->GfxclkFmax;
2249 0 : break;
2250 :
2251 : default:
2252 0 : dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2253 0 : dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2254 0 : return -EINVAL;
2255 : }
2256 :
2257 0 : ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2258 0 : freq_setting, input[i + 1]);
2259 0 : if (ret)
2260 : return ret;
2261 :
2262 0 : *freq_ptr = (uint16_t)input[i + 1];
2263 : }
2264 : break;
2265 :
2266 : case PP_OD_EDIT_MCLK_VDDC_TABLE:
2267 0 : if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2268 0 : dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2269 0 : return -ENOTSUPP;
2270 : }
2271 :
2272 0 : for (i = 0; i < size; i += 2) {
2273 0 : if (i + 2 > size) {
2274 0 : dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2275 0 : return -EINVAL;
2276 : }
2277 :
2278 0 : switch (input[i]) {
2279 : case 0:
2280 0 : if (input[i + 1] > od_table->UclkFmax) {
2281 0 : dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2282 : input[i + 1], od_table->UclkFmax);
2283 0 : return -EINVAL;
2284 : }
2285 :
2286 0 : freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2287 0 : freq_ptr = &od_table->UclkFmin;
2288 0 : break;
2289 :
2290 : case 1:
2291 0 : if (input[i + 1] < od_table->UclkFmin) {
2292 0 : dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2293 : input[i + 1], od_table->UclkFmin);
2294 0 : return -EINVAL;
2295 : }
2296 :
2297 0 : freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2298 0 : freq_ptr = &od_table->UclkFmax;
2299 0 : break;
2300 :
2301 : default:
2302 0 : dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2303 0 : dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2304 0 : return -EINVAL;
2305 : }
2306 :
2307 0 : ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2308 0 : freq_setting, input[i + 1]);
2309 0 : if (ret)
2310 : return ret;
2311 :
2312 0 : *freq_ptr = (uint16_t)input[i + 1];
2313 : }
2314 : break;
2315 :
2316 : case PP_OD_RESTORE_DEFAULT_TABLE:
2317 0 : memcpy(table_context->overdrive_table,
2318 : table_context->boot_overdrive_table,
2319 : sizeof(OverDriveTable_t));
2320 : fallthrough;
2321 :
2322 : case PP_OD_COMMIT_DPM_TABLE:
2323 0 : if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2324 0 : sienna_cichlid_dump_od_table(smu, od_table);
2325 0 : ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2326 0 : if (ret) {
2327 0 : dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2328 0 : return ret;
2329 : }
2330 0 : memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2331 0 : smu->user_dpm_profile.user_od = true;
2332 :
2333 0 : if (!memcmp(table_context->user_overdrive_table,
2334 0 : table_context->boot_overdrive_table,
2335 : sizeof(OverDriveTable_t)))
2336 0 : smu->user_dpm_profile.user_od = false;
2337 : }
2338 : break;
2339 :
2340 : case PP_OD_EDIT_VDDGFX_OFFSET:
2341 0 : if (size != 1) {
2342 0 : dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2343 0 : return -EINVAL;
2344 : }
2345 :
2346 : /*
2347 : * OD GFX Voltage Offset functionality is supported only by 58.41.0
2348 : * and onwards SMU firmwares.
2349 : */
2350 0 : smu_cmn_get_smc_version(smu, NULL, &smu_version);
2351 0 : if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2352 0 : (smu_version < 0x003a2900)) {
2353 0 : dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2354 : "only by 58.41.0 and onwards SMU firmwares!\n");
2355 0 : return -EOPNOTSUPP;
2356 : }
2357 :
2358 0 : od_table->VddGfxOffset = (int16_t)input[0];
2359 :
2360 0 : sienna_cichlid_dump_od_table(smu, od_table);
2361 : break;
2362 :
2363 : default:
2364 : return -ENOSYS;
2365 : }
2366 :
2367 : return ret;
2368 : }
2369 :
2370 0 : static int sienna_cichlid_run_btc(struct smu_context *smu)
2371 : {
2372 : int res;
2373 :
2374 0 : res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2375 0 : if (res)
2376 0 : dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2377 :
2378 0 : return res;
2379 : }
2380 :
2381 0 : static int sienna_cichlid_baco_enter(struct smu_context *smu)
2382 : {
2383 0 : struct amdgpu_device *adev = smu->adev;
2384 :
2385 0 : if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2386 0 : return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2387 : else
2388 0 : return smu_v11_0_baco_enter(smu);
2389 : }
2390 :
2391 0 : static int sienna_cichlid_baco_exit(struct smu_context *smu)
2392 : {
2393 0 : struct amdgpu_device *adev = smu->adev;
2394 :
2395 0 : if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2396 : /* Wait for PMFW handling for the Dstate change */
2397 0 : msleep(10);
2398 0 : return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2399 : } else {
2400 0 : return smu_v11_0_baco_exit(smu);
2401 : }
2402 : }
2403 :
2404 0 : static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2405 : {
2406 0 : struct amdgpu_device *adev = smu->adev;
2407 : uint32_t val;
2408 : u32 smu_version;
2409 :
2410 : /**
2411 : * SRIOV env will not support SMU mode1 reset
2412 : * PM FW support mode1 reset from 58.26
2413 : */
2414 0 : smu_cmn_get_smc_version(smu, NULL, &smu_version);
2415 0 : if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2416 : return false;
2417 :
2418 : /**
2419 : * mode1 reset relies on PSP, so we should check if
2420 : * PSP is alive.
2421 : */
2422 0 : val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2423 0 : return val != 0x0;
2424 : }
2425 :
2426 0 : static void beige_goby_dump_pptable(struct smu_context *smu)
2427 : {
2428 0 : struct smu_table_context *table_context = &smu->smu_table;
2429 0 : PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2430 : int i;
2431 :
2432 0 : dev_info(smu->adev->dev, "Dumped PPTable:\n");
2433 :
2434 0 : dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2435 0 : dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2436 0 : dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2437 :
2438 0 : for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2439 0 : dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2440 0 : dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2441 0 : dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2442 0 : dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2443 : }
2444 :
2445 0 : for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2446 0 : dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2447 0 : dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2448 : }
2449 :
2450 0 : for (i = 0; i < TEMP_COUNT; i++) {
2451 0 : dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2452 : }
2453 :
2454 0 : dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2455 0 : dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2456 0 : dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2457 0 : dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2458 0 : dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2459 :
2460 0 : dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2461 0 : for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2462 0 : dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2463 0 : dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2464 : }
2465 0 : dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2466 :
2467 0 : dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2468 :
2469 0 : dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2470 0 : dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2471 0 : dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2472 0 : dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2473 :
2474 0 : dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2475 :
2476 0 : dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2477 :
2478 0 : dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2479 0 : dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2480 0 : dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2481 0 : dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2482 :
2483 0 : dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2484 0 : dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2485 :
2486 0 : dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2487 0 : dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2488 0 : dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2489 0 : dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2490 0 : dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2491 0 : dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2492 0 : dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2493 0 : dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2494 :
2495 0 : dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2496 : " .VoltageMode = 0x%02x\n"
2497 : " .SnapToDiscrete = 0x%02x\n"
2498 : " .NumDiscreteLevels = 0x%02x\n"
2499 : " .padding = 0x%02x\n"
2500 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2501 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2502 : " .SsFmin = 0x%04x\n"
2503 : " .Padding_16 = 0x%04x\n",
2504 : pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2505 : pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2506 : pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2507 : pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2508 : pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2509 : pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2510 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2511 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2512 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2513 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2514 : pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2515 :
2516 0 : dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2517 : " .VoltageMode = 0x%02x\n"
2518 : " .SnapToDiscrete = 0x%02x\n"
2519 : " .NumDiscreteLevels = 0x%02x\n"
2520 : " .padding = 0x%02x\n"
2521 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2522 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2523 : " .SsFmin = 0x%04x\n"
2524 : " .Padding_16 = 0x%04x\n",
2525 : pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2526 : pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2527 : pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2528 : pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2529 : pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2530 : pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2531 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2532 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2533 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2534 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2535 : pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2536 :
2537 0 : dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2538 : " .VoltageMode = 0x%02x\n"
2539 : " .SnapToDiscrete = 0x%02x\n"
2540 : " .NumDiscreteLevels = 0x%02x\n"
2541 : " .padding = 0x%02x\n"
2542 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2543 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2544 : " .SsFmin = 0x%04x\n"
2545 : " .Padding_16 = 0x%04x\n",
2546 : pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2547 : pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2548 : pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2549 : pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2550 : pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2551 : pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2552 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2553 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2554 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2555 : pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2556 : pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2557 :
2558 0 : dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2559 : " .VoltageMode = 0x%02x\n"
2560 : " .SnapToDiscrete = 0x%02x\n"
2561 : " .NumDiscreteLevels = 0x%02x\n"
2562 : " .padding = 0x%02x\n"
2563 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2564 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2565 : " .SsFmin = 0x%04x\n"
2566 : " .Padding_16 = 0x%04x\n",
2567 : pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2568 : pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2569 : pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2570 : pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2571 : pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2572 : pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2573 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2574 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2575 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2576 : pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2577 : pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2578 :
2579 0 : dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2580 : " .VoltageMode = 0x%02x\n"
2581 : " .SnapToDiscrete = 0x%02x\n"
2582 : " .NumDiscreteLevels = 0x%02x\n"
2583 : " .padding = 0x%02x\n"
2584 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2585 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2586 : " .SsFmin = 0x%04x\n"
2587 : " .Padding_16 = 0x%04x\n",
2588 : pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2589 : pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2590 : pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2591 : pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2592 : pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2593 : pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2594 : pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2595 : pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2596 : pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2597 : pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2598 : pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2599 :
2600 0 : dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2601 : " .VoltageMode = 0x%02x\n"
2602 : " .SnapToDiscrete = 0x%02x\n"
2603 : " .NumDiscreteLevels = 0x%02x\n"
2604 : " .padding = 0x%02x\n"
2605 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2606 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2607 : " .SsFmin = 0x%04x\n"
2608 : " .Padding_16 = 0x%04x\n",
2609 : pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2610 : pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2611 : pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2612 : pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2613 : pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2614 : pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2615 : pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2616 : pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2617 : pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2618 : pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2619 : pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2620 :
2621 0 : dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2622 : " .VoltageMode = 0x%02x\n"
2623 : " .SnapToDiscrete = 0x%02x\n"
2624 : " .NumDiscreteLevels = 0x%02x\n"
2625 : " .padding = 0x%02x\n"
2626 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2627 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2628 : " .SsFmin = 0x%04x\n"
2629 : " .Padding_16 = 0x%04x\n",
2630 : pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2631 : pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2632 : pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2633 : pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2634 : pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2635 : pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2636 : pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2637 : pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2638 : pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2639 : pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2640 : pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2641 :
2642 0 : dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2643 : " .VoltageMode = 0x%02x\n"
2644 : " .SnapToDiscrete = 0x%02x\n"
2645 : " .NumDiscreteLevels = 0x%02x\n"
2646 : " .padding = 0x%02x\n"
2647 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2648 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2649 : " .SsFmin = 0x%04x\n"
2650 : " .Padding_16 = 0x%04x\n",
2651 : pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2652 : pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2653 : pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2654 : pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2655 : pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2656 : pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2657 : pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2658 : pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2659 : pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2660 : pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2661 : pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2662 :
2663 0 : dev_info(smu->adev->dev, "FreqTableGfx\n");
2664 0 : for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2665 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2666 :
2667 0 : dev_info(smu->adev->dev, "FreqTableVclk\n");
2668 0 : for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2669 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2670 :
2671 0 : dev_info(smu->adev->dev, "FreqTableDclk\n");
2672 0 : for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2673 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2674 :
2675 0 : dev_info(smu->adev->dev, "FreqTableSocclk\n");
2676 0 : for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2677 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2678 :
2679 0 : dev_info(smu->adev->dev, "FreqTableUclk\n");
2680 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2681 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2682 :
2683 0 : dev_info(smu->adev->dev, "FreqTableFclk\n");
2684 0 : for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2685 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2686 :
2687 0 : dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2688 0 : dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2689 0 : dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2690 0 : dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2691 0 : dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2692 0 : dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2693 0 : dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2694 0 : dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2695 0 : dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2696 :
2697 0 : dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2698 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2699 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2700 :
2701 0 : dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2702 0 : dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2703 :
2704 0 : dev_info(smu->adev->dev, "Mp0clkFreq\n");
2705 0 : for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2706 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2707 :
2708 0 : dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2709 0 : for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2710 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2711 :
2712 0 : dev_info(smu->adev->dev, "MemVddciVoltage\n");
2713 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2714 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2715 :
2716 0 : dev_info(smu->adev->dev, "MemMvddVoltage\n");
2717 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2718 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2719 :
2720 0 : dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2721 0 : dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2722 0 : dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2723 0 : dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2724 0 : dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2725 :
2726 0 : dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2727 :
2728 0 : dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2729 0 : dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2730 0 : dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2731 0 : dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2732 0 : dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2733 0 : dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2734 0 : dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2735 0 : dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2736 0 : dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2737 0 : dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2738 0 : dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2739 :
2740 0 : dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2741 0 : dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2742 0 : dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2743 0 : dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2744 0 : dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2745 0 : dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2746 :
2747 0 : dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2748 0 : dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2749 0 : dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2750 0 : dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2751 0 : dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2752 :
2753 0 : dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2754 0 : for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2755 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2756 :
2757 0 : dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2758 0 : dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2759 0 : dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2760 0 : dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2761 :
2762 0 : dev_info(smu->adev->dev, "UclkDpmPstates\n");
2763 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2764 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2765 :
2766 0 : dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2767 0 : dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2768 : pptable->UclkDpmSrcFreqRange.Fmin);
2769 0 : dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2770 : pptable->UclkDpmSrcFreqRange.Fmax);
2771 0 : dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2772 0 : dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2773 : pptable->UclkDpmTargFreqRange.Fmin);
2774 0 : dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2775 : pptable->UclkDpmTargFreqRange.Fmax);
2776 0 : dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2777 0 : dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2778 :
2779 0 : dev_info(smu->adev->dev, "PcieGenSpeed\n");
2780 0 : for (i = 0; i < NUM_LINK_LEVELS; i++)
2781 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2782 :
2783 0 : dev_info(smu->adev->dev, "PcieLaneCount\n");
2784 0 : for (i = 0; i < NUM_LINK_LEVELS; i++)
2785 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2786 :
2787 0 : dev_info(smu->adev->dev, "LclkFreq\n");
2788 0 : for (i = 0; i < NUM_LINK_LEVELS; i++)
2789 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2790 :
2791 0 : dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2792 0 : dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2793 :
2794 0 : dev_info(smu->adev->dev, "FanGain\n");
2795 0 : for (i = 0; i < TEMP_COUNT; i++)
2796 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2797 :
2798 0 : dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2799 0 : dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2800 0 : dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2801 0 : dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2802 0 : dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2803 0 : dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2804 0 : dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2805 0 : dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2806 0 : dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2807 0 : dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2808 0 : dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2809 0 : dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2810 :
2811 0 : dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2812 0 : dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2813 0 : dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2814 0 : dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2815 :
2816 0 : dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2817 0 : dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2818 0 : dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2819 0 : dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2820 :
2821 0 : dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2822 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2823 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2824 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2825 0 : dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2826 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2827 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2828 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2829 0 : dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2830 : pptable->dBtcGbGfxPll.a,
2831 : pptable->dBtcGbGfxPll.b,
2832 : pptable->dBtcGbGfxPll.c);
2833 0 : dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2834 : pptable->dBtcGbGfxDfll.a,
2835 : pptable->dBtcGbGfxDfll.b,
2836 : pptable->dBtcGbGfxDfll.c);
2837 0 : dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2838 : pptable->dBtcGbSoc.a,
2839 : pptable->dBtcGbSoc.b,
2840 : pptable->dBtcGbSoc.c);
2841 0 : dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2842 : pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2843 : pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2844 0 : dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2845 : pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2846 : pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2847 :
2848 0 : dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2849 0 : for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2850 0 : dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2851 : i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2852 0 : dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2853 : i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2854 : }
2855 :
2856 0 : dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2857 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2858 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2859 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2860 0 : dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2861 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2862 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2863 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2864 :
2865 0 : dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2866 0 : dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2867 :
2868 0 : dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2869 0 : dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2870 0 : dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2871 0 : dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2872 :
2873 0 : dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2874 0 : dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2875 0 : dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2876 0 : dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2877 :
2878 0 : dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2879 0 : dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2880 :
2881 0 : dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2882 0 : for (i = 0; i < NUM_XGMI_LEVELS; i++)
2883 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2884 0 : dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2885 0 : dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2886 :
2887 0 : dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2888 0 : dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2889 : pptable->ReservedEquation0.a,
2890 : pptable->ReservedEquation0.b,
2891 : pptable->ReservedEquation0.c);
2892 0 : dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2893 : pptable->ReservedEquation1.a,
2894 : pptable->ReservedEquation1.b,
2895 : pptable->ReservedEquation1.c);
2896 0 : dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2897 : pptable->ReservedEquation2.a,
2898 : pptable->ReservedEquation2.b,
2899 : pptable->ReservedEquation2.c);
2900 0 : dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2901 : pptable->ReservedEquation3.a,
2902 : pptable->ReservedEquation3.b,
2903 : pptable->ReservedEquation3.c);
2904 :
2905 0 : dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2906 0 : dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2907 0 : dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2908 0 : dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2909 0 : dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2910 0 : dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2911 0 : dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2912 0 : dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2913 :
2914 0 : dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2915 0 : dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2916 0 : dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2917 0 : dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2918 0 : dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2919 0 : dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2920 :
2921 0 : for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2922 0 : dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2923 0 : dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2924 : pptable->I2cControllers[i].Enabled);
2925 0 : dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2926 : pptable->I2cControllers[i].Speed);
2927 0 : dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2928 : pptable->I2cControllers[i].SlaveAddress);
2929 0 : dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2930 : pptable->I2cControllers[i].ControllerPort);
2931 0 : dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2932 : pptable->I2cControllers[i].ControllerName);
2933 0 : dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2934 : pptable->I2cControllers[i].ThermalThrotter);
2935 0 : dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2936 : pptable->I2cControllers[i].I2cProtocol);
2937 0 : dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2938 : pptable->I2cControllers[i].PaddingConfig);
2939 : }
2940 :
2941 0 : dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2942 0 : dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2943 0 : dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2944 0 : dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2945 :
2946 0 : dev_info(smu->adev->dev, "Board Parameters:\n");
2947 0 : dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2948 0 : dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2949 0 : dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2950 0 : dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2951 0 : dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2952 0 : dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2953 0 : dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2954 0 : dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2955 :
2956 0 : dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2957 0 : dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2958 0 : dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2959 :
2960 0 : dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2961 0 : dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2962 0 : dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2963 :
2964 0 : dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2965 0 : dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2966 0 : dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2967 :
2968 0 : dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2969 0 : dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2970 0 : dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2971 :
2972 0 : dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2973 :
2974 0 : dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2975 0 : dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2976 0 : dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2977 0 : dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2978 0 : dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2979 0 : dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2980 0 : dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2981 0 : dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2982 0 : dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2983 0 : dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2984 0 : dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2985 0 : dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2986 0 : dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2987 0 : dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2988 0 : dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2989 0 : dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2990 :
2991 0 : dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2992 0 : dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2993 0 : dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2994 :
2995 0 : dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2996 0 : dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2997 0 : dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2998 :
2999 0 : dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3000 0 : dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3001 :
3002 0 : dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3003 0 : dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3004 0 : dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3005 :
3006 0 : dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3007 0 : dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3008 0 : dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3009 0 : dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3010 0 : dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3011 :
3012 0 : dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3013 0 : dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3014 :
3015 0 : dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3016 0 : for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3017 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3018 0 : dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3019 0 : for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3020 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3021 0 : dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3022 0 : for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3023 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3024 0 : dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3025 0 : for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3026 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3027 :
3028 0 : dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3029 0 : dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3030 0 : dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3031 0 : dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3032 :
3033 0 : dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3034 0 : dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3035 0 : dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3036 0 : dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3037 0 : dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3038 0 : dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3039 0 : dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3040 0 : dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3041 0 : dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3042 0 : dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3043 0 : dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3044 :
3045 0 : dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3046 0 : dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3047 0 : dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3048 0 : dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3049 0 : dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3050 0 : dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3051 0 : dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3052 0 : dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3053 0 : }
3054 :
3055 0 : static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3056 : {
3057 0 : struct smu_table_context *table_context = &smu->smu_table;
3058 0 : PPTable_t *pptable = table_context->driver_pptable;
3059 : int i;
3060 :
3061 0 : if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
3062 0 : beige_goby_dump_pptable(smu);
3063 0 : return;
3064 : }
3065 :
3066 0 : dev_info(smu->adev->dev, "Dumped PPTable:\n");
3067 :
3068 0 : dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3069 0 : dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3070 0 : dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3071 :
3072 0 : for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3073 0 : dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3074 0 : dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3075 0 : dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3076 0 : dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3077 : }
3078 :
3079 0 : for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3080 0 : dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3081 0 : dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3082 : }
3083 :
3084 0 : for (i = 0; i < TEMP_COUNT; i++) {
3085 0 : dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3086 : }
3087 :
3088 0 : dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3089 0 : dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3090 0 : dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3091 0 : dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3092 0 : dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3093 :
3094 0 : dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3095 0 : for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3096 0 : dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3097 0 : dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3098 : }
3099 0 : dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3100 :
3101 0 : dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3102 :
3103 0 : dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3104 0 : dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3105 0 : dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3106 0 : dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3107 :
3108 0 : dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3109 0 : dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3110 :
3111 0 : dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3112 0 : dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3113 0 : dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3114 0 : dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3115 :
3116 0 : dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3117 0 : dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3118 0 : dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3119 0 : dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3120 :
3121 0 : dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3122 0 : dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3123 :
3124 0 : dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3125 0 : dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3126 0 : dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3127 0 : dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3128 0 : dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3129 0 : dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3130 0 : dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3131 0 : dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3132 :
3133 0 : dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3134 : " .VoltageMode = 0x%02x\n"
3135 : " .SnapToDiscrete = 0x%02x\n"
3136 : " .NumDiscreteLevels = 0x%02x\n"
3137 : " .padding = 0x%02x\n"
3138 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3139 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3140 : " .SsFmin = 0x%04x\n"
3141 : " .Padding_16 = 0x%04x\n",
3142 : pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3143 : pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3144 : pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3145 : pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3146 : pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3147 : pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3148 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3149 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3150 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3151 : pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3152 : pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3153 :
3154 0 : dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3155 : " .VoltageMode = 0x%02x\n"
3156 : " .SnapToDiscrete = 0x%02x\n"
3157 : " .NumDiscreteLevels = 0x%02x\n"
3158 : " .padding = 0x%02x\n"
3159 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3160 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3161 : " .SsFmin = 0x%04x\n"
3162 : " .Padding_16 = 0x%04x\n",
3163 : pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3164 : pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3165 : pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3166 : pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3167 : pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3168 : pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3169 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3170 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3171 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3172 : pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3173 : pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3174 :
3175 0 : dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3176 : " .VoltageMode = 0x%02x\n"
3177 : " .SnapToDiscrete = 0x%02x\n"
3178 : " .NumDiscreteLevels = 0x%02x\n"
3179 : " .padding = 0x%02x\n"
3180 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3181 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3182 : " .SsFmin = 0x%04x\n"
3183 : " .Padding_16 = 0x%04x\n",
3184 : pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3185 : pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3186 : pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3187 : pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3188 : pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3189 : pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3190 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3191 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3192 : pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3193 : pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3194 : pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3195 :
3196 0 : dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3197 : " .VoltageMode = 0x%02x\n"
3198 : " .SnapToDiscrete = 0x%02x\n"
3199 : " .NumDiscreteLevels = 0x%02x\n"
3200 : " .padding = 0x%02x\n"
3201 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3202 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3203 : " .SsFmin = 0x%04x\n"
3204 : " .Padding_16 = 0x%04x\n",
3205 : pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3206 : pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3207 : pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3208 : pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3209 : pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3210 : pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3211 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3212 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3213 : pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3214 : pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3215 : pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3216 :
3217 0 : dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3218 : " .VoltageMode = 0x%02x\n"
3219 : " .SnapToDiscrete = 0x%02x\n"
3220 : " .NumDiscreteLevels = 0x%02x\n"
3221 : " .padding = 0x%02x\n"
3222 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3223 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3224 : " .SsFmin = 0x%04x\n"
3225 : " .Padding_16 = 0x%04x\n",
3226 : pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3227 : pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3228 : pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3229 : pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3230 : pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3231 : pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3232 : pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3233 : pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3234 : pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3235 : pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3236 : pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3237 :
3238 0 : dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3239 : " .VoltageMode = 0x%02x\n"
3240 : " .SnapToDiscrete = 0x%02x\n"
3241 : " .NumDiscreteLevels = 0x%02x\n"
3242 : " .padding = 0x%02x\n"
3243 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3244 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3245 : " .SsFmin = 0x%04x\n"
3246 : " .Padding_16 = 0x%04x\n",
3247 : pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3248 : pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3249 : pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3250 : pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3251 : pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3252 : pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3253 : pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3254 : pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3255 : pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3256 : pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3257 : pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3258 :
3259 0 : dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3260 : " .VoltageMode = 0x%02x\n"
3261 : " .SnapToDiscrete = 0x%02x\n"
3262 : " .NumDiscreteLevels = 0x%02x\n"
3263 : " .padding = 0x%02x\n"
3264 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3265 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3266 : " .SsFmin = 0x%04x\n"
3267 : " .Padding_16 = 0x%04x\n",
3268 : pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3269 : pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3270 : pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3271 : pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3272 : pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3273 : pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3274 : pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3275 : pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3276 : pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3277 : pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3278 : pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3279 :
3280 0 : dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3281 : " .VoltageMode = 0x%02x\n"
3282 : " .SnapToDiscrete = 0x%02x\n"
3283 : " .NumDiscreteLevels = 0x%02x\n"
3284 : " .padding = 0x%02x\n"
3285 : " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3286 : " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3287 : " .SsFmin = 0x%04x\n"
3288 : " .Padding_16 = 0x%04x\n",
3289 : pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3290 : pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3291 : pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3292 : pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3293 : pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3294 : pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3295 : pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3296 : pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3297 : pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3298 : pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3299 : pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3300 :
3301 0 : dev_info(smu->adev->dev, "FreqTableGfx\n");
3302 0 : for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3303 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3304 :
3305 0 : dev_info(smu->adev->dev, "FreqTableVclk\n");
3306 0 : for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3307 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3308 :
3309 0 : dev_info(smu->adev->dev, "FreqTableDclk\n");
3310 0 : for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3311 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3312 :
3313 0 : dev_info(smu->adev->dev, "FreqTableSocclk\n");
3314 0 : for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3315 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3316 :
3317 0 : dev_info(smu->adev->dev, "FreqTableUclk\n");
3318 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3319 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3320 :
3321 0 : dev_info(smu->adev->dev, "FreqTableFclk\n");
3322 0 : for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3323 0 : dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3324 :
3325 0 : dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3326 0 : dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3327 0 : dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3328 0 : dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3329 0 : dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3330 0 : dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3331 0 : dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3332 0 : dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3333 0 : dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3334 :
3335 0 : dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3336 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3337 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3338 :
3339 0 : dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3340 0 : dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3341 :
3342 0 : dev_info(smu->adev->dev, "Mp0clkFreq\n");
3343 0 : for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3344 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3345 :
3346 0 : dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3347 0 : for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3348 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3349 :
3350 0 : dev_info(smu->adev->dev, "MemVddciVoltage\n");
3351 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3352 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3353 :
3354 0 : dev_info(smu->adev->dev, "MemMvddVoltage\n");
3355 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3356 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3357 :
3358 0 : dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3359 0 : dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3360 0 : dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3361 0 : dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3362 0 : dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3363 :
3364 0 : dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3365 :
3366 0 : dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3367 0 : dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3368 0 : dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3369 0 : dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3370 0 : dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3371 0 : dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3372 0 : dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3373 0 : dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3374 0 : dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3375 0 : dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3376 0 : dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3377 :
3378 0 : dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3379 0 : dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3380 0 : dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3381 0 : dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3382 0 : dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3383 0 : dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3384 :
3385 0 : dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3386 0 : dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3387 0 : dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3388 0 : dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3389 0 : dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3390 :
3391 0 : dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3392 0 : for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3393 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3394 :
3395 0 : dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3396 0 : dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3397 0 : dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3398 0 : dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3399 :
3400 0 : dev_info(smu->adev->dev, "UclkDpmPstates\n");
3401 0 : for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3402 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3403 :
3404 0 : dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3405 0 : dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3406 : pptable->UclkDpmSrcFreqRange.Fmin);
3407 0 : dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3408 : pptable->UclkDpmSrcFreqRange.Fmax);
3409 0 : dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3410 0 : dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3411 : pptable->UclkDpmTargFreqRange.Fmin);
3412 0 : dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3413 : pptable->UclkDpmTargFreqRange.Fmax);
3414 0 : dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3415 0 : dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3416 :
3417 0 : dev_info(smu->adev->dev, "PcieGenSpeed\n");
3418 0 : for (i = 0; i < NUM_LINK_LEVELS; i++)
3419 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3420 :
3421 0 : dev_info(smu->adev->dev, "PcieLaneCount\n");
3422 0 : for (i = 0; i < NUM_LINK_LEVELS; i++)
3423 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3424 :
3425 0 : dev_info(smu->adev->dev, "LclkFreq\n");
3426 0 : for (i = 0; i < NUM_LINK_LEVELS; i++)
3427 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3428 :
3429 0 : dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3430 0 : dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3431 :
3432 0 : dev_info(smu->adev->dev, "FanGain\n");
3433 0 : for (i = 0; i < TEMP_COUNT; i++)
3434 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3435 :
3436 0 : dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3437 0 : dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3438 0 : dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3439 0 : dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3440 0 : dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3441 0 : dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3442 0 : dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3443 0 : dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3444 0 : dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3445 0 : dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3446 0 : dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3447 0 : dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3448 :
3449 0 : dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3450 0 : dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3451 0 : dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3452 0 : dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3453 :
3454 0 : dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3455 0 : dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3456 0 : dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3457 0 : dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3458 :
3459 0 : dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3460 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3461 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3462 : pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3463 0 : dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3464 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3465 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3466 : pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3467 0 : dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3468 : pptable->dBtcGbGfxPll.a,
3469 : pptable->dBtcGbGfxPll.b,
3470 : pptable->dBtcGbGfxPll.c);
3471 0 : dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3472 : pptable->dBtcGbGfxDfll.a,
3473 : pptable->dBtcGbGfxDfll.b,
3474 : pptable->dBtcGbGfxDfll.c);
3475 0 : dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3476 : pptable->dBtcGbSoc.a,
3477 : pptable->dBtcGbSoc.b,
3478 : pptable->dBtcGbSoc.c);
3479 0 : dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3480 : pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3481 : pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3482 0 : dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3483 : pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3484 : pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3485 :
3486 0 : dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3487 0 : for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3488 0 : dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
3489 : i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3490 0 : dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
3491 : i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3492 : }
3493 :
3494 0 : dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3495 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3496 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3497 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3498 0 : dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3499 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3500 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3501 : pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3502 :
3503 0 : dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3504 0 : dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3505 :
3506 0 : dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3507 0 : dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3508 0 : dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3509 0 : dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3510 :
3511 0 : dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3512 0 : dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3513 0 : dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3514 0 : dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3515 :
3516 0 : dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3517 0 : dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3518 :
3519 0 : dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3520 0 : for (i = 0; i < NUM_XGMI_LEVELS; i++)
3521 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3522 0 : dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3523 0 : dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3524 :
3525 0 : dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3526 0 : dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3527 : pptable->ReservedEquation0.a,
3528 : pptable->ReservedEquation0.b,
3529 : pptable->ReservedEquation0.c);
3530 0 : dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3531 : pptable->ReservedEquation1.a,
3532 : pptable->ReservedEquation1.b,
3533 : pptable->ReservedEquation1.c);
3534 0 : dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3535 : pptable->ReservedEquation2.a,
3536 : pptable->ReservedEquation2.b,
3537 : pptable->ReservedEquation2.c);
3538 0 : dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3539 : pptable->ReservedEquation3.a,
3540 : pptable->ReservedEquation3.b,
3541 : pptable->ReservedEquation3.c);
3542 :
3543 0 : dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3544 0 : dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3545 0 : dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3546 0 : dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3547 0 : dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3548 0 : dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3549 0 : dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3550 0 : dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3551 :
3552 0 : dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3553 0 : dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3554 0 : dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3555 0 : dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3556 0 : dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3557 0 : dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3558 :
3559 0 : for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3560 0 : dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3561 0 : dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3562 : pptable->I2cControllers[i].Enabled);
3563 0 : dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3564 : pptable->I2cControllers[i].Speed);
3565 0 : dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3566 : pptable->I2cControllers[i].SlaveAddress);
3567 0 : dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3568 : pptable->I2cControllers[i].ControllerPort);
3569 0 : dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3570 : pptable->I2cControllers[i].ControllerName);
3571 0 : dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3572 : pptable->I2cControllers[i].ThermalThrotter);
3573 0 : dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3574 : pptable->I2cControllers[i].I2cProtocol);
3575 0 : dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3576 : pptable->I2cControllers[i].PaddingConfig);
3577 : }
3578 :
3579 0 : dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3580 0 : dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3581 0 : dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3582 0 : dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3583 :
3584 0 : dev_info(smu->adev->dev, "Board Parameters:\n");
3585 0 : dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3586 0 : dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3587 0 : dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3588 0 : dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3589 0 : dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3590 0 : dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3591 0 : dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3592 0 : dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3593 :
3594 0 : dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3595 0 : dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3596 0 : dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3597 :
3598 0 : dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3599 0 : dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3600 0 : dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3601 :
3602 0 : dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3603 0 : dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3604 0 : dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3605 :
3606 0 : dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3607 0 : dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3608 0 : dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3609 :
3610 0 : dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3611 :
3612 0 : dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3613 0 : dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3614 0 : dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3615 0 : dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3616 0 : dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3617 0 : dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3618 0 : dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3619 0 : dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3620 0 : dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3621 0 : dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3622 0 : dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3623 0 : dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3624 0 : dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3625 0 : dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3626 0 : dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3627 0 : dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3628 :
3629 0 : dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3630 0 : dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3631 0 : dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3632 :
3633 0 : dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3634 0 : dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3635 0 : dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3636 :
3637 0 : dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3638 0 : dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3639 :
3640 0 : dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3641 0 : dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3642 0 : dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3643 :
3644 0 : dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3645 0 : dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3646 0 : dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3647 0 : dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3648 0 : dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3649 :
3650 0 : dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3651 0 : dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3652 :
3653 0 : dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3654 0 : for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3655 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3656 0 : dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3657 0 : for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3658 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3659 0 : dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3660 0 : for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3661 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3662 0 : dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3663 0 : for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3664 0 : dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3665 :
3666 0 : dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3667 0 : dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3668 0 : dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3669 0 : dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3670 :
3671 0 : dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3672 0 : dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3673 0 : dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3674 0 : dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3675 0 : dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3676 0 : dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3677 0 : dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3678 0 : dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3679 0 : dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3680 0 : dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3681 0 : dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3682 :
3683 0 : dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3684 0 : dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3685 0 : dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3686 0 : dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3687 0 : dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3688 0 : dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3689 0 : dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3690 0 : dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3691 : }
3692 :
3693 0 : static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3694 : struct i2c_msg *msg, int num_msgs)
3695 : {
3696 0 : struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3697 0 : struct amdgpu_device *adev = smu_i2c->adev;
3698 0 : struct smu_context *smu = adev->powerplay.pp_handle;
3699 0 : struct smu_table_context *smu_table = &smu->smu_table;
3700 0 : struct smu_table *table = &smu_table->driver_table;
3701 0 : SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3702 : int i, j, r, c;
3703 : u16 dir;
3704 :
3705 0 : if (!adev->pm.dpm_enabled)
3706 : return -EBUSY;
3707 :
3708 0 : req = kzalloc(sizeof(*req), GFP_KERNEL);
3709 0 : if (!req)
3710 : return -ENOMEM;
3711 :
3712 0 : req->I2CcontrollerPort = smu_i2c->port;
3713 0 : req->I2CSpeed = I2C_SPEED_FAST_400K;
3714 0 : req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3715 0 : dir = msg[0].flags & I2C_M_RD;
3716 :
3717 0 : for (c = i = 0; i < num_msgs; i++) {
3718 0 : for (j = 0; j < msg[i].len; j++, c++) {
3719 0 : SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3720 :
3721 0 : if (!(msg[i].flags & I2C_M_RD)) {
3722 : /* write */
3723 0 : cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3724 0 : cmd->ReadWriteData = msg[i].buf[j];
3725 : }
3726 :
3727 0 : if ((dir ^ msg[i].flags) & I2C_M_RD) {
3728 : /* The direction changes.
3729 : */
3730 0 : dir = msg[i].flags & I2C_M_RD;
3731 0 : cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3732 : }
3733 :
3734 0 : req->NumCmds++;
3735 :
3736 : /*
3737 : * Insert STOP if we are at the last byte of either last
3738 : * message for the transaction or the client explicitly
3739 : * requires a STOP at this particular message.
3740 : */
3741 0 : if ((j == msg[i].len - 1) &&
3742 0 : ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3743 0 : cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3744 0 : cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3745 : }
3746 : }
3747 : }
3748 0 : mutex_lock(&adev->pm.mutex);
3749 0 : r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3750 0 : mutex_unlock(&adev->pm.mutex);
3751 0 : if (r)
3752 : goto fail;
3753 :
3754 0 : for (c = i = 0; i < num_msgs; i++) {
3755 0 : if (!(msg[i].flags & I2C_M_RD)) {
3756 0 : c += msg[i].len;
3757 0 : continue;
3758 : }
3759 0 : for (j = 0; j < msg[i].len; j++, c++) {
3760 0 : SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3761 :
3762 0 : msg[i].buf[j] = cmd->ReadWriteData;
3763 : }
3764 : }
3765 : r = num_msgs;
3766 : fail:
3767 0 : kfree(req);
3768 0 : return r;
3769 : }
3770 :
3771 0 : static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3772 : {
3773 0 : return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3774 : }
3775 :
3776 :
3777 : static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3778 : .master_xfer = sienna_cichlid_i2c_xfer,
3779 : .functionality = sienna_cichlid_i2c_func,
3780 : };
3781 :
3782 : static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3783 : .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3784 : .max_read_len = MAX_SW_I2C_COMMANDS,
3785 : .max_write_len = MAX_SW_I2C_COMMANDS,
3786 : .max_comb_1st_msg_len = 2,
3787 : .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3788 : };
3789 :
3790 0 : static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3791 : {
3792 0 : struct amdgpu_device *adev = smu->adev;
3793 : int res, i;
3794 :
3795 0 : for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3796 0 : struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3797 0 : struct i2c_adapter *control = &smu_i2c->adapter;
3798 :
3799 0 : smu_i2c->adev = adev;
3800 0 : smu_i2c->port = i;
3801 0 : mutex_init(&smu_i2c->mutex);
3802 0 : control->owner = THIS_MODULE;
3803 0 : control->class = I2C_CLASS_HWMON;
3804 0 : control->dev.parent = &adev->pdev->dev;
3805 0 : control->algo = &sienna_cichlid_i2c_algo;
3806 0 : snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3807 0 : control->quirks = &sienna_cichlid_i2c_control_quirks;
3808 0 : i2c_set_adapdata(control, smu_i2c);
3809 :
3810 0 : res = i2c_add_adapter(control);
3811 0 : if (res) {
3812 0 : DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3813 : goto Out_err;
3814 : }
3815 : }
3816 : /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3817 : /* XXX ideally this would be something in a vbios data table */
3818 0 : adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3819 0 : adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3820 :
3821 0 : return 0;
3822 : Out_err:
3823 0 : for ( ; i >= 0; i--) {
3824 0 : struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3825 0 : struct i2c_adapter *control = &smu_i2c->adapter;
3826 :
3827 0 : i2c_del_adapter(control);
3828 : }
3829 : return res;
3830 : }
3831 :
3832 0 : static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3833 : {
3834 0 : struct amdgpu_device *adev = smu->adev;
3835 : int i;
3836 :
3837 0 : for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3838 0 : struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3839 0 : struct i2c_adapter *control = &smu_i2c->adapter;
3840 :
3841 0 : i2c_del_adapter(control);
3842 : }
3843 0 : adev->pm.ras_eeprom_i2c_bus = NULL;
3844 0 : adev->pm.fru_eeprom_i2c_bus = NULL;
3845 0 : }
3846 :
3847 0 : static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3848 : void **table)
3849 : {
3850 0 : struct smu_table_context *smu_table = &smu->smu_table;
3851 0 : struct gpu_metrics_v1_3 *gpu_metrics =
3852 : (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3853 : SmuMetricsExternal_t metrics_external;
3854 0 : SmuMetrics_t *metrics =
3855 : &(metrics_external.SmuMetrics);
3856 0 : SmuMetrics_V2_t *metrics_v2 =
3857 : &(metrics_external.SmuMetrics_V2);
3858 0 : SmuMetrics_V3_t *metrics_v3 =
3859 : &(metrics_external.SmuMetrics_V3);
3860 0 : struct amdgpu_device *adev = smu->adev;
3861 0 : bool use_metrics_v2 = false;
3862 0 : bool use_metrics_v3 = false;
3863 : uint16_t average_gfx_activity;
3864 0 : int ret = 0;
3865 :
3866 0 : switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3867 : case IP_VERSION(11, 0, 7):
3868 0 : if (smu->smc_fw_version >= 0x3A4900)
3869 : use_metrics_v3 = true;
3870 0 : else if (smu->smc_fw_version >= 0x3A4300)
3871 0 : use_metrics_v2 = true;
3872 : break;
3873 : case IP_VERSION(11, 0, 11):
3874 0 : if (smu->smc_fw_version >= 0x412D00)
3875 0 : use_metrics_v2 = true;
3876 : break;
3877 : case IP_VERSION(11, 0, 12):
3878 0 : if (smu->smc_fw_version >= 0x3B2300)
3879 0 : use_metrics_v2 = true;
3880 : break;
3881 : case IP_VERSION(11, 0, 13):
3882 0 : if (smu->smc_fw_version >= 0x491100)
3883 0 : use_metrics_v2 = true;
3884 : break;
3885 : default:
3886 : break;
3887 : }
3888 :
3889 0 : ret = smu_cmn_get_metrics_table(smu,
3890 : &metrics_external,
3891 : true);
3892 0 : if (ret)
3893 0 : return ret;
3894 :
3895 0 : smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3896 :
3897 0 : gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3898 : use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3899 0 : gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3900 : use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3901 0 : gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3902 : use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3903 0 : gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3904 : use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3905 0 : gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3906 : use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3907 0 : gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3908 : use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3909 :
3910 0 : gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3911 : use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3912 0 : gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3913 : use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3914 0 : gpu_metrics->average_mm_activity = use_metrics_v3 ?
3915 0 : (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3916 : use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3917 :
3918 0 : gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3919 : use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3920 0 : gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3921 0 : use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3922 :
3923 0 : if (metrics->CurrGfxVoltageOffset)
3924 0 : gpu_metrics->voltage_gfx =
3925 0 : (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3926 0 : if (metrics->CurrMemVidOffset)
3927 0 : gpu_metrics->voltage_mem =
3928 0 : (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3929 0 : if (metrics->CurrSocVoltageOffset)
3930 0 : gpu_metrics->voltage_soc =
3931 0 : (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3932 :
3933 0 : average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3934 : use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3935 0 : if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3936 0 : gpu_metrics->average_gfxclk_frequency =
3937 : use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3938 : use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3939 : metrics->AverageGfxclkFrequencyPostDs;
3940 : else
3941 0 : gpu_metrics->average_gfxclk_frequency =
3942 : use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3943 : use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3944 : metrics->AverageGfxclkFrequencyPreDs;
3945 :
3946 0 : gpu_metrics->average_uclk_frequency =
3947 : use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3948 : use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3949 : metrics->AverageUclkFrequencyPostDs;
3950 0 : gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
3951 : use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3952 0 : gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
3953 : use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3954 0 : gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
3955 : use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3956 0 : gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
3957 : use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3958 :
3959 0 : gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
3960 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3961 0 : gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
3962 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3963 0 : gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
3964 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3965 0 : gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
3966 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3967 0 : gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
3968 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3969 0 : gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
3970 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3971 0 : gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
3972 0 : use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3973 :
3974 0 : gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
3975 0 : gpu_metrics->indep_throttle_status =
3976 0 : smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
3977 : sienna_cichlid_throttler_map);
3978 :
3979 0 : gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
3980 : use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
3981 :
3982 0 : if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
3983 0 : ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
3984 0 : gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
3985 0 : use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3986 0 : gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
3987 0 : use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
3988 : } else {
3989 0 : gpu_metrics->pcie_link_width =
3990 0 : smu_v11_0_get_current_pcie_link_width(smu);
3991 0 : gpu_metrics->pcie_link_speed =
3992 0 : smu_v11_0_get_current_pcie_link_speed(smu);
3993 : }
3994 :
3995 0 : gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3996 :
3997 0 : *table = (void *)gpu_metrics;
3998 :
3999 0 : return sizeof(struct gpu_metrics_v1_3);
4000 : }
4001 :
4002 0 : static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4003 : {
4004 0 : uint32_t if_version = 0xff, smu_version = 0xff;
4005 0 : int ret = 0;
4006 :
4007 0 : ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
4008 0 : if (ret)
4009 : return -EOPNOTSUPP;
4010 :
4011 0 : if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4012 0 : ret = -EOPNOTSUPP;
4013 :
4014 : return ret;
4015 : }
4016 :
4017 0 : static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4018 : void *table)
4019 : {
4020 0 : struct smu_table_context *smu_table = &smu->smu_table;
4021 0 : EccInfoTable_t *ecc_table = NULL;
4022 0 : struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4023 0 : int i, ret = 0;
4024 0 : struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4025 :
4026 0 : ret = sienna_cichlid_check_ecc_table_support(smu);
4027 0 : if (ret)
4028 0 : return ret;
4029 :
4030 0 : ret = smu_cmn_update_table(smu,
4031 : SMU_TABLE_ECCINFO,
4032 : 0,
4033 : smu_table->ecc_table,
4034 : false);
4035 0 : if (ret) {
4036 0 : dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4037 0 : return ret;
4038 : }
4039 :
4040 0 : ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4041 :
4042 0 : for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4043 0 : ecc_info_per_channel = &(eccinfo->ecc[i]);
4044 0 : ecc_info_per_channel->ce_count_lo_chip =
4045 0 : ecc_table->EccInfo[i].ce_count_lo_chip;
4046 0 : ecc_info_per_channel->ce_count_hi_chip =
4047 0 : ecc_table->EccInfo[i].ce_count_hi_chip;
4048 0 : ecc_info_per_channel->mca_umc_status =
4049 0 : ecc_table->EccInfo[i].mca_umc_status;
4050 0 : ecc_info_per_channel->mca_umc_addr =
4051 0 : ecc_table->EccInfo[i].mca_umc_addr;
4052 : }
4053 :
4054 0 : return ret;
4055 : }
4056 0 : static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4057 : {
4058 : uint16_t *mgpu_fan_boost_limit_rpm;
4059 :
4060 0 : GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4061 : /*
4062 : * Skip the MGpuFanBoost setting for those ASICs
4063 : * which do not support it
4064 : */
4065 0 : if (*mgpu_fan_boost_limit_rpm == 0)
4066 : return 0;
4067 :
4068 0 : return smu_cmn_send_smc_msg_with_param(smu,
4069 : SMU_MSG_SetMGpuFanBoostLimitRpm,
4070 : 0,
4071 : NULL);
4072 : }
4073 :
4074 0 : static int sienna_cichlid_gpo_control(struct smu_context *smu,
4075 : bool enablement)
4076 : {
4077 : uint32_t smu_version;
4078 0 : int ret = 0;
4079 :
4080 :
4081 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4082 0 : ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4083 0 : if (ret)
4084 : return ret;
4085 :
4086 0 : if (enablement) {
4087 0 : if (smu_version < 0x003a2500) {
4088 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
4089 : SMU_MSG_SetGpoFeaturePMask,
4090 : GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4091 : NULL);
4092 : } else {
4093 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
4094 : SMU_MSG_DisallowGpo,
4095 : 0,
4096 : NULL);
4097 : }
4098 : } else {
4099 0 : if (smu_version < 0x003a2500) {
4100 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
4101 : SMU_MSG_SetGpoFeaturePMask,
4102 : 0,
4103 : NULL);
4104 : } else {
4105 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
4106 : SMU_MSG_DisallowGpo,
4107 : 1,
4108 : NULL);
4109 : }
4110 : }
4111 : }
4112 :
4113 : return ret;
4114 : }
4115 :
4116 0 : static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4117 : {
4118 : uint32_t smu_version;
4119 0 : int ret = 0;
4120 :
4121 0 : ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4122 0 : if (ret)
4123 : return ret;
4124 :
4125 : /*
4126 : * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4127 : * onwards PMFWs.
4128 : */
4129 0 : if (smu_version < 0x003A2D00)
4130 : return 0;
4131 :
4132 0 : return smu_cmn_send_smc_msg_with_param(smu,
4133 : SMU_MSG_Enable2ndUSB20Port,
4134 0 : smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4135 : 1 : 0,
4136 : NULL);
4137 : }
4138 :
4139 0 : static int sienna_cichlid_system_features_control(struct smu_context *smu,
4140 : bool en)
4141 : {
4142 0 : int ret = 0;
4143 :
4144 0 : if (en) {
4145 0 : ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4146 0 : if (ret)
4147 : return ret;
4148 : }
4149 :
4150 0 : return smu_v11_0_system_features_control(smu, en);
4151 : }
4152 :
4153 0 : static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4154 : enum pp_mp1_state mp1_state)
4155 : {
4156 : int ret;
4157 :
4158 0 : switch (mp1_state) {
4159 : case PP_MP1_STATE_UNLOAD:
4160 0 : ret = smu_cmn_set_mp1_state(smu, mp1_state);
4161 0 : break;
4162 : default:
4163 : /* Ignore others */
4164 : ret = 0;
4165 : }
4166 :
4167 0 : return ret;
4168 : }
4169 :
4170 0 : static void sienna_cichlid_stb_init(struct smu_context *smu)
4171 : {
4172 0 : struct amdgpu_device *adev = smu->adev;
4173 : uint32_t reg;
4174 :
4175 0 : reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4176 0 : smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4177 :
4178 : /* STB is disabled */
4179 0 : if (!smu->stb_context.enabled)
4180 : return;
4181 :
4182 0 : spin_lock_init(&smu->stb_context.lock);
4183 :
4184 : /* STB buffer size in bytes as function of FIFO depth */
4185 0 : reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4186 0 : smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4187 0 : smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4188 :
4189 0 : dev_info(smu->adev->dev, "STB initialized to %d entries",
4190 : smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4191 :
4192 : }
4193 :
4194 0 : static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4195 : struct config_table_setting *table)
4196 : {
4197 0 : struct amdgpu_device *adev = smu->adev;
4198 :
4199 0 : if (!table)
4200 : return -EINVAL;
4201 :
4202 0 : table->gfxclk_average_tau = 10;
4203 0 : table->socclk_average_tau = 10;
4204 0 : table->fclk_average_tau = 10;
4205 0 : table->uclk_average_tau = 10;
4206 0 : table->gfx_activity_average_tau = 10;
4207 0 : table->mem_activity_average_tau = 10;
4208 0 : table->socket_power_average_tau = 100;
4209 0 : if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
4210 0 : table->apu_socket_power_average_tau = 100;
4211 :
4212 : return 0;
4213 : }
4214 :
4215 0 : static int sienna_cichlid_set_config_table(struct smu_context *smu,
4216 : struct config_table_setting *table)
4217 : {
4218 : DriverSmuConfigExternal_t driver_smu_config_table;
4219 :
4220 0 : if (!table)
4221 : return -EINVAL;
4222 :
4223 0 : memset(&driver_smu_config_table,
4224 : 0,
4225 : sizeof(driver_smu_config_table));
4226 0 : driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4227 0 : table->gfxclk_average_tau;
4228 0 : driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4229 0 : table->fclk_average_tau;
4230 0 : driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4231 0 : table->uclk_average_tau;
4232 0 : driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4233 0 : table->gfx_activity_average_tau;
4234 0 : driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4235 0 : table->mem_activity_average_tau;
4236 0 : driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4237 0 : table->socket_power_average_tau;
4238 :
4239 0 : return smu_cmn_update_table(smu,
4240 : SMU_TABLE_DRIVER_SMU_CONFIG,
4241 : 0,
4242 : (void *)&driver_smu_config_table,
4243 : true);
4244 : }
4245 :
4246 0 : static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4247 : void *buf,
4248 : uint32_t size)
4249 : {
4250 0 : uint32_t *p = buf;
4251 0 : struct amdgpu_device *adev = smu->adev;
4252 :
4253 : /* No need to disable interrupts for now as we don't lock it yet from ISR */
4254 0 : spin_lock(&smu->stb_context.lock);
4255 :
4256 : /*
4257 : * Read the STB FIFO in units of 32bit since this is the accessor window
4258 : * (register width) we have.
4259 : */
4260 0 : buf = ((char *) buf) + size;
4261 0 : while ((void *)p < buf)
4262 0 : *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4263 :
4264 0 : spin_unlock(&smu->stb_context.lock);
4265 :
4266 0 : return 0;
4267 : }
4268 :
4269 0 : static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4270 : {
4271 0 : return true;
4272 : }
4273 :
4274 0 : static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4275 : {
4276 : u32 smu_version;
4277 0 : int ret = 0, index;
4278 0 : struct amdgpu_device *adev = smu->adev;
4279 0 : int timeout = 100;
4280 :
4281 0 : smu_cmn_get_smc_version(smu, NULL, &smu_version);
4282 :
4283 0 : index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4284 : SMU_MSG_DriverMode2Reset);
4285 :
4286 0 : mutex_lock(&smu->message_lock);
4287 :
4288 0 : ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4289 : SMU_RESET_MODE_2);
4290 :
4291 0 : ret = smu_cmn_wait_for_response(smu);
4292 0 : while (ret != 0 && timeout) {
4293 0 : ret = smu_cmn_wait_for_response(smu);
4294 : /* Wait a bit more time for getting ACK */
4295 0 : if (ret != 0) {
4296 0 : --timeout;
4297 0 : usleep_range(500, 1000);
4298 0 : continue;
4299 : } else {
4300 : break;
4301 : }
4302 : }
4303 :
4304 0 : if (!timeout) {
4305 0 : dev_err(adev->dev,
4306 : "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4307 : SMU_RESET_MODE_2, ret);
4308 0 : goto out;
4309 : }
4310 :
4311 0 : dev_info(smu->adev->dev, "restore config space...\n");
4312 : /* Restore the config space saved during init */
4313 0 : amdgpu_device_load_pci_state(adev->pdev);
4314 : out:
4315 0 : mutex_unlock(&smu->message_lock);
4316 :
4317 0 : return ret;
4318 : }
4319 :
4320 : static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4321 : .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4322 : .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4323 : .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4324 : .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4325 : .i2c_init = sienna_cichlid_i2c_control_init,
4326 : .i2c_fini = sienna_cichlid_i2c_control_fini,
4327 : .print_clk_levels = sienna_cichlid_print_clk_levels,
4328 : .force_clk_levels = sienna_cichlid_force_clk_levels,
4329 : .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4330 : .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4331 : .display_config_changed = sienna_cichlid_display_config_changed,
4332 : .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4333 : .is_dpm_running = sienna_cichlid_is_dpm_running,
4334 : .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4335 : .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4336 : .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4337 : .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4338 : .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4339 : .read_sensor = sienna_cichlid_read_sensor,
4340 : .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4341 : .set_performance_level = smu_v11_0_set_performance_level,
4342 : .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4343 : .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4344 : .get_power_limit = sienna_cichlid_get_power_limit,
4345 : .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4346 : .dump_pptable = sienna_cichlid_dump_pptable,
4347 : .init_microcode = smu_v11_0_init_microcode,
4348 : .load_microcode = smu_v11_0_load_microcode,
4349 : .fini_microcode = smu_v11_0_fini_microcode,
4350 : .init_smc_tables = sienna_cichlid_init_smc_tables,
4351 : .fini_smc_tables = smu_v11_0_fini_smc_tables,
4352 : .init_power = smu_v11_0_init_power,
4353 : .fini_power = smu_v11_0_fini_power,
4354 : .check_fw_status = smu_v11_0_check_fw_status,
4355 : .setup_pptable = sienna_cichlid_setup_pptable,
4356 : .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4357 : .check_fw_version = smu_v11_0_check_fw_version,
4358 : .write_pptable = smu_cmn_write_pptable,
4359 : .set_driver_table_location = smu_v11_0_set_driver_table_location,
4360 : .set_tool_table_location = smu_v11_0_set_tool_table_location,
4361 : .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4362 : .system_features_control = sienna_cichlid_system_features_control,
4363 : .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4364 : .send_smc_msg = smu_cmn_send_smc_msg,
4365 : .init_display_count = NULL,
4366 : .set_allowed_mask = smu_v11_0_set_allowed_mask,
4367 : .get_enabled_mask = smu_cmn_get_enabled_mask,
4368 : .feature_is_enabled = smu_cmn_feature_is_enabled,
4369 : .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4370 : .notify_display_change = NULL,
4371 : .set_power_limit = smu_v11_0_set_power_limit,
4372 : .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4373 : .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4374 : .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4375 : .set_min_dcef_deep_sleep = NULL,
4376 : .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4377 : .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4378 : .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4379 : .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4380 : .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4381 : .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4382 : .gfx_off_control = smu_v11_0_gfx_off_control,
4383 : .register_irq_handler = smu_v11_0_register_irq_handler,
4384 : .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4385 : .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4386 : .baco_is_support = smu_v11_0_baco_is_support,
4387 : .baco_get_state = smu_v11_0_baco_get_state,
4388 : .baco_set_state = smu_v11_0_baco_set_state,
4389 : .baco_enter = sienna_cichlid_baco_enter,
4390 : .baco_exit = sienna_cichlid_baco_exit,
4391 : .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4392 : .mode1_reset = smu_v11_0_mode1_reset,
4393 : .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4394 : .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4395 : .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4396 : .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4397 : .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
4398 : .run_btc = sienna_cichlid_run_btc,
4399 : .set_power_source = smu_v11_0_set_power_source,
4400 : .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4401 : .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4402 : .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4403 : .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4404 : .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4405 : .deep_sleep_control = smu_v11_0_deep_sleep_control,
4406 : .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4407 : .interrupt_work = smu_v11_0_interrupt_work,
4408 : .gpo_control = sienna_cichlid_gpo_control,
4409 : .set_mp1_state = sienna_cichlid_set_mp1_state,
4410 : .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4411 : .get_ecc_info = sienna_cichlid_get_ecc_info,
4412 : .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4413 : .set_config_table = sienna_cichlid_set_config_table,
4414 : .get_unique_id = sienna_cichlid_get_unique_id,
4415 : .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4416 : .mode2_reset = sienna_cichlid_mode2_reset,
4417 : };
4418 :
4419 0 : void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4420 : {
4421 0 : smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4422 0 : smu->message_map = sienna_cichlid_message_map;
4423 0 : smu->clock_map = sienna_cichlid_clk_map;
4424 0 : smu->feature_map = sienna_cichlid_feature_mask_map;
4425 0 : smu->table_map = sienna_cichlid_table_map;
4426 0 : smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4427 0 : smu->workload_map = sienna_cichlid_workload_map;
4428 0 : smu_v11_0_set_smu_mailbox_registers(smu);
4429 0 : }
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