Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : */
22 :
23 : #include <linux/firmware.h>
24 : #include <linux/module.h>
25 : #include <linux/pci.h>
26 : #include <linux/reboot.h>
27 :
28 : #define SMU_13_0_PARTIAL_PPTABLE
29 : #define SWSMU_CODE_LAYER_L3
30 :
31 : #include "amdgpu.h"
32 : #include "amdgpu_smu.h"
33 : #include "atomfirmware.h"
34 : #include "amdgpu_atomfirmware.h"
35 : #include "amdgpu_atombios.h"
36 : #include "smu_v13_0.h"
37 : #include "soc15_common.h"
38 : #include "atom.h"
39 : #include "amdgpu_ras.h"
40 : #include "smu_cmn.h"
41 :
42 : #include "asic_reg/thm/thm_13_0_2_offset.h"
43 : #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 : #include "asic_reg/mp/mp_13_0_2_offset.h"
45 : #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 : #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 : #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48 :
49 : /*
50 : * DO NOT use these for err/warn/info/debug messages.
51 : * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 : * They are more MGPU friendly.
53 : */
54 : #undef pr_err
55 : #undef pr_warn
56 : #undef pr_info
57 : #undef pr_debug
58 :
59 : MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 : MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 : MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62 : MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
63 :
64 : #define mmMP1_SMN_C2PMSG_66 0x0282
65 : #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
66 :
67 : #define mmMP1_SMN_C2PMSG_82 0x0292
68 : #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
69 :
70 : #define mmMP1_SMN_C2PMSG_90 0x029a
71 : #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
72 :
73 : #define SMU13_VOLTAGE_SCALE 4
74 :
75 : #define LINK_WIDTH_MAX 6
76 : #define LINK_SPEED_MAX 3
77 :
78 : #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
79 : #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
80 : #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
81 : #define smnPCIE_LC_SPEED_CNTL 0x11140290
82 : #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
83 : #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
84 :
85 : static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
86 : static const int link_speed[] = {25, 50, 80, 160};
87 :
88 0 : int smu_v13_0_init_microcode(struct smu_context *smu)
89 : {
90 0 : struct amdgpu_device *adev = smu->adev;
91 : const char *chip_name;
92 : char fw_name[30];
93 : char ucode_prefix[30];
94 0 : int err = 0;
95 : const struct smc_firmware_header_v1_0 *hdr;
96 : const struct common_firmware_header *header;
97 0 : struct amdgpu_firmware_info *ucode = NULL;
98 :
99 : /* doesn't need to load smu firmware in IOV mode */
100 0 : if (amdgpu_sriov_vf(adev))
101 : return 0;
102 :
103 0 : switch (adev->ip_versions[MP1_HWIP][0]) {
104 : case IP_VERSION(13, 0, 2):
105 : chip_name = "aldebaran_smc";
106 : break;
107 : default:
108 0 : amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
109 0 : chip_name = ucode_prefix;
110 : }
111 :
112 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
113 :
114 0 : err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
115 0 : if (err)
116 : goto out;
117 0 : err = amdgpu_ucode_validate(adev->pm.fw);
118 0 : if (err)
119 : goto out;
120 :
121 0 : hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
122 0 : amdgpu_ucode_print_smc_hdr(&hdr->header);
123 0 : adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
124 :
125 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
126 0 : ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
127 0 : ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
128 0 : ucode->fw = adev->pm.fw;
129 0 : header = (const struct common_firmware_header *)ucode->fw->data;
130 0 : adev->firmware.fw_size +=
131 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
132 : }
133 :
134 : out:
135 0 : if (err) {
136 0 : DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
137 : fw_name);
138 0 : release_firmware(adev->pm.fw);
139 0 : adev->pm.fw = NULL;
140 : }
141 : return err;
142 : }
143 :
144 0 : void smu_v13_0_fini_microcode(struct smu_context *smu)
145 : {
146 0 : struct amdgpu_device *adev = smu->adev;
147 :
148 0 : release_firmware(adev->pm.fw);
149 0 : adev->pm.fw = NULL;
150 0 : adev->pm.fw_version = 0;
151 0 : }
152 :
153 0 : int smu_v13_0_load_microcode(struct smu_context *smu)
154 : {
155 : #if 0
156 : struct amdgpu_device *adev = smu->adev;
157 : const uint32_t *src;
158 : const struct smc_firmware_header_v1_0 *hdr;
159 : uint32_t addr_start = MP1_SRAM;
160 : uint32_t i;
161 : uint32_t smc_fw_size;
162 : uint32_t mp1_fw_flags;
163 :
164 : hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
165 : src = (const uint32_t *)(adev->pm.fw->data +
166 : le32_to_cpu(hdr->header.ucode_array_offset_bytes));
167 : smc_fw_size = hdr->header.ucode_size_bytes;
168 :
169 : for (i = 1; i < smc_fw_size/4 - 1; i++) {
170 : WREG32_PCIE(addr_start, src[i]);
171 : addr_start += 4;
172 : }
173 :
174 : WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
175 : 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
176 : WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
177 : 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
178 :
179 : for (i = 0; i < adev->usec_timeout; i++) {
180 : mp1_fw_flags = RREG32_PCIE(MP1_Public |
181 : (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
182 : if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
183 : MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
184 : break;
185 : udelay(1);
186 : }
187 :
188 : if (i == adev->usec_timeout)
189 : return -ETIME;
190 : #endif
191 :
192 0 : return 0;
193 : }
194 :
195 0 : int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
196 : {
197 0 : struct amdgpu_device *adev = smu->adev;
198 0 : struct amdgpu_firmware_info *ucode = NULL;
199 0 : uint32_t size = 0, pptable_id = 0;
200 0 : int ret = 0;
201 : void *table;
202 :
203 : /* doesn't need to load smu firmware in IOV mode */
204 0 : if (amdgpu_sriov_vf(adev))
205 : return 0;
206 :
207 0 : if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
208 : return 0;
209 :
210 0 : if (!adev->scpm_enabled)
211 : return 0;
212 :
213 0 : if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7))
214 : return 0;
215 :
216 : /* override pptable_id from driver parameter */
217 0 : if (amdgpu_smu_pptable_id >= 0) {
218 0 : pptable_id = amdgpu_smu_pptable_id;
219 0 : dev_info(adev->dev, "override pptable id %d\n", pptable_id);
220 : } else {
221 0 : pptable_id = smu->smu_table.boot_values.pp_table_id;
222 :
223 : /*
224 : * Temporary solution for SMU V13.0.0 with SCPM enabled:
225 : * - use vbios carried pptable when pptable_id is 3664, 3715 or 3795
226 : * - use 36831 soft pptable when pptable_id is 3683
227 : */
228 0 : if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
229 0 : switch (pptable_id) {
230 : case 3664:
231 : case 3715:
232 : case 3795:
233 : pptable_id = 0;
234 : break;
235 : case 3683:
236 0 : pptable_id = 36831;
237 0 : break;
238 : default:
239 0 : dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
240 0 : return -EINVAL;
241 : }
242 : }
243 : }
244 :
245 : /* "pptable_id == 0" means vbios carries the pptable. */
246 0 : if (!pptable_id)
247 : return 0;
248 :
249 0 : ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
250 0 : if (ret)
251 : return ret;
252 :
253 0 : smu->pptable_firmware.data = table;
254 0 : smu->pptable_firmware.size = size;
255 :
256 0 : ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
257 0 : ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
258 0 : ucode->fw = &smu->pptable_firmware;
259 0 : adev->firmware.fw_size +=
260 0 : ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
261 :
262 0 : return 0;
263 : }
264 :
265 0 : int smu_v13_0_check_fw_status(struct smu_context *smu)
266 : {
267 0 : struct amdgpu_device *adev = smu->adev;
268 : uint32_t mp1_fw_flags;
269 :
270 0 : switch (adev->ip_versions[MP1_HWIP][0]) {
271 : case IP_VERSION(13, 0, 4):
272 0 : mp1_fw_flags = RREG32_PCIE(MP1_Public |
273 : (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
274 0 : break;
275 : default:
276 0 : mp1_fw_flags = RREG32_PCIE(MP1_Public |
277 : (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
278 0 : break;
279 : }
280 :
281 0 : if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
282 : MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
283 : return 0;
284 :
285 0 : return -EIO;
286 : }
287 :
288 0 : int smu_v13_0_check_fw_version(struct smu_context *smu)
289 : {
290 0 : struct amdgpu_device *adev = smu->adev;
291 0 : uint32_t if_version = 0xff, smu_version = 0xff;
292 : uint8_t smu_program, smu_major, smu_minor, smu_debug;
293 0 : int ret = 0;
294 :
295 0 : ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
296 0 : if (ret)
297 : return ret;
298 :
299 0 : smu_program = (smu_version >> 24) & 0xff;
300 0 : smu_major = (smu_version >> 16) & 0xff;
301 0 : smu_minor = (smu_version >> 8) & 0xff;
302 0 : smu_debug = (smu_version >> 0) & 0xff;
303 0 : if (smu->is_apu)
304 0 : adev->pm.fw_version = smu_version;
305 :
306 0 : switch (adev->ip_versions[MP1_HWIP][0]) {
307 : case IP_VERSION(13, 0, 2):
308 0 : smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
309 0 : break;
310 : case IP_VERSION(13, 0, 0):
311 0 : smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0;
312 0 : break;
313 : case IP_VERSION(13, 0, 7):
314 0 : smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
315 0 : break;
316 : case IP_VERSION(13, 0, 1):
317 : case IP_VERSION(13, 0, 3):
318 : case IP_VERSION(13, 0, 8):
319 0 : smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
320 0 : break;
321 : case IP_VERSION(13, 0, 4):
322 0 : smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
323 0 : break;
324 : case IP_VERSION(13, 0, 5):
325 0 : smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
326 0 : break;
327 : case IP_VERSION(13, 0, 10):
328 0 : smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_10;
329 0 : break;
330 : default:
331 0 : dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
332 : adev->ip_versions[MP1_HWIP][0]);
333 0 : smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
334 0 : break;
335 : }
336 :
337 : /* only for dGPU w/ SMU13*/
338 : if (adev->pm.fw)
339 : dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
340 : smu_program, smu_version, smu_major, smu_minor, smu_debug);
341 :
342 : /*
343 : * 1. if_version mismatch is not critical as our fw is designed
344 : * to be backward compatible.
345 : * 2. New fw usually brings some optimizations. But that's visible
346 : * only on the paired driver.
347 : * Considering above, we just leave user a warning message instead
348 : * of halt driver loading.
349 : */
350 0 : if (if_version != smu->smc_driver_if_version) {
351 0 : dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
352 : "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
353 : smu->smc_driver_if_version, if_version,
354 : smu_program, smu_version, smu_major, smu_minor, smu_debug);
355 0 : dev_warn(adev->dev, "SMU driver if version not matched\n");
356 : }
357 :
358 : return ret;
359 : }
360 :
361 : static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
362 : {
363 0 : struct amdgpu_device *adev = smu->adev;
364 : uint32_t ppt_offset_bytes;
365 : const struct smc_firmware_header_v2_0 *v2;
366 :
367 0 : v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
368 :
369 0 : ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
370 0 : *size = le32_to_cpu(v2->ppt_size_bytes);
371 0 : *table = (uint8_t *)v2 + ppt_offset_bytes;
372 :
373 : return 0;
374 : }
375 :
376 : static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
377 : uint32_t *size, uint32_t pptable_id)
378 : {
379 0 : struct amdgpu_device *adev = smu->adev;
380 : const struct smc_firmware_header_v2_1 *v2_1;
381 : struct smc_soft_pptable_entry *entries;
382 0 : uint32_t pptable_count = 0;
383 0 : int i = 0;
384 :
385 0 : v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
386 0 : entries = (struct smc_soft_pptable_entry *)
387 0 : ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
388 0 : pptable_count = le32_to_cpu(v2_1->pptable_count);
389 0 : for (i = 0; i < pptable_count; i++) {
390 0 : if (le32_to_cpu(entries[i].id) == pptable_id) {
391 0 : *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
392 0 : *size = le32_to_cpu(entries[i].ppt_size_bytes);
393 : break;
394 : }
395 : }
396 :
397 0 : if (i == pptable_count)
398 : return -EINVAL;
399 :
400 : return 0;
401 : }
402 :
403 0 : static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
404 : {
405 0 : struct amdgpu_device *adev = smu->adev;
406 : uint16_t atom_table_size;
407 : uint8_t frev, crev;
408 : int ret, index;
409 :
410 0 : dev_info(adev->dev, "use vbios provided pptable\n");
411 0 : index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
412 : powerplayinfo);
413 :
414 0 : ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
415 : (uint8_t **)table);
416 0 : if (ret)
417 : return ret;
418 :
419 0 : if (size)
420 0 : *size = atom_table_size;
421 :
422 : return 0;
423 : }
424 :
425 0 : int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
426 : void **table,
427 : uint32_t *size,
428 : uint32_t pptable_id)
429 : {
430 : const struct smc_firmware_header_v1_0 *hdr;
431 0 : struct amdgpu_device *adev = smu->adev;
432 : uint16_t version_major, version_minor;
433 : int ret;
434 :
435 0 : hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
436 0 : if (!hdr)
437 : return -EINVAL;
438 :
439 0 : dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
440 :
441 0 : version_major = le16_to_cpu(hdr->header.header_version_major);
442 0 : version_minor = le16_to_cpu(hdr->header.header_version_minor);
443 0 : if (version_major != 2) {
444 0 : dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
445 : version_major, version_minor);
446 0 : return -EINVAL;
447 : }
448 :
449 0 : switch (version_minor) {
450 : case 0:
451 0 : ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
452 0 : break;
453 : case 1:
454 0 : ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
455 : break;
456 : default:
457 : ret = -EINVAL;
458 : break;
459 : }
460 :
461 : return ret;
462 : }
463 :
464 0 : int smu_v13_0_setup_pptable(struct smu_context *smu)
465 : {
466 0 : struct amdgpu_device *adev = smu->adev;
467 0 : uint32_t size = 0, pptable_id = 0;
468 : void *table;
469 0 : int ret = 0;
470 :
471 : /* override pptable_id from driver parameter */
472 0 : if (amdgpu_smu_pptable_id >= 0) {
473 0 : pptable_id = amdgpu_smu_pptable_id;
474 0 : dev_info(adev->dev, "override pptable id %d\n", pptable_id);
475 : } else {
476 0 : pptable_id = smu->smu_table.boot_values.pp_table_id;
477 :
478 : /*
479 : * Temporary solution for SMU V13.0.0 with SCPM disabled:
480 : * - use 3664, 3683 or 3715 on request
481 : * - use 3664 when pptable_id is 0
482 : * TODO: drop these when the pptable carried in vbios is ready.
483 : */
484 0 : if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
485 0 : switch (pptable_id) {
486 : case 0:
487 0 : pptable_id = 3664;
488 0 : break;
489 : case 3664:
490 : case 3683:
491 : case 3715:
492 : break;
493 : default:
494 0 : dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
495 0 : return -EINVAL;
496 : }
497 0 : } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)) {
498 0 : pptable_id = 6666;
499 : }
500 : }
501 :
502 : /* force using vbios pptable in sriov mode */
503 0 : if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
504 0 : ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
505 : else
506 0 : ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
507 :
508 0 : if (ret)
509 : return ret;
510 :
511 0 : if (!smu->smu_table.power_play_table)
512 0 : smu->smu_table.power_play_table = table;
513 0 : if (!smu->smu_table.power_play_table_size)
514 0 : smu->smu_table.power_play_table_size = size;
515 :
516 : return 0;
517 : }
518 :
519 0 : int smu_v13_0_init_smc_tables(struct smu_context *smu)
520 : {
521 0 : struct smu_table_context *smu_table = &smu->smu_table;
522 0 : struct smu_table *tables = smu_table->tables;
523 0 : int ret = 0;
524 :
525 0 : smu_table->driver_pptable =
526 0 : kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
527 0 : if (!smu_table->driver_pptable) {
528 : ret = -ENOMEM;
529 : goto err0_out;
530 : }
531 :
532 0 : smu_table->max_sustainable_clocks =
533 0 : kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
534 0 : if (!smu_table->max_sustainable_clocks) {
535 : ret = -ENOMEM;
536 : goto err1_out;
537 : }
538 :
539 : /* Aldebaran does not support OVERDRIVE */
540 0 : if (tables[SMU_TABLE_OVERDRIVE].size) {
541 0 : smu_table->overdrive_table =
542 0 : kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
543 0 : if (!smu_table->overdrive_table) {
544 : ret = -ENOMEM;
545 : goto err2_out;
546 : }
547 :
548 0 : smu_table->boot_overdrive_table =
549 0 : kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
550 0 : if (!smu_table->boot_overdrive_table) {
551 : ret = -ENOMEM;
552 : goto err3_out;
553 : }
554 : }
555 :
556 0 : smu_table->combo_pptable =
557 0 : kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
558 0 : if (!smu_table->combo_pptable) {
559 0 : ret = -ENOMEM;
560 : goto err4_out;
561 : }
562 :
563 : return 0;
564 :
565 : err4_out:
566 0 : kfree(smu_table->boot_overdrive_table);
567 : err3_out:
568 0 : kfree(smu_table->overdrive_table);
569 : err2_out:
570 0 : kfree(smu_table->max_sustainable_clocks);
571 : err1_out:
572 0 : kfree(smu_table->driver_pptable);
573 : err0_out:
574 : return ret;
575 : }
576 :
577 0 : int smu_v13_0_fini_smc_tables(struct smu_context *smu)
578 : {
579 0 : struct smu_table_context *smu_table = &smu->smu_table;
580 0 : struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
581 :
582 0 : kfree(smu_table->gpu_metrics_table);
583 0 : kfree(smu_table->combo_pptable);
584 0 : kfree(smu_table->boot_overdrive_table);
585 0 : kfree(smu_table->overdrive_table);
586 0 : kfree(smu_table->max_sustainable_clocks);
587 0 : kfree(smu_table->driver_pptable);
588 0 : smu_table->gpu_metrics_table = NULL;
589 0 : smu_table->combo_pptable = NULL;
590 0 : smu_table->boot_overdrive_table = NULL;
591 0 : smu_table->overdrive_table = NULL;
592 0 : smu_table->max_sustainable_clocks = NULL;
593 0 : smu_table->driver_pptable = NULL;
594 0 : kfree(smu_table->hardcode_pptable);
595 0 : smu_table->hardcode_pptable = NULL;
596 :
597 0 : kfree(smu_table->ecc_table);
598 0 : kfree(smu_table->metrics_table);
599 0 : kfree(smu_table->watermarks_table);
600 0 : smu_table->ecc_table = NULL;
601 0 : smu_table->metrics_table = NULL;
602 0 : smu_table->watermarks_table = NULL;
603 0 : smu_table->metrics_time = 0;
604 :
605 0 : kfree(smu_dpm->dpm_context);
606 0 : kfree(smu_dpm->golden_dpm_context);
607 0 : kfree(smu_dpm->dpm_current_power_state);
608 0 : kfree(smu_dpm->dpm_request_power_state);
609 0 : smu_dpm->dpm_context = NULL;
610 0 : smu_dpm->golden_dpm_context = NULL;
611 0 : smu_dpm->dpm_context_size = 0;
612 0 : smu_dpm->dpm_current_power_state = NULL;
613 0 : smu_dpm->dpm_request_power_state = NULL;
614 :
615 0 : return 0;
616 : }
617 :
618 0 : int smu_v13_0_init_power(struct smu_context *smu)
619 : {
620 0 : struct smu_power_context *smu_power = &smu->smu_power;
621 :
622 0 : if (smu_power->power_context || smu_power->power_context_size != 0)
623 : return -EINVAL;
624 :
625 0 : smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
626 : GFP_KERNEL);
627 0 : if (!smu_power->power_context)
628 : return -ENOMEM;
629 0 : smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
630 :
631 0 : return 0;
632 : }
633 :
634 0 : int smu_v13_0_fini_power(struct smu_context *smu)
635 : {
636 0 : struct smu_power_context *smu_power = &smu->smu_power;
637 :
638 0 : if (!smu_power->power_context || smu_power->power_context_size == 0)
639 : return -EINVAL;
640 :
641 0 : kfree(smu_power->power_context);
642 0 : smu_power->power_context = NULL;
643 0 : smu_power->power_context_size = 0;
644 :
645 0 : return 0;
646 : }
647 :
648 0 : int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
649 : {
650 : int ret, index;
651 : uint16_t size;
652 : uint8_t frev, crev;
653 : struct atom_common_table_header *header;
654 : struct atom_firmware_info_v3_4 *v_3_4;
655 : struct atom_firmware_info_v3_3 *v_3_3;
656 : struct atom_firmware_info_v3_1 *v_3_1;
657 : struct atom_smu_info_v3_6 *smu_info_v3_6;
658 : struct atom_smu_info_v4_0 *smu_info_v4_0;
659 :
660 0 : index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
661 : firmwareinfo);
662 :
663 0 : ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
664 : (uint8_t **)&header);
665 0 : if (ret)
666 : return ret;
667 :
668 0 : if (header->format_revision != 3) {
669 0 : dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
670 0 : return -EINVAL;
671 : }
672 :
673 0 : switch (header->content_revision) {
674 : case 0:
675 : case 1:
676 : case 2:
677 0 : v_3_1 = (struct atom_firmware_info_v3_1 *)header;
678 0 : smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
679 0 : smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
680 0 : smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
681 0 : smu->smu_table.boot_values.socclk = 0;
682 0 : smu->smu_table.boot_values.dcefclk = 0;
683 0 : smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
684 0 : smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
685 0 : smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
686 0 : smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
687 0 : smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
688 0 : smu->smu_table.boot_values.pp_table_id = 0;
689 0 : break;
690 : case 3:
691 0 : v_3_3 = (struct atom_firmware_info_v3_3 *)header;
692 0 : smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
693 0 : smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
694 0 : smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
695 0 : smu->smu_table.boot_values.socclk = 0;
696 0 : smu->smu_table.boot_values.dcefclk = 0;
697 0 : smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
698 0 : smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
699 0 : smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
700 0 : smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
701 0 : smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
702 0 : smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
703 0 : break;
704 : case 4:
705 : default:
706 0 : v_3_4 = (struct atom_firmware_info_v3_4 *)header;
707 0 : smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
708 0 : smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
709 0 : smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
710 0 : smu->smu_table.boot_values.socclk = 0;
711 0 : smu->smu_table.boot_values.dcefclk = 0;
712 0 : smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
713 0 : smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
714 0 : smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
715 0 : smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
716 0 : smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
717 0 : smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
718 0 : break;
719 : }
720 :
721 0 : smu->smu_table.boot_values.format_revision = header->format_revision;
722 0 : smu->smu_table.boot_values.content_revision = header->content_revision;
723 :
724 0 : index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
725 : smu_info);
726 0 : if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
727 : (uint8_t **)&header)) {
728 :
729 0 : if ((frev == 3) && (crev == 6)) {
730 0 : smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
731 :
732 0 : smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
733 0 : smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
734 0 : smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
735 0 : smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
736 0 : } else if ((frev == 3) && (crev == 1)) {
737 : return 0;
738 0 : } else if ((frev == 4) && (crev == 0)) {
739 0 : smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
740 :
741 0 : smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
742 0 : smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
743 0 : smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
744 0 : smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
745 0 : smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
746 : } else {
747 0 : dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
748 : (uint32_t)frev, (uint32_t)crev);
749 : }
750 : }
751 :
752 : return 0;
753 : }
754 :
755 :
756 0 : int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
757 : {
758 0 : struct smu_table_context *smu_table = &smu->smu_table;
759 0 : struct smu_table *memory_pool = &smu_table->memory_pool;
760 0 : int ret = 0;
761 : uint64_t address;
762 : uint32_t address_low, address_high;
763 :
764 0 : if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
765 : return ret;
766 :
767 0 : address = memory_pool->mc_address;
768 0 : address_high = (uint32_t)upper_32_bits(address);
769 0 : address_low = (uint32_t)lower_32_bits(address);
770 :
771 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
772 : address_high, NULL);
773 0 : if (ret)
774 : return ret;
775 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
776 : address_low, NULL);
777 0 : if (ret)
778 : return ret;
779 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
780 0 : (uint32_t)memory_pool->size, NULL);
781 : if (ret)
782 : return ret;
783 :
784 : return ret;
785 : }
786 :
787 0 : int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
788 : {
789 : int ret;
790 :
791 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
792 : SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
793 0 : if (ret)
794 0 : dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
795 :
796 0 : return ret;
797 : }
798 :
799 0 : int smu_v13_0_set_driver_table_location(struct smu_context *smu)
800 : {
801 0 : struct smu_table *driver_table = &smu->smu_table.driver_table;
802 0 : int ret = 0;
803 :
804 0 : if (driver_table->mc_address) {
805 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
806 : SMU_MSG_SetDriverDramAddrHigh,
807 0 : upper_32_bits(driver_table->mc_address),
808 : NULL);
809 0 : if (!ret)
810 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
811 : SMU_MSG_SetDriverDramAddrLow,
812 0 : lower_32_bits(driver_table->mc_address),
813 : NULL);
814 : }
815 :
816 0 : return ret;
817 : }
818 :
819 0 : int smu_v13_0_set_tool_table_location(struct smu_context *smu)
820 : {
821 0 : int ret = 0;
822 0 : struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
823 :
824 0 : if (tool_table->mc_address) {
825 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
826 : SMU_MSG_SetToolsDramAddrHigh,
827 0 : upper_32_bits(tool_table->mc_address),
828 : NULL);
829 0 : if (!ret)
830 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
831 : SMU_MSG_SetToolsDramAddrLow,
832 0 : lower_32_bits(tool_table->mc_address),
833 : NULL);
834 : }
835 :
836 0 : return ret;
837 : }
838 :
839 0 : int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
840 : {
841 0 : int ret = 0;
842 :
843 0 : if (!smu->pm_enabled)
844 : return ret;
845 :
846 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
847 :
848 0 : return ret;
849 : }
850 :
851 0 : int smu_v13_0_set_allowed_mask(struct smu_context *smu)
852 : {
853 0 : struct smu_feature *feature = &smu->smu_feature;
854 0 : int ret = 0;
855 : uint32_t feature_mask[2];
856 :
857 0 : if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
858 0 : feature->feature_num < 64)
859 : return -EINVAL;
860 :
861 0 : bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
862 :
863 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
864 : feature_mask[1], NULL);
865 0 : if (ret)
866 : return ret;
867 :
868 0 : return smu_cmn_send_smc_msg_with_param(smu,
869 : SMU_MSG_SetAllowedFeaturesMaskLow,
870 : feature_mask[0],
871 : NULL);
872 : }
873 :
874 0 : int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
875 : {
876 0 : int ret = 0;
877 0 : struct amdgpu_device *adev = smu->adev;
878 :
879 0 : switch (adev->ip_versions[MP1_HWIP][0]) {
880 : case IP_VERSION(13, 0, 0):
881 : case IP_VERSION(13, 0, 1):
882 : case IP_VERSION(13, 0, 3):
883 : case IP_VERSION(13, 0, 4):
884 : case IP_VERSION(13, 0, 5):
885 : case IP_VERSION(13, 0, 7):
886 : case IP_VERSION(13, 0, 8):
887 0 : if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
888 : return 0;
889 0 : if (enable)
890 0 : ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
891 : else
892 0 : ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
893 : break;
894 : default:
895 : break;
896 : }
897 :
898 : return ret;
899 : }
900 :
901 0 : int smu_v13_0_system_features_control(struct smu_context *smu,
902 : bool en)
903 : {
904 0 : return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
905 : SMU_MSG_DisableAllSmuFeatures), NULL);
906 : }
907 :
908 0 : int smu_v13_0_notify_display_change(struct smu_context *smu)
909 : {
910 0 : int ret = 0;
911 :
912 0 : if (!smu->pm_enabled)
913 : return ret;
914 :
915 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
916 0 : smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
917 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
918 :
919 : return ret;
920 : }
921 :
922 : static int
923 0 : smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
924 : enum smu_clk_type clock_select)
925 : {
926 0 : int ret = 0;
927 : int clk_id;
928 :
929 0 : if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
930 0 : (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
931 : return 0;
932 :
933 0 : clk_id = smu_cmn_to_asic_specific_index(smu,
934 : CMN2ASIC_MAPPING_CLK,
935 : clock_select);
936 0 : if (clk_id < 0)
937 : return -EINVAL;
938 :
939 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
940 0 : clk_id << 16, clock);
941 0 : if (ret) {
942 0 : dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
943 0 : return ret;
944 : }
945 :
946 0 : if (*clock != 0)
947 : return 0;
948 :
949 : /* if DC limit is zero, return AC limit */
950 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
951 : clk_id << 16, clock);
952 0 : if (ret) {
953 0 : dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
954 0 : return ret;
955 : }
956 :
957 : return 0;
958 : }
959 :
960 0 : int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
961 : {
962 0 : struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
963 : smu->smu_table.max_sustainable_clocks;
964 0 : int ret = 0;
965 :
966 0 : max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
967 0 : max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
968 0 : max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
969 0 : max_sustainable_clocks->display_clock = 0xFFFFFFFF;
970 0 : max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
971 0 : max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
972 :
973 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
974 0 : ret = smu_v13_0_get_max_sustainable_clock(smu,
975 : &(max_sustainable_clocks->uclock),
976 : SMU_UCLK);
977 0 : if (ret) {
978 0 : dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
979 : __func__);
980 0 : return ret;
981 : }
982 : }
983 :
984 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
985 0 : ret = smu_v13_0_get_max_sustainable_clock(smu,
986 : &(max_sustainable_clocks->soc_clock),
987 : SMU_SOCCLK);
988 0 : if (ret) {
989 0 : dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
990 : __func__);
991 0 : return ret;
992 : }
993 : }
994 :
995 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
996 0 : ret = smu_v13_0_get_max_sustainable_clock(smu,
997 : &(max_sustainable_clocks->dcef_clock),
998 : SMU_DCEFCLK);
999 0 : if (ret) {
1000 0 : dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
1001 : __func__);
1002 0 : return ret;
1003 : }
1004 :
1005 0 : ret = smu_v13_0_get_max_sustainable_clock(smu,
1006 : &(max_sustainable_clocks->display_clock),
1007 : SMU_DISPCLK);
1008 0 : if (ret) {
1009 0 : dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
1010 : __func__);
1011 0 : return ret;
1012 : }
1013 0 : ret = smu_v13_0_get_max_sustainable_clock(smu,
1014 : &(max_sustainable_clocks->phy_clock),
1015 : SMU_PHYCLK);
1016 0 : if (ret) {
1017 0 : dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
1018 : __func__);
1019 0 : return ret;
1020 : }
1021 0 : ret = smu_v13_0_get_max_sustainable_clock(smu,
1022 : &(max_sustainable_clocks->pixel_clock),
1023 : SMU_PIXCLK);
1024 0 : if (ret) {
1025 0 : dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
1026 : __func__);
1027 0 : return ret;
1028 : }
1029 : }
1030 :
1031 0 : if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1032 0 : max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1033 :
1034 : return 0;
1035 : }
1036 :
1037 0 : int smu_v13_0_get_current_power_limit(struct smu_context *smu,
1038 : uint32_t *power_limit)
1039 : {
1040 : int power_src;
1041 0 : int ret = 0;
1042 :
1043 0 : if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1044 : return -EINVAL;
1045 :
1046 0 : power_src = smu_cmn_to_asic_specific_index(smu,
1047 : CMN2ASIC_MAPPING_PWR,
1048 0 : smu->adev->pm.ac_power ?
1049 0 : SMU_POWER_SOURCE_AC :
1050 : SMU_POWER_SOURCE_DC);
1051 0 : if (power_src < 0)
1052 : return -EINVAL;
1053 :
1054 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
1055 : SMU_MSG_GetPptLimit,
1056 0 : power_src << 16,
1057 : power_limit);
1058 0 : if (ret)
1059 0 : dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1060 :
1061 : return ret;
1062 : }
1063 :
1064 0 : int smu_v13_0_set_power_limit(struct smu_context *smu,
1065 : enum smu_ppt_limit_type limit_type,
1066 : uint32_t limit)
1067 : {
1068 0 : int ret = 0;
1069 :
1070 0 : if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1071 : return -EINVAL;
1072 :
1073 0 : if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1074 0 : dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1075 0 : return -EOPNOTSUPP;
1076 : }
1077 :
1078 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1079 0 : if (ret) {
1080 0 : dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1081 0 : return ret;
1082 : }
1083 :
1084 0 : smu->current_power_limit = limit;
1085 :
1086 0 : return 0;
1087 : }
1088 :
1089 : static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1090 : {
1091 0 : return smu_cmn_send_smc_msg(smu,
1092 : SMU_MSG_AllowIHHostInterrupt,
1093 : NULL);
1094 : }
1095 :
1096 0 : static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1097 : {
1098 0 : int ret = 0;
1099 :
1100 0 : if (smu->dc_controlled_by_gpio &&
1101 0 : smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1102 0 : ret = smu_v13_0_allow_ih_interrupt(smu);
1103 :
1104 0 : return ret;
1105 : }
1106 :
1107 0 : int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1108 : {
1109 0 : int ret = 0;
1110 :
1111 0 : if (!smu->irq_source.num_types)
1112 : return 0;
1113 :
1114 0 : ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1115 0 : if (ret)
1116 : return ret;
1117 :
1118 0 : return smu_v13_0_process_pending_interrupt(smu);
1119 : }
1120 :
1121 0 : int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1122 : {
1123 0 : if (!smu->irq_source.num_types)
1124 : return 0;
1125 :
1126 0 : return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1127 : }
1128 :
1129 : static uint16_t convert_to_vddc(uint8_t vid)
1130 : {
1131 0 : return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1132 : }
1133 :
1134 0 : int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1135 : {
1136 0 : struct amdgpu_device *adev = smu->adev;
1137 0 : uint32_t vdd = 0, val_vid = 0;
1138 :
1139 0 : if (!value)
1140 : return -EINVAL;
1141 0 : val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1142 0 : SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1143 : SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1144 :
1145 0 : vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1146 :
1147 0 : *value = vdd;
1148 :
1149 0 : return 0;
1150 :
1151 : }
1152 :
1153 : int
1154 0 : smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1155 : struct pp_display_clock_request
1156 : *clock_req)
1157 : {
1158 0 : enum amd_pp_clock_type clk_type = clock_req->clock_type;
1159 0 : int ret = 0;
1160 0 : enum smu_clk_type clk_select = 0;
1161 0 : uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1162 :
1163 0 : if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1164 0 : smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1165 0 : switch (clk_type) {
1166 : case amd_pp_dcef_clock:
1167 : clk_select = SMU_DCEFCLK;
1168 : break;
1169 : case amd_pp_disp_clock:
1170 0 : clk_select = SMU_DISPCLK;
1171 0 : break;
1172 : case amd_pp_pixel_clock:
1173 0 : clk_select = SMU_PIXCLK;
1174 0 : break;
1175 : case amd_pp_phy_clock:
1176 0 : clk_select = SMU_PHYCLK;
1177 0 : break;
1178 : case amd_pp_mem_clock:
1179 0 : clk_select = SMU_UCLK;
1180 0 : break;
1181 : default:
1182 0 : dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1183 0 : ret = -EINVAL;
1184 0 : break;
1185 : }
1186 :
1187 0 : if (ret)
1188 : goto failed;
1189 :
1190 0 : if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1191 : return 0;
1192 :
1193 0 : ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1194 :
1195 0 : if(clk_select == SMU_UCLK)
1196 0 : smu->hard_min_uclk_req_from_dal = clk_freq;
1197 : }
1198 :
1199 : failed:
1200 : return ret;
1201 : }
1202 :
1203 0 : uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1204 : {
1205 0 : if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1206 : return AMD_FAN_CTRL_MANUAL;
1207 : else
1208 0 : return AMD_FAN_CTRL_AUTO;
1209 : }
1210 :
1211 : static int
1212 0 : smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1213 : {
1214 0 : int ret = 0;
1215 :
1216 0 : if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1217 : return 0;
1218 :
1219 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1220 0 : if (ret)
1221 0 : dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1222 : __func__, (auto_fan_control ? "Start" : "Stop"));
1223 :
1224 : return ret;
1225 : }
1226 :
1227 : static int
1228 0 : smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1229 : {
1230 0 : struct amdgpu_device *adev = smu->adev;
1231 :
1232 0 : WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1233 : REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1234 : CG_FDO_CTRL2, TMIN, 0));
1235 0 : WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1236 : REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1237 : CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1238 :
1239 0 : return 0;
1240 : }
1241 :
1242 0 : int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1243 : uint32_t speed)
1244 : {
1245 0 : struct amdgpu_device *adev = smu->adev;
1246 : uint32_t duty100, duty;
1247 : uint64_t tmp64;
1248 :
1249 0 : speed = MIN(speed, 255);
1250 :
1251 0 : if (smu_v13_0_auto_fan_control(smu, 0))
1252 : return -EINVAL;
1253 :
1254 0 : duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1255 : CG_FDO_CTRL1, FMAX_DUTY100);
1256 0 : if (!duty100)
1257 : return -EINVAL;
1258 :
1259 0 : tmp64 = (uint64_t)speed * duty100;
1260 0 : do_div(tmp64, 255);
1261 0 : duty = (uint32_t)tmp64;
1262 :
1263 0 : WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1264 : REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1265 : CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1266 :
1267 0 : return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1268 : }
1269 :
1270 : int
1271 0 : smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1272 : uint32_t mode)
1273 : {
1274 0 : int ret = 0;
1275 :
1276 0 : switch (mode) {
1277 : case AMD_FAN_CTRL_NONE:
1278 0 : ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1279 0 : break;
1280 : case AMD_FAN_CTRL_MANUAL:
1281 0 : ret = smu_v13_0_auto_fan_control(smu, 0);
1282 0 : break;
1283 : case AMD_FAN_CTRL_AUTO:
1284 0 : ret = smu_v13_0_auto_fan_control(smu, 1);
1285 0 : break;
1286 : default:
1287 : break;
1288 : }
1289 :
1290 0 : if (ret) {
1291 0 : dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1292 0 : return -EINVAL;
1293 : }
1294 :
1295 : return ret;
1296 : }
1297 :
1298 0 : int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1299 : uint32_t speed)
1300 : {
1301 0 : struct amdgpu_device *adev = smu->adev;
1302 : uint32_t tach_period, crystal_clock_freq;
1303 : int ret;
1304 :
1305 0 : if (!speed)
1306 : return -EINVAL;
1307 :
1308 0 : ret = smu_v13_0_auto_fan_control(smu, 0);
1309 0 : if (ret)
1310 : return ret;
1311 :
1312 0 : crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1313 0 : tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1314 0 : WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1315 : REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1316 : CG_TACH_CTRL, TARGET_PERIOD,
1317 : tach_period));
1318 :
1319 0 : return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1320 : }
1321 :
1322 0 : int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1323 : uint32_t pstate)
1324 : {
1325 0 : int ret = 0;
1326 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
1327 : SMU_MSG_SetXgmiMode,
1328 : pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1329 : NULL);
1330 0 : return ret;
1331 : }
1332 :
1333 0 : static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1334 : struct amdgpu_irq_src *source,
1335 : unsigned tyep,
1336 : enum amdgpu_interrupt_state state)
1337 : {
1338 0 : struct smu_context *smu = adev->powerplay.pp_handle;
1339 : uint32_t low, high;
1340 0 : uint32_t val = 0;
1341 :
1342 0 : switch (state) {
1343 : case AMDGPU_IRQ_STATE_DISABLE:
1344 : /* For THM irqs */
1345 0 : val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1346 0 : val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1347 0 : val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1348 0 : WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1349 :
1350 0 : WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1351 :
1352 : /* For MP1 SW irqs */
1353 0 : val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1354 0 : val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1355 0 : WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1356 :
1357 : break;
1358 : case AMDGPU_IRQ_STATE_ENABLE:
1359 : /* For THM irqs */
1360 0 : low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1361 : smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1362 0 : high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1363 : smu->thermal_range.software_shutdown_temp);
1364 :
1365 0 : val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1366 0 : val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1367 0 : val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1368 0 : val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1369 0 : val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1370 0 : val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1371 0 : val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1372 0 : val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1373 0 : WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1374 :
1375 0 : val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1376 0 : val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1377 0 : val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1378 0 : WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1379 :
1380 : /* For MP1 SW irqs */
1381 0 : val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1382 0 : val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1383 0 : val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1384 0 : WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1385 :
1386 0 : val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1387 0 : val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1388 0 : WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1389 :
1390 : break;
1391 : default:
1392 : break;
1393 : }
1394 :
1395 0 : return 0;
1396 : }
1397 :
1398 : static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1399 : {
1400 0 : return smu_cmn_send_smc_msg(smu,
1401 : SMU_MSG_ReenableAcDcInterrupt,
1402 : NULL);
1403 : }
1404 :
1405 : #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1406 : #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1407 : #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1408 :
1409 0 : static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1410 : struct amdgpu_irq_src *source,
1411 : struct amdgpu_iv_entry *entry)
1412 : {
1413 0 : struct smu_context *smu = adev->powerplay.pp_handle;
1414 0 : uint32_t client_id = entry->client_id;
1415 0 : uint32_t src_id = entry->src_id;
1416 : /*
1417 : * ctxid is used to distinguish different
1418 : * events for SMCToHost interrupt.
1419 : */
1420 0 : uint32_t ctxid = entry->src_data[0];
1421 : uint32_t data;
1422 :
1423 0 : if (client_id == SOC15_IH_CLIENTID_THM) {
1424 0 : switch (src_id) {
1425 : case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1426 0 : dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1427 : /*
1428 : * SW CTF just occurred.
1429 : * Try to do a graceful shutdown to prevent further damage.
1430 : */
1431 0 : dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1432 0 : orderly_poweroff(true);
1433 0 : break;
1434 : case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1435 0 : dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1436 0 : break;
1437 : default:
1438 0 : dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1439 : src_id);
1440 0 : break;
1441 : }
1442 0 : } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1443 0 : dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1444 : /*
1445 : * HW CTF just occurred. Shutdown to prevent further damage.
1446 : */
1447 0 : dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1448 0 : orderly_poweroff(true);
1449 0 : } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1450 0 : if (src_id == 0xfe) {
1451 : /* ACK SMUToHost interrupt */
1452 0 : data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1453 0 : data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1454 0 : WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1455 :
1456 0 : switch (ctxid) {
1457 : case 0x3:
1458 : dev_dbg(adev->dev, "Switched to AC mode!\n");
1459 : smu_v13_0_ack_ac_dc_interrupt(smu);
1460 : break;
1461 : case 0x4:
1462 : dev_dbg(adev->dev, "Switched to DC mode!\n");
1463 : smu_v13_0_ack_ac_dc_interrupt(smu);
1464 : break;
1465 : case 0x7:
1466 : /*
1467 : * Increment the throttle interrupt counter
1468 : */
1469 0 : atomic64_inc(&smu->throttle_int_counter);
1470 :
1471 0 : if (!atomic_read(&adev->throttling_logging_enabled))
1472 : return 0;
1473 :
1474 0 : if (__ratelimit(&adev->throttling_logging_rs))
1475 0 : schedule_work(&smu->throttling_logging_work);
1476 :
1477 : break;
1478 : }
1479 : }
1480 : }
1481 :
1482 : return 0;
1483 : }
1484 :
1485 : static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1486 : {
1487 : .set = smu_v13_0_set_irq_state,
1488 : .process = smu_v13_0_irq_process,
1489 : };
1490 :
1491 0 : int smu_v13_0_register_irq_handler(struct smu_context *smu)
1492 : {
1493 0 : struct amdgpu_device *adev = smu->adev;
1494 0 : struct amdgpu_irq_src *irq_src = &smu->irq_source;
1495 0 : int ret = 0;
1496 :
1497 0 : if (amdgpu_sriov_vf(adev))
1498 : return 0;
1499 :
1500 0 : irq_src->num_types = 1;
1501 0 : irq_src->funcs = &smu_v13_0_irq_funcs;
1502 :
1503 0 : ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1504 : THM_11_0__SRCID__THM_DIG_THERM_L2H,
1505 : irq_src);
1506 0 : if (ret)
1507 : return ret;
1508 :
1509 0 : ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1510 : THM_11_0__SRCID__THM_DIG_THERM_H2L,
1511 : irq_src);
1512 0 : if (ret)
1513 : return ret;
1514 :
1515 : /* Register CTF(GPIO_19) interrupt */
1516 0 : ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1517 : SMUIO_11_0__SRCID__SMUIO_GPIO19,
1518 : irq_src);
1519 0 : if (ret)
1520 : return ret;
1521 :
1522 0 : ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1523 : 0xfe,
1524 : irq_src);
1525 : if (ret)
1526 : return ret;
1527 :
1528 : return ret;
1529 : }
1530 :
1531 0 : int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1532 : struct pp_smu_nv_clock_table *max_clocks)
1533 : {
1534 0 : struct smu_table_context *table_context = &smu->smu_table;
1535 0 : struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1536 :
1537 0 : if (!max_clocks || !table_context->max_sustainable_clocks)
1538 : return -EINVAL;
1539 :
1540 0 : sustainable_clocks = table_context->max_sustainable_clocks;
1541 :
1542 0 : max_clocks->dcfClockInKhz =
1543 0 : (unsigned int) sustainable_clocks->dcef_clock * 1000;
1544 0 : max_clocks->displayClockInKhz =
1545 0 : (unsigned int) sustainable_clocks->display_clock * 1000;
1546 0 : max_clocks->phyClockInKhz =
1547 0 : (unsigned int) sustainable_clocks->phy_clock * 1000;
1548 0 : max_clocks->pixelClockInKhz =
1549 0 : (unsigned int) sustainable_clocks->pixel_clock * 1000;
1550 0 : max_clocks->uClockInKhz =
1551 0 : (unsigned int) sustainable_clocks->uclock * 1000;
1552 0 : max_clocks->socClockInKhz =
1553 0 : (unsigned int) sustainable_clocks->soc_clock * 1000;
1554 0 : max_clocks->dscClockInKhz = 0;
1555 0 : max_clocks->dppClockInKhz = 0;
1556 0 : max_clocks->fabricClockInKhz = 0;
1557 :
1558 0 : return 0;
1559 : }
1560 :
1561 0 : int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1562 : {
1563 0 : int ret = 0;
1564 :
1565 0 : ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1566 :
1567 0 : return ret;
1568 : }
1569 :
1570 : static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1571 : uint64_t event_arg)
1572 : {
1573 0 : int ret = 0;
1574 :
1575 : dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1576 0 : ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1577 :
1578 : return ret;
1579 : }
1580 :
1581 0 : int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1582 : uint64_t event_arg)
1583 : {
1584 0 : int ret = -EINVAL;
1585 :
1586 0 : switch (event) {
1587 : case SMU_EVENT_RESET_COMPLETE:
1588 0 : ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1589 0 : break;
1590 : default:
1591 : break;
1592 : }
1593 :
1594 0 : return ret;
1595 : }
1596 :
1597 0 : int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1598 : uint32_t *min, uint32_t *max)
1599 : {
1600 0 : int ret = 0, clk_id = 0;
1601 0 : uint32_t param = 0;
1602 : uint32_t clock_limit;
1603 :
1604 0 : if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1605 0 : switch (clk_type) {
1606 : case SMU_MCLK:
1607 : case SMU_UCLK:
1608 0 : clock_limit = smu->smu_table.boot_values.uclk;
1609 0 : break;
1610 : case SMU_GFXCLK:
1611 : case SMU_SCLK:
1612 0 : clock_limit = smu->smu_table.boot_values.gfxclk;
1613 0 : break;
1614 : case SMU_SOCCLK:
1615 0 : clock_limit = smu->smu_table.boot_values.socclk;
1616 0 : break;
1617 : default:
1618 : clock_limit = 0;
1619 : break;
1620 : }
1621 :
1622 : /* clock in Mhz unit */
1623 0 : if (min)
1624 0 : *min = clock_limit / 100;
1625 0 : if (max)
1626 0 : *max = clock_limit / 100;
1627 :
1628 : return 0;
1629 : }
1630 :
1631 0 : clk_id = smu_cmn_to_asic_specific_index(smu,
1632 : CMN2ASIC_MAPPING_CLK,
1633 : clk_type);
1634 0 : if (clk_id < 0) {
1635 : ret = -EINVAL;
1636 : goto failed;
1637 : }
1638 0 : param = (clk_id & 0xffff) << 16;
1639 :
1640 0 : if (max) {
1641 0 : if (smu->adev->pm.ac_power)
1642 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
1643 : SMU_MSG_GetMaxDpmFreq,
1644 : param,
1645 : max);
1646 : else
1647 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
1648 : SMU_MSG_GetDcModeMaxDpmFreq,
1649 : param,
1650 : max);
1651 0 : if (ret)
1652 : goto failed;
1653 : }
1654 :
1655 0 : if (min) {
1656 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1657 : if (ret)
1658 : goto failed;
1659 : }
1660 :
1661 : failed:
1662 : return ret;
1663 : }
1664 :
1665 0 : int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1666 : enum smu_clk_type clk_type,
1667 : uint32_t min,
1668 : uint32_t max)
1669 : {
1670 0 : int ret = 0, clk_id = 0;
1671 : uint32_t param;
1672 :
1673 0 : if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1674 : return 0;
1675 :
1676 0 : clk_id = smu_cmn_to_asic_specific_index(smu,
1677 : CMN2ASIC_MAPPING_CLK,
1678 : clk_type);
1679 0 : if (clk_id < 0)
1680 : return clk_id;
1681 :
1682 0 : if (max > 0) {
1683 0 : param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1684 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1685 : param, NULL);
1686 0 : if (ret)
1687 : goto out;
1688 : }
1689 :
1690 0 : if (min > 0) {
1691 0 : param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1692 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1693 : param, NULL);
1694 : if (ret)
1695 : goto out;
1696 : }
1697 :
1698 : out:
1699 : return ret;
1700 : }
1701 :
1702 0 : int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1703 : enum smu_clk_type clk_type,
1704 : uint32_t min,
1705 : uint32_t max)
1706 : {
1707 0 : int ret = 0, clk_id = 0;
1708 : uint32_t param;
1709 :
1710 0 : if (min <= 0 && max <= 0)
1711 : return -EINVAL;
1712 :
1713 0 : if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1714 : return 0;
1715 :
1716 0 : clk_id = smu_cmn_to_asic_specific_index(smu,
1717 : CMN2ASIC_MAPPING_CLK,
1718 : clk_type);
1719 0 : if (clk_id < 0)
1720 : return clk_id;
1721 :
1722 0 : if (max > 0) {
1723 0 : param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1724 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1725 : param, NULL);
1726 0 : if (ret)
1727 : return ret;
1728 : }
1729 :
1730 0 : if (min > 0) {
1731 0 : param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1732 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1733 : param, NULL);
1734 : if (ret)
1735 : return ret;
1736 : }
1737 :
1738 : return ret;
1739 : }
1740 :
1741 0 : int smu_v13_0_set_performance_level(struct smu_context *smu,
1742 : enum amd_dpm_forced_level level)
1743 : {
1744 0 : struct smu_13_0_dpm_context *dpm_context =
1745 : smu->smu_dpm.dpm_context;
1746 0 : struct smu_13_0_dpm_table *gfx_table =
1747 : &dpm_context->dpm_tables.gfx_table;
1748 0 : struct smu_13_0_dpm_table *mem_table =
1749 : &dpm_context->dpm_tables.uclk_table;
1750 0 : struct smu_13_0_dpm_table *soc_table =
1751 : &dpm_context->dpm_tables.soc_table;
1752 0 : struct smu_13_0_dpm_table *vclk_table =
1753 : &dpm_context->dpm_tables.vclk_table;
1754 0 : struct smu_13_0_dpm_table *dclk_table =
1755 : &dpm_context->dpm_tables.dclk_table;
1756 0 : struct smu_13_0_dpm_table *fclk_table =
1757 : &dpm_context->dpm_tables.fclk_table;
1758 0 : struct smu_umd_pstate_table *pstate_table =
1759 : &smu->pstate_table;
1760 0 : struct amdgpu_device *adev = smu->adev;
1761 0 : uint32_t sclk_min = 0, sclk_max = 0;
1762 0 : uint32_t mclk_min = 0, mclk_max = 0;
1763 0 : uint32_t socclk_min = 0, socclk_max = 0;
1764 0 : uint32_t vclk_min = 0, vclk_max = 0;
1765 0 : uint32_t dclk_min = 0, dclk_max = 0;
1766 0 : uint32_t fclk_min = 0, fclk_max = 0;
1767 0 : int ret = 0, i;
1768 :
1769 0 : switch (level) {
1770 : case AMD_DPM_FORCED_LEVEL_HIGH:
1771 0 : sclk_min = sclk_max = gfx_table->max;
1772 0 : mclk_min = mclk_max = mem_table->max;
1773 0 : socclk_min = socclk_max = soc_table->max;
1774 0 : vclk_min = vclk_max = vclk_table->max;
1775 0 : dclk_min = dclk_max = dclk_table->max;
1776 0 : fclk_min = fclk_max = fclk_table->max;
1777 0 : break;
1778 : case AMD_DPM_FORCED_LEVEL_LOW:
1779 0 : sclk_min = sclk_max = gfx_table->min;
1780 0 : mclk_min = mclk_max = mem_table->min;
1781 0 : socclk_min = socclk_max = soc_table->min;
1782 0 : vclk_min = vclk_max = vclk_table->min;
1783 0 : dclk_min = dclk_max = dclk_table->min;
1784 0 : fclk_min = fclk_max = fclk_table->min;
1785 0 : break;
1786 : case AMD_DPM_FORCED_LEVEL_AUTO:
1787 0 : sclk_min = gfx_table->min;
1788 0 : sclk_max = gfx_table->max;
1789 0 : mclk_min = mem_table->min;
1790 0 : mclk_max = mem_table->max;
1791 0 : socclk_min = soc_table->min;
1792 0 : socclk_max = soc_table->max;
1793 0 : vclk_min = vclk_table->min;
1794 0 : vclk_max = vclk_table->max;
1795 0 : dclk_min = dclk_table->min;
1796 0 : dclk_max = dclk_table->max;
1797 0 : fclk_min = fclk_table->min;
1798 0 : fclk_max = fclk_table->max;
1799 0 : break;
1800 : case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1801 0 : sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1802 0 : mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1803 0 : socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1804 0 : vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1805 0 : dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1806 0 : fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1807 0 : break;
1808 : case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1809 0 : sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1810 0 : break;
1811 : case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1812 0 : mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1813 0 : break;
1814 : case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1815 0 : sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1816 0 : mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1817 0 : socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1818 0 : vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1819 0 : dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1820 0 : fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1821 0 : break;
1822 : case AMD_DPM_FORCED_LEVEL_MANUAL:
1823 : case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1824 : return 0;
1825 : default:
1826 0 : dev_err(adev->dev, "Invalid performance level %d\n", level);
1827 0 : return -EINVAL;
1828 : }
1829 :
1830 : /*
1831 : * Unset those settings for SMU 13.0.2. As soft limits settings
1832 : * for those clock domains are not supported.
1833 : */
1834 0 : if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1835 0 : mclk_min = mclk_max = 0;
1836 0 : socclk_min = socclk_max = 0;
1837 0 : vclk_min = vclk_max = 0;
1838 0 : dclk_min = dclk_max = 0;
1839 0 : fclk_min = fclk_max = 0;
1840 : }
1841 :
1842 0 : if (sclk_min && sclk_max) {
1843 0 : ret = smu_v13_0_set_soft_freq_limited_range(smu,
1844 : SMU_GFXCLK,
1845 : sclk_min,
1846 : sclk_max);
1847 0 : if (ret)
1848 : return ret;
1849 :
1850 0 : pstate_table->gfxclk_pstate.curr.min = sclk_min;
1851 0 : pstate_table->gfxclk_pstate.curr.max = sclk_max;
1852 : }
1853 :
1854 0 : if (mclk_min && mclk_max) {
1855 0 : ret = smu_v13_0_set_soft_freq_limited_range(smu,
1856 : SMU_MCLK,
1857 : mclk_min,
1858 : mclk_max);
1859 0 : if (ret)
1860 : return ret;
1861 :
1862 0 : pstate_table->uclk_pstate.curr.min = mclk_min;
1863 0 : pstate_table->uclk_pstate.curr.max = mclk_max;
1864 : }
1865 :
1866 0 : if (socclk_min && socclk_max) {
1867 0 : ret = smu_v13_0_set_soft_freq_limited_range(smu,
1868 : SMU_SOCCLK,
1869 : socclk_min,
1870 : socclk_max);
1871 0 : if (ret)
1872 : return ret;
1873 :
1874 0 : pstate_table->socclk_pstate.curr.min = socclk_min;
1875 0 : pstate_table->socclk_pstate.curr.max = socclk_max;
1876 : }
1877 :
1878 0 : if (vclk_min && vclk_max) {
1879 0 : for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1880 0 : if (adev->vcn.harvest_config & (1 << i))
1881 0 : continue;
1882 0 : ret = smu_v13_0_set_soft_freq_limited_range(smu,
1883 : i ? SMU_VCLK1 : SMU_VCLK,
1884 : vclk_min,
1885 : vclk_max);
1886 0 : if (ret)
1887 : return ret;
1888 : }
1889 0 : pstate_table->vclk_pstate.curr.min = vclk_min;
1890 0 : pstate_table->vclk_pstate.curr.max = vclk_max;
1891 : }
1892 :
1893 0 : if (dclk_min && dclk_max) {
1894 0 : for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1895 0 : if (adev->vcn.harvest_config & (1 << i))
1896 0 : continue;
1897 0 : ret = smu_v13_0_set_soft_freq_limited_range(smu,
1898 : i ? SMU_DCLK1 : SMU_DCLK,
1899 : dclk_min,
1900 : dclk_max);
1901 0 : if (ret)
1902 : return ret;
1903 : }
1904 0 : pstate_table->dclk_pstate.curr.min = dclk_min;
1905 0 : pstate_table->dclk_pstate.curr.max = dclk_max;
1906 : }
1907 :
1908 0 : if (fclk_min && fclk_max) {
1909 0 : ret = smu_v13_0_set_soft_freq_limited_range(smu,
1910 : SMU_FCLK,
1911 : fclk_min,
1912 : fclk_max);
1913 0 : if (ret)
1914 : return ret;
1915 :
1916 0 : pstate_table->fclk_pstate.curr.min = fclk_min;
1917 0 : pstate_table->fclk_pstate.curr.max = fclk_max;
1918 : }
1919 :
1920 : return ret;
1921 : }
1922 :
1923 0 : int smu_v13_0_set_power_source(struct smu_context *smu,
1924 : enum smu_power_src_type power_src)
1925 : {
1926 : int pwr_source;
1927 :
1928 0 : pwr_source = smu_cmn_to_asic_specific_index(smu,
1929 : CMN2ASIC_MAPPING_PWR,
1930 : (uint32_t)power_src);
1931 0 : if (pwr_source < 0)
1932 : return -EINVAL;
1933 :
1934 0 : return smu_cmn_send_smc_msg_with_param(smu,
1935 : SMU_MSG_NotifyPowerSource,
1936 : pwr_source,
1937 : NULL);
1938 : }
1939 :
1940 0 : static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1941 : enum smu_clk_type clk_type,
1942 : uint16_t level,
1943 : uint32_t *value)
1944 : {
1945 0 : int ret = 0, clk_id = 0;
1946 : uint32_t param;
1947 :
1948 0 : if (!value)
1949 : return -EINVAL;
1950 :
1951 0 : if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1952 : return 0;
1953 :
1954 0 : clk_id = smu_cmn_to_asic_specific_index(smu,
1955 : CMN2ASIC_MAPPING_CLK,
1956 : clk_type);
1957 0 : if (clk_id < 0)
1958 : return clk_id;
1959 :
1960 0 : param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1961 :
1962 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
1963 : SMU_MSG_GetDpmFreqByIndex,
1964 : param,
1965 : value);
1966 0 : if (ret)
1967 : return ret;
1968 :
1969 0 : *value = *value & 0x7fffffff;
1970 :
1971 0 : return ret;
1972 : }
1973 :
1974 0 : static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1975 : enum smu_clk_type clk_type,
1976 : uint32_t *value)
1977 : {
1978 : int ret;
1979 :
1980 0 : ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1981 : /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1982 0 : if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1983 0 : ++(*value);
1984 :
1985 0 : return ret;
1986 : }
1987 :
1988 0 : static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1989 : enum smu_clk_type clk_type,
1990 : bool *is_fine_grained_dpm)
1991 : {
1992 0 : int ret = 0, clk_id = 0;
1993 : uint32_t param;
1994 : uint32_t value;
1995 :
1996 0 : if (!is_fine_grained_dpm)
1997 : return -EINVAL;
1998 :
1999 0 : if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
2000 : return 0;
2001 :
2002 0 : clk_id = smu_cmn_to_asic_specific_index(smu,
2003 : CMN2ASIC_MAPPING_CLK,
2004 : clk_type);
2005 0 : if (clk_id < 0)
2006 : return clk_id;
2007 :
2008 0 : param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
2009 :
2010 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
2011 : SMU_MSG_GetDpmFreqByIndex,
2012 : param,
2013 : &value);
2014 0 : if (ret)
2015 : return ret;
2016 :
2017 : /*
2018 : * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
2019 : * now, we un-support it
2020 : */
2021 0 : *is_fine_grained_dpm = value & 0x80000000;
2022 :
2023 0 : return 0;
2024 : }
2025 :
2026 0 : int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
2027 : enum smu_clk_type clk_type,
2028 : struct smu_13_0_dpm_table *single_dpm_table)
2029 : {
2030 0 : int ret = 0;
2031 : uint32_t clk;
2032 : int i;
2033 :
2034 0 : ret = smu_v13_0_get_dpm_level_count(smu,
2035 : clk_type,
2036 : &single_dpm_table->count);
2037 0 : if (ret) {
2038 0 : dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2039 0 : return ret;
2040 : }
2041 :
2042 0 : if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
2043 0 : ret = smu_v13_0_get_fine_grained_status(smu,
2044 : clk_type,
2045 : &single_dpm_table->is_fine_grained);
2046 0 : if (ret) {
2047 0 : dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2048 0 : return ret;
2049 : }
2050 : }
2051 :
2052 0 : for (i = 0; i < single_dpm_table->count; i++) {
2053 0 : ret = smu_v13_0_get_dpm_freq_by_index(smu,
2054 : clk_type,
2055 : i,
2056 : &clk);
2057 0 : if (ret) {
2058 0 : dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2059 0 : return ret;
2060 : }
2061 :
2062 0 : single_dpm_table->dpm_levels[i].value = clk;
2063 0 : single_dpm_table->dpm_levels[i].enabled = true;
2064 :
2065 0 : if (i == 0)
2066 0 : single_dpm_table->min = clk;
2067 0 : else if (i == single_dpm_table->count - 1)
2068 0 : single_dpm_table->max = clk;
2069 : }
2070 :
2071 : return 0;
2072 : }
2073 :
2074 0 : int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2075 : enum smu_clk_type clk_type,
2076 : uint32_t *min_value,
2077 : uint32_t *max_value)
2078 : {
2079 0 : uint32_t level_count = 0;
2080 0 : int ret = 0;
2081 :
2082 0 : if (!min_value && !max_value)
2083 : return -EINVAL;
2084 :
2085 0 : if (min_value) {
2086 : /* by default, level 0 clock value as min value */
2087 0 : ret = smu_v13_0_get_dpm_freq_by_index(smu,
2088 : clk_type,
2089 : 0,
2090 : min_value);
2091 0 : if (ret)
2092 : return ret;
2093 : }
2094 :
2095 0 : if (max_value) {
2096 0 : ret = smu_v13_0_get_dpm_level_count(smu,
2097 : clk_type,
2098 : &level_count);
2099 0 : if (ret)
2100 : return ret;
2101 :
2102 0 : ret = smu_v13_0_get_dpm_freq_by_index(smu,
2103 : clk_type,
2104 0 : level_count - 1,
2105 : max_value);
2106 0 : if (ret)
2107 : return ret;
2108 : }
2109 :
2110 : return ret;
2111 : }
2112 :
2113 0 : int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2114 : {
2115 0 : struct amdgpu_device *adev = smu->adev;
2116 :
2117 0 : return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2118 : PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2119 0 : >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2120 : }
2121 :
2122 0 : int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2123 : {
2124 : uint32_t width_level;
2125 :
2126 0 : width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2127 0 : if (width_level > LINK_WIDTH_MAX)
2128 0 : width_level = 0;
2129 :
2130 0 : return link_width[width_level];
2131 : }
2132 :
2133 0 : int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2134 : {
2135 0 : struct amdgpu_device *adev = smu->adev;
2136 :
2137 0 : return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2138 : PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2139 0 : >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2140 : }
2141 :
2142 0 : int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2143 : {
2144 : uint32_t speed_level;
2145 :
2146 0 : speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2147 0 : if (speed_level > LINK_SPEED_MAX)
2148 0 : speed_level = 0;
2149 :
2150 0 : return link_speed[speed_level];
2151 : }
2152 :
2153 0 : int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2154 : bool enable)
2155 : {
2156 0 : struct amdgpu_device *adev = smu->adev;
2157 0 : int i, ret = 0;
2158 :
2159 0 : for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2160 0 : if (adev->vcn.harvest_config & (1 << i))
2161 0 : continue;
2162 :
2163 0 : ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2164 : SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2165 0 : i << 16U, NULL);
2166 0 : if (ret)
2167 : return ret;
2168 : }
2169 :
2170 : return ret;
2171 : }
2172 :
2173 0 : int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2174 : bool enable)
2175 : {
2176 0 : return smu_cmn_send_smc_msg_with_param(smu, enable ?
2177 : SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2178 : 0, NULL);
2179 : }
2180 :
2181 0 : int smu_v13_0_run_btc(struct smu_context *smu)
2182 : {
2183 : int res;
2184 :
2185 0 : res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2186 0 : if (res)
2187 0 : dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2188 :
2189 0 : return res;
2190 : }
2191 :
2192 0 : int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2193 : bool enablement)
2194 : {
2195 0 : struct amdgpu_device *adev = smu->adev;
2196 0 : int ret = 0;
2197 :
2198 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2199 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2200 0 : if (ret) {
2201 0 : dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2202 0 : return ret;
2203 : }
2204 : }
2205 :
2206 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2207 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2208 0 : if (ret) {
2209 0 : dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2210 0 : return ret;
2211 : }
2212 : }
2213 :
2214 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2215 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2216 0 : if (ret) {
2217 0 : dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2218 0 : return ret;
2219 : }
2220 : }
2221 :
2222 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2223 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2224 0 : if (ret) {
2225 0 : dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2226 0 : return ret;
2227 : }
2228 : }
2229 :
2230 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2231 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2232 0 : if (ret) {
2233 0 : dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2234 0 : return ret;
2235 : }
2236 : }
2237 :
2238 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2239 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2240 0 : if (ret) {
2241 0 : dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2242 0 : return ret;
2243 : }
2244 : }
2245 :
2246 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2247 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2248 0 : if (ret) {
2249 0 : dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2250 0 : return ret;
2251 : }
2252 : }
2253 :
2254 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2255 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2256 0 : if (ret) {
2257 0 : dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2258 0 : return ret;
2259 : }
2260 : }
2261 :
2262 : return ret;
2263 : }
2264 :
2265 0 : int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2266 : bool enablement)
2267 : {
2268 0 : int ret = 0;
2269 :
2270 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2271 0 : ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2272 :
2273 0 : return ret;
2274 : }
2275 :
2276 0 : bool smu_v13_0_baco_is_support(struct smu_context *smu)
2277 : {
2278 0 : struct smu_baco_context *smu_baco = &smu->smu_baco;
2279 :
2280 0 : if (amdgpu_sriov_vf(smu->adev) ||
2281 0 : !smu_baco->platform_support)
2282 : return false;
2283 :
2284 0 : if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2285 0 : !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2286 : return false;
2287 :
2288 : return true;
2289 : }
2290 :
2291 0 : enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2292 : {
2293 0 : struct smu_baco_context *smu_baco = &smu->smu_baco;
2294 :
2295 0 : return smu_baco->state;
2296 : }
2297 :
2298 0 : int smu_v13_0_baco_set_state(struct smu_context *smu,
2299 : enum smu_baco_state state)
2300 : {
2301 0 : struct smu_baco_context *smu_baco = &smu->smu_baco;
2302 0 : struct amdgpu_device *adev = smu->adev;
2303 0 : int ret = 0;
2304 :
2305 0 : if (smu_v13_0_baco_get_state(smu) == state)
2306 : return 0;
2307 :
2308 0 : if (state == SMU_BACO_STATE_ENTER) {
2309 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
2310 : SMU_MSG_EnterBaco,
2311 0 : smu_baco->maco_support ?
2312 : BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2313 : NULL);
2314 : } else {
2315 0 : ret = smu_cmn_send_smc_msg(smu,
2316 : SMU_MSG_ExitBaco,
2317 : NULL);
2318 0 : if (ret)
2319 : return ret;
2320 :
2321 : /* clear vbios scratch 6 and 7 for coming asic reinit */
2322 0 : WREG32(adev->bios_scratch_reg_offset + 6, 0);
2323 0 : WREG32(adev->bios_scratch_reg_offset + 7, 0);
2324 : }
2325 :
2326 0 : if (!ret)
2327 0 : smu_baco->state = state;
2328 :
2329 : return ret;
2330 : }
2331 :
2332 0 : int smu_v13_0_baco_enter(struct smu_context *smu)
2333 : {
2334 0 : int ret = 0;
2335 :
2336 0 : ret = smu_v13_0_baco_set_state(smu,
2337 : SMU_BACO_STATE_ENTER);
2338 0 : if (ret)
2339 : return ret;
2340 :
2341 0 : msleep(10);
2342 :
2343 0 : return ret;
2344 : }
2345 :
2346 0 : int smu_v13_0_baco_exit(struct smu_context *smu)
2347 : {
2348 0 : return smu_v13_0_baco_set_state(smu,
2349 : SMU_BACO_STATE_EXIT);
2350 : }
2351 :
2352 0 : int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2353 : {
2354 : uint16_t index;
2355 :
2356 0 : index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2357 : SMU_MSG_EnableGfxImu);
2358 : /* Param 1 to tell PMFW to enable GFXOFF feature */
2359 0 : return smu_cmn_send_msg_without_waiting(smu, index, 1);
2360 : }
2361 :
2362 0 : int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2363 : enum PP_OD_DPM_TABLE_COMMAND type,
2364 : long input[], uint32_t size)
2365 : {
2366 0 : struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2367 0 : int ret = 0;
2368 :
2369 : /* Only allowed in manual mode */
2370 0 : if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2371 : return -EINVAL;
2372 :
2373 0 : switch (type) {
2374 : case PP_OD_EDIT_SCLK_VDDC_TABLE:
2375 0 : if (size != 2) {
2376 0 : dev_err(smu->adev->dev, "Input parameter number not correct\n");
2377 0 : return -EINVAL;
2378 : }
2379 :
2380 0 : if (input[0] == 0) {
2381 0 : if (input[1] < smu->gfx_default_hard_min_freq) {
2382 0 : dev_warn(smu->adev->dev,
2383 : "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2384 : input[1], smu->gfx_default_hard_min_freq);
2385 0 : return -EINVAL;
2386 : }
2387 0 : smu->gfx_actual_hard_min_freq = input[1];
2388 0 : } else if (input[0] == 1) {
2389 0 : if (input[1] > smu->gfx_default_soft_max_freq) {
2390 0 : dev_warn(smu->adev->dev,
2391 : "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2392 : input[1], smu->gfx_default_soft_max_freq);
2393 0 : return -EINVAL;
2394 : }
2395 0 : smu->gfx_actual_soft_max_freq = input[1];
2396 : } else {
2397 : return -EINVAL;
2398 : }
2399 : break;
2400 : case PP_OD_RESTORE_DEFAULT_TABLE:
2401 0 : if (size != 0) {
2402 0 : dev_err(smu->adev->dev, "Input parameter number not correct\n");
2403 0 : return -EINVAL;
2404 : }
2405 0 : smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2406 0 : smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2407 0 : break;
2408 : case PP_OD_COMMIT_DPM_TABLE:
2409 0 : if (size != 0) {
2410 0 : dev_err(smu->adev->dev, "Input parameter number not correct\n");
2411 0 : return -EINVAL;
2412 : }
2413 0 : if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2414 0 : dev_err(smu->adev->dev,
2415 : "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2416 : smu->gfx_actual_hard_min_freq,
2417 : smu->gfx_actual_soft_max_freq);
2418 0 : return -EINVAL;
2419 : }
2420 :
2421 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2422 : smu->gfx_actual_hard_min_freq,
2423 : NULL);
2424 0 : if (ret) {
2425 0 : dev_err(smu->adev->dev, "Set hard min sclk failed!");
2426 0 : return ret;
2427 : }
2428 :
2429 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2430 : smu->gfx_actual_soft_max_freq,
2431 : NULL);
2432 0 : if (ret) {
2433 0 : dev_err(smu->adev->dev, "Set soft max sclk failed!");
2434 0 : return ret;
2435 : }
2436 : break;
2437 : default:
2438 : return -ENOSYS;
2439 : }
2440 :
2441 : return ret;
2442 : }
2443 :
2444 0 : int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2445 : {
2446 0 : struct smu_table_context *smu_table = &smu->smu_table;
2447 :
2448 0 : return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2449 : smu_table->clocks_table, false);
2450 : }
2451 :
2452 0 : void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2453 : {
2454 0 : struct amdgpu_device *adev = smu->adev;
2455 :
2456 0 : smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2457 0 : smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2458 0 : smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2459 0 : }
2460 :
2461 0 : int smu_v13_0_mode1_reset(struct smu_context *smu)
2462 : {
2463 0 : int ret = 0;
2464 :
2465 0 : ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2466 0 : if (!ret)
2467 0 : msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2468 :
2469 0 : return ret;
2470 : }
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