Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #define SWSMU_CODE_LAYER_L2
25 :
26 : #include "amdgpu.h"
27 : #include "amdgpu_smu.h"
28 : #include "smu_v13_0.h"
29 : #include "smu13_driver_if_yellow_carp.h"
30 : #include "yellow_carp_ppt.h"
31 : #include "smu_v13_0_1_ppsmc.h"
32 : #include "smu_v13_0_1_pmfw.h"
33 : #include "smu_cmn.h"
34 :
35 : /*
36 : * DO NOT use these for err/warn/info/debug messages.
37 : * Use dev_err, dev_warn, dev_info and dev_dbg instead.
38 : * They are more MGPU friendly.
39 : */
40 : #undef pr_err
41 : #undef pr_warn
42 : #undef pr_info
43 : #undef pr_debug
44 :
45 : #define regSMUIO_GFX_MISC_CNTL 0x00c5
46 : #define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0
47 : #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
48 : #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1L
49 :
50 : #define FEATURE_MASK(feature) (1ULL << feature)
51 : #define SMC_DPM_FEATURE ( \
52 : FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
53 : FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
54 : FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
55 : FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
56 : FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
57 : FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
58 : FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
59 : FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
60 : FEATURE_MASK(FEATURE_GFX_DPM_BIT))
61 :
62 : static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = {
63 : MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
64 : MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
65 : MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
66 : MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1),
67 : MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
68 : MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
69 : MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
70 : MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
71 : MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
72 : MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
73 : MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
74 : MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
75 : MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
76 : MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
77 : MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
78 : MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
79 : MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
80 : MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
81 : MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
82 : MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
83 : MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
84 : MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
85 : MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
86 : MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
87 : MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
88 : MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
89 : MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
90 : MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
91 : MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
92 : MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
93 : };
94 :
95 : static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = {
96 : FEA_MAP(CCLK_DPM),
97 : FEA_MAP(FAN_CONTROLLER),
98 : FEA_MAP(PPT),
99 : FEA_MAP(TDC),
100 : FEA_MAP(THERMAL),
101 : FEA_MAP(ULV),
102 : FEA_MAP(VCN_DPM),
103 : FEA_MAP_REVERSE(FCLK),
104 : FEA_MAP_REVERSE(SOCCLK),
105 : FEA_MAP(LCLK_DPM),
106 : FEA_MAP(SHUBCLK_DPM),
107 : FEA_MAP(DCFCLK_DPM),
108 : FEA_MAP_HALF_REVERSE(GFX),
109 : FEA_MAP(DS_GFXCLK),
110 : FEA_MAP(DS_SOCCLK),
111 : FEA_MAP(DS_LCLK),
112 : FEA_MAP(DS_DCFCLK),
113 : FEA_MAP(DS_FCLK),
114 : FEA_MAP(DS_MP1CLK),
115 : FEA_MAP(DS_MP0CLK),
116 : FEA_MAP(GFX_DEM),
117 : FEA_MAP(PSI),
118 : FEA_MAP(PROCHOT),
119 : FEA_MAP(CPUOFF),
120 : FEA_MAP(STAPM),
121 : FEA_MAP(S0I3),
122 : FEA_MAP(PERF_LIMIT),
123 : FEA_MAP(CORE_DLDO),
124 : FEA_MAP(RSMU_LOW_POWER),
125 : FEA_MAP(SMN_LOW_POWER),
126 : FEA_MAP(THM_LOW_POWER),
127 : FEA_MAP(SMUIO_LOW_POWER),
128 : FEA_MAP(MP1_LOW_POWER),
129 : FEA_MAP(DS_VCN),
130 : FEA_MAP(CPPC),
131 : FEA_MAP(DF_CSTATES),
132 : FEA_MAP(MSMU_LOW_POWER),
133 : FEA_MAP(ATHUB_PG),
134 : };
135 :
136 : static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
137 : TAB_MAP_VALID(WATERMARKS),
138 : TAB_MAP_VALID(SMU_METRICS),
139 : TAB_MAP_VALID(CUSTOM_DPM),
140 : TAB_MAP_VALID(DPMCLOCKS),
141 : };
142 :
143 0 : static int yellow_carp_init_smc_tables(struct smu_context *smu)
144 : {
145 0 : struct smu_table_context *smu_table = &smu->smu_table;
146 0 : struct smu_table *tables = smu_table->tables;
147 :
148 0 : SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
149 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
150 0 : SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
151 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
152 0 : SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
153 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
154 :
155 0 : smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
156 0 : if (!smu_table->clocks_table)
157 : goto err0_out;
158 :
159 0 : smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
160 0 : if (!smu_table->metrics_table)
161 : goto err1_out;
162 0 : smu_table->metrics_time = 0;
163 :
164 0 : smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
165 0 : if (!smu_table->watermarks_table)
166 : goto err2_out;
167 :
168 0 : smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
169 0 : smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
170 0 : if (!smu_table->gpu_metrics_table)
171 : goto err3_out;
172 :
173 : return 0;
174 :
175 : err3_out:
176 0 : kfree(smu_table->watermarks_table);
177 : err2_out:
178 0 : kfree(smu_table->metrics_table);
179 : err1_out:
180 0 : kfree(smu_table->clocks_table);
181 : err0_out:
182 : return -ENOMEM;
183 : }
184 :
185 0 : static int yellow_carp_fini_smc_tables(struct smu_context *smu)
186 : {
187 0 : struct smu_table_context *smu_table = &smu->smu_table;
188 :
189 0 : kfree(smu_table->clocks_table);
190 0 : smu_table->clocks_table = NULL;
191 :
192 0 : kfree(smu_table->metrics_table);
193 0 : smu_table->metrics_table = NULL;
194 :
195 0 : kfree(smu_table->watermarks_table);
196 0 : smu_table->watermarks_table = NULL;
197 :
198 0 : kfree(smu_table->gpu_metrics_table);
199 0 : smu_table->gpu_metrics_table = NULL;
200 :
201 0 : return 0;
202 : }
203 :
204 0 : static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
205 : {
206 0 : struct amdgpu_device *adev = smu->adev;
207 0 : int ret = 0;
208 :
209 0 : if (!en && !adev->in_s0ix)
210 0 : ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
211 :
212 0 : return ret;
213 : }
214 :
215 0 : static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
216 : {
217 0 : int ret = 0;
218 :
219 : /* vcn dpm on is a prerequisite for vcn power gate messages */
220 0 : if (enable)
221 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
222 : 0, NULL);
223 : else
224 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
225 : 0, NULL);
226 :
227 0 : return ret;
228 : }
229 :
230 0 : static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
231 : {
232 0 : int ret = 0;
233 :
234 0 : if (enable)
235 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
236 : 0, NULL);
237 : else
238 0 : ret = smu_cmn_send_smc_msg_with_param(smu,
239 : SMU_MSG_PowerDownJpeg, 0,
240 : NULL);
241 :
242 0 : return ret;
243 : }
244 :
245 :
246 0 : static bool yellow_carp_is_dpm_running(struct smu_context *smu)
247 : {
248 0 : int ret = 0;
249 : uint64_t feature_enabled;
250 :
251 0 : ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
252 :
253 0 : if (ret)
254 : return false;
255 :
256 0 : return !!(feature_enabled & SMC_DPM_FEATURE);
257 : }
258 :
259 0 : static int yellow_carp_post_smu_init(struct smu_context *smu)
260 : {
261 0 : struct amdgpu_device *adev = smu->adev;
262 0 : int ret = 0;
263 :
264 : /* allow message will be sent after enable message on Yellow Carp*/
265 0 : ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
266 0 : if (ret)
267 0 : dev_err(adev->dev, "Failed to Enable GfxOff!\n");
268 0 : return ret;
269 : }
270 :
271 0 : static int yellow_carp_mode_reset(struct smu_context *smu, int type)
272 : {
273 0 : int ret = 0;
274 :
275 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
276 0 : if (ret)
277 0 : dev_err(smu->adev->dev, "Failed to mode reset!\n");
278 :
279 0 : return ret;
280 : }
281 :
282 0 : static int yellow_carp_mode2_reset(struct smu_context *smu)
283 : {
284 0 : return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2);
285 : }
286 :
287 :
288 0 : static void yellow_carp_get_ss_power_percent(SmuMetrics_t *metrics,
289 : uint32_t *apu_percent, uint32_t *dgpu_percent)
290 : {
291 0 : uint32_t apu_boost = 0;
292 0 : uint32_t dgpu_boost = 0;
293 0 : uint16_t apu_limit = 0;
294 0 : uint16_t dgpu_limit = 0;
295 0 : uint16_t apu_power = 0;
296 0 : uint16_t dgpu_power = 0;
297 :
298 : /* APU and dGPU power values are reported in milli Watts
299 : * and STAPM power limits are in Watts */
300 0 : apu_power = metrics->ApuPower/1000;
301 0 : apu_limit = metrics->StapmOpnLimit;
302 0 : if (apu_power > apu_limit && apu_limit != 0)
303 0 : apu_boost = ((apu_power - apu_limit) * 100) / apu_limit;
304 0 : apu_boost = (apu_boost > 100) ? 100 : apu_boost;
305 :
306 0 : dgpu_power = metrics->dGpuPower/1000;
307 0 : if (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)
308 0 : dgpu_limit = metrics->StapmCurrentLimit - metrics->StapmOpnLimit;
309 0 : if (dgpu_power > dgpu_limit && dgpu_limit != 0)
310 0 : dgpu_boost = ((dgpu_power - dgpu_limit) * 100) / dgpu_limit;
311 0 : dgpu_boost = (dgpu_boost > 100) ? 100 : dgpu_boost;
312 :
313 0 : if (dgpu_boost >= apu_boost)
314 : apu_boost = 0;
315 : else
316 0 : dgpu_boost = 0;
317 :
318 0 : *apu_percent = apu_boost;
319 0 : *dgpu_percent = dgpu_boost;
320 :
321 0 : }
322 :
323 0 : static int yellow_carp_get_smu_metrics_data(struct smu_context *smu,
324 : MetricsMember_t member,
325 : uint32_t *value)
326 : {
327 0 : struct smu_table_context *smu_table = &smu->smu_table;
328 :
329 0 : SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
330 0 : int ret = 0;
331 0 : uint32_t apu_percent = 0;
332 0 : uint32_t dgpu_percent = 0;
333 :
334 0 : ret = smu_cmn_get_metrics_table(smu, NULL, false);
335 0 : if (ret)
336 : return ret;
337 :
338 0 : switch (member) {
339 : case METRICS_AVERAGE_GFXCLK:
340 0 : *value = metrics->GfxclkFrequency;
341 0 : break;
342 : case METRICS_AVERAGE_SOCCLK:
343 0 : *value = metrics->SocclkFrequency;
344 0 : break;
345 : case METRICS_AVERAGE_VCLK:
346 0 : *value = metrics->VclkFrequency;
347 0 : break;
348 : case METRICS_AVERAGE_DCLK:
349 0 : *value = metrics->DclkFrequency;
350 0 : break;
351 : case METRICS_AVERAGE_UCLK:
352 0 : *value = metrics->MemclkFrequency;
353 0 : break;
354 : case METRICS_AVERAGE_GFXACTIVITY:
355 0 : *value = metrics->GfxActivity / 100;
356 0 : break;
357 : case METRICS_AVERAGE_VCNACTIVITY:
358 0 : *value = metrics->UvdActivity;
359 0 : break;
360 : case METRICS_AVERAGE_SOCKETPOWER:
361 0 : *value = (metrics->CurrentSocketPower << 8) / 1000;
362 0 : break;
363 : case METRICS_TEMPERATURE_EDGE:
364 0 : *value = metrics->GfxTemperature / 100 *
365 : SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
366 0 : break;
367 : case METRICS_TEMPERATURE_HOTSPOT:
368 0 : *value = metrics->SocTemperature / 100 *
369 : SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
370 0 : break;
371 : case METRICS_THROTTLER_STATUS:
372 0 : *value = metrics->ThrottlerStatus;
373 0 : break;
374 : case METRICS_VOLTAGE_VDDGFX:
375 0 : *value = metrics->Voltage[0];
376 0 : break;
377 : case METRICS_VOLTAGE_VDDSOC:
378 0 : *value = metrics->Voltage[1];
379 0 : break;
380 : case METRICS_SS_APU_SHARE:
381 : /* return the percentage of APU power boost
382 : * with respect to APU's power limit.
383 : */
384 0 : yellow_carp_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
385 0 : *value = apu_percent;
386 0 : break;
387 : case METRICS_SS_DGPU_SHARE:
388 : /* return the percentage of dGPU power boost
389 : * with respect to dGPU's power limit.
390 : */
391 0 : yellow_carp_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
392 0 : *value = dgpu_percent;
393 0 : break;
394 : default:
395 0 : *value = UINT_MAX;
396 0 : break;
397 : }
398 :
399 : return ret;
400 : }
401 :
402 0 : static int yellow_carp_read_sensor(struct smu_context *smu,
403 : enum amd_pp_sensors sensor,
404 : void *data, uint32_t *size)
405 : {
406 0 : int ret = 0;
407 :
408 0 : if (!data || !size)
409 : return -EINVAL;
410 :
411 0 : switch (sensor) {
412 : case AMDGPU_PP_SENSOR_GPU_LOAD:
413 0 : ret = yellow_carp_get_smu_metrics_data(smu,
414 : METRICS_AVERAGE_GFXACTIVITY,
415 : (uint32_t *)data);
416 0 : *size = 4;
417 0 : break;
418 : case AMDGPU_PP_SENSOR_GPU_POWER:
419 0 : ret = yellow_carp_get_smu_metrics_data(smu,
420 : METRICS_AVERAGE_SOCKETPOWER,
421 : (uint32_t *)data);
422 0 : *size = 4;
423 0 : break;
424 : case AMDGPU_PP_SENSOR_EDGE_TEMP:
425 0 : ret = yellow_carp_get_smu_metrics_data(smu,
426 : METRICS_TEMPERATURE_EDGE,
427 : (uint32_t *)data);
428 0 : *size = 4;
429 0 : break;
430 : case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
431 0 : ret = yellow_carp_get_smu_metrics_data(smu,
432 : METRICS_TEMPERATURE_HOTSPOT,
433 : (uint32_t *)data);
434 0 : *size = 4;
435 0 : break;
436 : case AMDGPU_PP_SENSOR_GFX_MCLK:
437 0 : ret = yellow_carp_get_smu_metrics_data(smu,
438 : METRICS_AVERAGE_UCLK,
439 : (uint32_t *)data);
440 0 : *(uint32_t *)data *= 100;
441 0 : *size = 4;
442 0 : break;
443 : case AMDGPU_PP_SENSOR_GFX_SCLK:
444 0 : ret = yellow_carp_get_smu_metrics_data(smu,
445 : METRICS_AVERAGE_GFXCLK,
446 : (uint32_t *)data);
447 0 : *(uint32_t *)data *= 100;
448 0 : *size = 4;
449 0 : break;
450 : case AMDGPU_PP_SENSOR_VDDGFX:
451 0 : ret = yellow_carp_get_smu_metrics_data(smu,
452 : METRICS_VOLTAGE_VDDGFX,
453 : (uint32_t *)data);
454 0 : *size = 4;
455 0 : break;
456 : case AMDGPU_PP_SENSOR_VDDNB:
457 0 : ret = yellow_carp_get_smu_metrics_data(smu,
458 : METRICS_VOLTAGE_VDDSOC,
459 : (uint32_t *)data);
460 0 : *size = 4;
461 0 : break;
462 : case AMDGPU_PP_SENSOR_SS_APU_SHARE:
463 0 : ret = yellow_carp_get_smu_metrics_data(smu,
464 : METRICS_SS_APU_SHARE,
465 : (uint32_t *)data);
466 0 : *size = 4;
467 0 : break;
468 : case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
469 0 : ret = yellow_carp_get_smu_metrics_data(smu,
470 : METRICS_SS_DGPU_SHARE,
471 : (uint32_t *)data);
472 0 : *size = 4;
473 0 : break;
474 : default:
475 : ret = -EOPNOTSUPP;
476 : break;
477 : }
478 :
479 : return ret;
480 : }
481 :
482 0 : static int yellow_carp_set_watermarks_table(struct smu_context *smu,
483 : struct pp_smu_wm_range_sets *clock_ranges)
484 : {
485 : int i;
486 0 : int ret = 0;
487 0 : Watermarks_t *table = smu->smu_table.watermarks_table;
488 :
489 0 : if (!table || !clock_ranges)
490 : return -EINVAL;
491 :
492 0 : if (clock_ranges) {
493 0 : if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
494 0 : clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
495 : return -EINVAL;
496 :
497 0 : for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
498 0 : table->WatermarkRow[WM_DCFCLK][i].MinClock =
499 0 : clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
500 0 : table->WatermarkRow[WM_DCFCLK][i].MaxClock =
501 0 : clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
502 0 : table->WatermarkRow[WM_DCFCLK][i].MinMclk =
503 0 : clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
504 0 : table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
505 0 : clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
506 :
507 0 : table->WatermarkRow[WM_DCFCLK][i].WmSetting =
508 0 : clock_ranges->reader_wm_sets[i].wm_inst;
509 : }
510 :
511 0 : for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
512 0 : table->WatermarkRow[WM_SOCCLK][i].MinClock =
513 0 : clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
514 0 : table->WatermarkRow[WM_SOCCLK][i].MaxClock =
515 0 : clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
516 0 : table->WatermarkRow[WM_SOCCLK][i].MinMclk =
517 0 : clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
518 0 : table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
519 0 : clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
520 :
521 0 : table->WatermarkRow[WM_SOCCLK][i].WmSetting =
522 0 : clock_ranges->writer_wm_sets[i].wm_inst;
523 : }
524 :
525 0 : smu->watermarks_bitmap |= WATERMARKS_EXIST;
526 : }
527 :
528 : /* pass data to smu controller */
529 0 : if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
530 : !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
531 0 : ret = smu_cmn_write_watermarks_table(smu);
532 0 : if (ret) {
533 0 : dev_err(smu->adev->dev, "Failed to update WMTABLE!");
534 0 : return ret;
535 : }
536 0 : smu->watermarks_bitmap |= WATERMARKS_LOADED;
537 : }
538 :
539 : return 0;
540 : }
541 :
542 0 : static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
543 : void **table)
544 : {
545 0 : struct smu_table_context *smu_table = &smu->smu_table;
546 0 : struct gpu_metrics_v2_1 *gpu_metrics =
547 : (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
548 : SmuMetrics_t metrics;
549 0 : int ret = 0;
550 :
551 0 : ret = smu_cmn_get_metrics_table(smu, &metrics, true);
552 0 : if (ret)
553 0 : return ret;
554 :
555 0 : smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
556 :
557 0 : gpu_metrics->temperature_gfx = metrics.GfxTemperature;
558 0 : gpu_metrics->temperature_soc = metrics.SocTemperature;
559 0 : memcpy(&gpu_metrics->temperature_core[0],
560 : &metrics.CoreTemperature[0],
561 : sizeof(uint16_t) * 8);
562 0 : gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
563 :
564 0 : gpu_metrics->average_gfx_activity = metrics.GfxActivity;
565 0 : gpu_metrics->average_mm_activity = metrics.UvdActivity;
566 :
567 0 : gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
568 0 : gpu_metrics->average_gfx_power = metrics.Power[0];
569 0 : gpu_metrics->average_soc_power = metrics.Power[1];
570 0 : memcpy(&gpu_metrics->average_core_power[0],
571 : &metrics.CorePower[0],
572 : sizeof(uint16_t) * 8);
573 :
574 0 : gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
575 0 : gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
576 0 : gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
577 0 : gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
578 0 : gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
579 0 : gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
580 :
581 0 : memcpy(&gpu_metrics->current_coreclk[0],
582 : &metrics.CoreFrequency[0],
583 : sizeof(uint16_t) * 8);
584 0 : gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
585 :
586 0 : gpu_metrics->throttle_status = metrics.ThrottlerStatus;
587 :
588 0 : gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
589 :
590 0 : *table = (void *)gpu_metrics;
591 :
592 0 : return sizeof(struct gpu_metrics_v2_1);
593 : }
594 :
595 : /**
596 : * yellow_carp_get_gfxoff_status - get gfxoff status
597 : *
598 : * @smu: smu_context pointer
599 : *
600 : * This function will be used to get gfxoff status
601 : *
602 : * Returns 0=GFXOFF(default).
603 : * Returns 1=Transition out of GFX State.
604 : * Returns 2=Not in GFXOFF.
605 : * Returns 3=Transition into GFXOFF.
606 : */
607 0 : static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
608 : {
609 : uint32_t reg;
610 0 : uint32_t gfxoff_status = 0;
611 0 : struct amdgpu_device *adev = smu->adev;
612 :
613 0 : reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
614 0 : gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
615 0 : >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
616 :
617 0 : return gfxoff_status;
618 : }
619 :
620 0 : static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
621 : {
622 0 : struct smu_table_context *smu_table = &smu->smu_table;
623 :
624 0 : return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
625 : }
626 :
627 0 : static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
628 : long input[], uint32_t size)
629 : {
630 0 : struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
631 0 : int ret = 0;
632 :
633 : /* Only allowed in manual mode */
634 0 : if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
635 : return -EINVAL;
636 :
637 0 : switch (type) {
638 : case PP_OD_EDIT_SCLK_VDDC_TABLE:
639 0 : if (size != 2) {
640 0 : dev_err(smu->adev->dev, "Input parameter number not correct\n");
641 0 : return -EINVAL;
642 : }
643 :
644 0 : if (input[0] == 0) {
645 0 : if (input[1] < smu->gfx_default_hard_min_freq) {
646 0 : dev_warn(smu->adev->dev,
647 : "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
648 : input[1], smu->gfx_default_hard_min_freq);
649 0 : return -EINVAL;
650 : }
651 0 : smu->gfx_actual_hard_min_freq = input[1];
652 0 : } else if (input[0] == 1) {
653 0 : if (input[1] > smu->gfx_default_soft_max_freq) {
654 0 : dev_warn(smu->adev->dev,
655 : "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
656 : input[1], smu->gfx_default_soft_max_freq);
657 0 : return -EINVAL;
658 : }
659 0 : smu->gfx_actual_soft_max_freq = input[1];
660 : } else {
661 : return -EINVAL;
662 : }
663 : break;
664 : case PP_OD_RESTORE_DEFAULT_TABLE:
665 0 : if (size != 0) {
666 0 : dev_err(smu->adev->dev, "Input parameter number not correct\n");
667 0 : return -EINVAL;
668 : } else {
669 0 : smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
670 0 : smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
671 : }
672 0 : break;
673 : case PP_OD_COMMIT_DPM_TABLE:
674 0 : if (size != 0) {
675 0 : dev_err(smu->adev->dev, "Input parameter number not correct\n");
676 0 : return -EINVAL;
677 : } else {
678 0 : if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
679 0 : dev_err(smu->adev->dev,
680 : "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
681 : smu->gfx_actual_hard_min_freq,
682 : smu->gfx_actual_soft_max_freq);
683 0 : return -EINVAL;
684 : }
685 :
686 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
687 : smu->gfx_actual_hard_min_freq, NULL);
688 0 : if (ret) {
689 0 : dev_err(smu->adev->dev, "Set hard min sclk failed!");
690 0 : return ret;
691 : }
692 :
693 0 : ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
694 : smu->gfx_actual_soft_max_freq, NULL);
695 0 : if (ret) {
696 0 : dev_err(smu->adev->dev, "Set soft max sclk failed!");
697 0 : return ret;
698 : }
699 : }
700 : break;
701 : default:
702 : return -ENOSYS;
703 : }
704 :
705 : return ret;
706 : }
707 :
708 0 : static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
709 : enum smu_clk_type clk_type,
710 : uint32_t *value)
711 : {
712 : MetricsMember_t member_type;
713 :
714 0 : switch (clk_type) {
715 : case SMU_SOCCLK:
716 : member_type = METRICS_AVERAGE_SOCCLK;
717 : break;
718 : case SMU_VCLK:
719 0 : member_type = METRICS_AVERAGE_VCLK;
720 0 : break;
721 : case SMU_DCLK:
722 0 : member_type = METRICS_AVERAGE_DCLK;
723 0 : break;
724 : case SMU_MCLK:
725 0 : member_type = METRICS_AVERAGE_UCLK;
726 0 : break;
727 : case SMU_FCLK:
728 0 : return smu_cmn_send_smc_msg_with_param(smu,
729 : SMU_MSG_GetFclkFrequency, 0, value);
730 : case SMU_GFXCLK:
731 : case SMU_SCLK:
732 0 : return smu_cmn_send_smc_msg_with_param(smu,
733 : SMU_MSG_GetGfxclkFrequency, 0, value);
734 : break;
735 : default:
736 : return -EINVAL;
737 : }
738 :
739 0 : return yellow_carp_get_smu_metrics_data(smu, member_type, value);
740 : }
741 :
742 : static int yellow_carp_get_dpm_level_count(struct smu_context *smu,
743 : enum smu_clk_type clk_type,
744 : uint32_t *count)
745 : {
746 0 : DpmClocks_t *clk_table = smu->smu_table.clocks_table;
747 :
748 0 : switch (clk_type) {
749 : case SMU_SOCCLK:
750 0 : *count = clk_table->NumSocClkLevelsEnabled;
751 : break;
752 : case SMU_VCLK:
753 0 : *count = clk_table->VcnClkLevelsEnabled;
754 : break;
755 : case SMU_DCLK:
756 0 : *count = clk_table->VcnClkLevelsEnabled;
757 : break;
758 : case SMU_MCLK:
759 0 : *count = clk_table->NumDfPstatesEnabled;
760 : break;
761 : case SMU_FCLK:
762 0 : *count = clk_table->NumDfPstatesEnabled;
763 : break;
764 : default:
765 : break;
766 : }
767 :
768 : return 0;
769 : }
770 :
771 0 : static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu,
772 : enum smu_clk_type clk_type,
773 : uint32_t dpm_level,
774 : uint32_t *freq)
775 : {
776 0 : DpmClocks_t *clk_table = smu->smu_table.clocks_table;
777 :
778 0 : if (!clk_table || clk_type >= SMU_CLK_COUNT)
779 : return -EINVAL;
780 :
781 0 : switch (clk_type) {
782 : case SMU_SOCCLK:
783 0 : if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
784 : return -EINVAL;
785 0 : *freq = clk_table->SocClocks[dpm_level];
786 : break;
787 : case SMU_VCLK:
788 0 : if (dpm_level >= clk_table->VcnClkLevelsEnabled)
789 : return -EINVAL;
790 0 : *freq = clk_table->VClocks[dpm_level];
791 : break;
792 : case SMU_DCLK:
793 0 : if (dpm_level >= clk_table->VcnClkLevelsEnabled)
794 : return -EINVAL;
795 0 : *freq = clk_table->DClocks[dpm_level];
796 : break;
797 : case SMU_UCLK:
798 : case SMU_MCLK:
799 0 : if (dpm_level >= clk_table->NumDfPstatesEnabled)
800 : return -EINVAL;
801 0 : *freq = clk_table->DfPstateTable[dpm_level].MemClk;
802 : break;
803 : case SMU_FCLK:
804 0 : if (dpm_level >= clk_table->NumDfPstatesEnabled)
805 : return -EINVAL;
806 0 : *freq = clk_table->DfPstateTable[dpm_level].FClk;
807 : break;
808 : default:
809 : return -EINVAL;
810 : }
811 :
812 : return 0;
813 : }
814 :
815 0 : static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
816 : enum smu_clk_type clk_type)
817 : {
818 0 : enum smu_feature_mask feature_id = 0;
819 :
820 0 : switch (clk_type) {
821 : case SMU_MCLK:
822 : case SMU_UCLK:
823 : case SMU_FCLK:
824 : feature_id = SMU_FEATURE_DPM_FCLK_BIT;
825 : break;
826 : case SMU_GFXCLK:
827 : case SMU_SCLK:
828 0 : feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
829 0 : break;
830 : case SMU_SOCCLK:
831 0 : feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
832 0 : break;
833 : case SMU_VCLK:
834 : case SMU_DCLK:
835 0 : feature_id = SMU_FEATURE_VCN_DPM_BIT;
836 0 : break;
837 : default:
838 : return true;
839 : }
840 :
841 0 : return smu_cmn_feature_is_enabled(smu, feature_id);
842 : }
843 :
844 0 : static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
845 : enum smu_clk_type clk_type,
846 : uint32_t *min,
847 : uint32_t *max)
848 : {
849 0 : DpmClocks_t *clk_table = smu->smu_table.clocks_table;
850 : uint32_t clock_limit;
851 : uint32_t max_dpm_level, min_dpm_level;
852 0 : int ret = 0;
853 :
854 0 : if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
855 0 : switch (clk_type) {
856 : case SMU_MCLK:
857 : case SMU_UCLK:
858 0 : clock_limit = smu->smu_table.boot_values.uclk;
859 0 : break;
860 : case SMU_FCLK:
861 0 : clock_limit = smu->smu_table.boot_values.fclk;
862 0 : break;
863 : case SMU_GFXCLK:
864 : case SMU_SCLK:
865 0 : clock_limit = smu->smu_table.boot_values.gfxclk;
866 0 : break;
867 : case SMU_SOCCLK:
868 0 : clock_limit = smu->smu_table.boot_values.socclk;
869 0 : break;
870 : case SMU_VCLK:
871 0 : clock_limit = smu->smu_table.boot_values.vclk;
872 0 : break;
873 : case SMU_DCLK:
874 0 : clock_limit = smu->smu_table.boot_values.dclk;
875 0 : break;
876 : default:
877 : clock_limit = 0;
878 : break;
879 : }
880 :
881 : /* clock in Mhz unit */
882 0 : if (min)
883 0 : *min = clock_limit / 100;
884 0 : if (max)
885 0 : *max = clock_limit / 100;
886 :
887 : return 0;
888 : }
889 :
890 0 : if (max) {
891 0 : switch (clk_type) {
892 : case SMU_GFXCLK:
893 : case SMU_SCLK:
894 0 : *max = clk_table->MaxGfxClk;
895 0 : break;
896 : case SMU_MCLK:
897 : case SMU_UCLK:
898 : case SMU_FCLK:
899 : max_dpm_level = 0;
900 : break;
901 : case SMU_SOCCLK:
902 0 : max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
903 0 : break;
904 : case SMU_VCLK:
905 : case SMU_DCLK:
906 0 : max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
907 0 : break;
908 : default:
909 : ret = -EINVAL;
910 : goto failed;
911 : }
912 :
913 0 : if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
914 0 : ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
915 0 : if (ret)
916 : goto failed;
917 : }
918 : }
919 :
920 0 : if (min) {
921 : switch (clk_type) {
922 : case SMU_GFXCLK:
923 : case SMU_SCLK:
924 0 : *min = clk_table->MinGfxClk;
925 0 : break;
926 : case SMU_MCLK:
927 : case SMU_UCLK:
928 : case SMU_FCLK:
929 0 : min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
930 0 : break;
931 : case SMU_SOCCLK:
932 : min_dpm_level = 0;
933 : break;
934 : case SMU_VCLK:
935 : case SMU_DCLK:
936 : min_dpm_level = 0;
937 : break;
938 : default:
939 : ret = -EINVAL;
940 : goto failed;
941 : }
942 :
943 0 : if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
944 0 : ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
945 : if (ret)
946 : goto failed;
947 : }
948 : }
949 :
950 : failed:
951 : return ret;
952 : }
953 :
954 0 : static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
955 : enum smu_clk_type clk_type,
956 : uint32_t min,
957 : uint32_t max)
958 : {
959 : enum smu_message_type msg_set_min, msg_set_max;
960 0 : int ret = 0;
961 :
962 0 : if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
963 : return -EINVAL;
964 :
965 0 : switch (clk_type) {
966 : case SMU_GFXCLK:
967 : case SMU_SCLK:
968 : msg_set_min = SMU_MSG_SetHardMinGfxClk;
969 : msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
970 : break;
971 : case SMU_FCLK:
972 0 : msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
973 0 : msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
974 0 : break;
975 : case SMU_SOCCLK:
976 0 : msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
977 0 : msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
978 0 : break;
979 : case SMU_VCLK:
980 : case SMU_DCLK:
981 0 : msg_set_min = SMU_MSG_SetHardMinVcn;
982 0 : msg_set_max = SMU_MSG_SetSoftMaxVcn;
983 0 : break;
984 : default:
985 : return -EINVAL;
986 : }
987 :
988 0 : ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
989 0 : if (ret)
990 : goto out;
991 :
992 0 : ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
993 : if (ret)
994 : goto out;
995 :
996 : out:
997 : return ret;
998 : }
999 :
1000 0 : static int yellow_carp_print_clk_levels(struct smu_context *smu,
1001 : enum smu_clk_type clk_type, char *buf)
1002 : {
1003 0 : int i, size = 0, ret = 0;
1004 0 : uint32_t cur_value = 0, value = 0, count = 0;
1005 : uint32_t min, max;
1006 :
1007 0 : smu_cmn_get_sysfs_buf(&buf, &size);
1008 :
1009 0 : switch (clk_type) {
1010 : case SMU_OD_SCLK:
1011 0 : size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1012 0 : size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
1013 0 : (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
1014 0 : size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
1015 0 : (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
1016 0 : break;
1017 : case SMU_OD_RANGE:
1018 0 : size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1019 0 : size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1020 : smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
1021 0 : break;
1022 : case SMU_SOCCLK:
1023 : case SMU_VCLK:
1024 : case SMU_DCLK:
1025 : case SMU_MCLK:
1026 : case SMU_FCLK:
1027 0 : ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1028 0 : if (ret)
1029 : goto print_clk_out;
1030 :
1031 0 : ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);
1032 : if (ret)
1033 : goto print_clk_out;
1034 :
1035 0 : for (i = 0; i < count; i++) {
1036 0 : ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, i, &value);
1037 0 : if (ret)
1038 : goto print_clk_out;
1039 :
1040 0 : size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1041 0 : cur_value == value ? "*" : "");
1042 : }
1043 : break;
1044 : case SMU_GFXCLK:
1045 : case SMU_SCLK:
1046 0 : ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1047 0 : if (ret)
1048 : goto print_clk_out;
1049 0 : min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
1050 0 : max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
1051 0 : if (cur_value == max)
1052 : i = 2;
1053 0 : else if (cur_value == min)
1054 : i = 0;
1055 : else
1056 0 : i = 1;
1057 0 : size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
1058 : i == 0 ? "*" : "");
1059 0 : size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1060 : i == 1 ? cur_value : YELLOW_CARP_UMD_PSTATE_GFXCLK,
1061 : i == 1 ? "*" : "");
1062 0 : size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
1063 : i == 2 ? "*" : "");
1064 0 : break;
1065 : default:
1066 : break;
1067 : }
1068 :
1069 : print_clk_out:
1070 0 : return size;
1071 : }
1072 :
1073 0 : static int yellow_carp_force_clk_levels(struct smu_context *smu,
1074 : enum smu_clk_type clk_type, uint32_t mask)
1075 : {
1076 0 : uint32_t soft_min_level = 0, soft_max_level = 0;
1077 0 : uint32_t min_freq = 0, max_freq = 0;
1078 0 : int ret = 0;
1079 :
1080 0 : soft_min_level = mask ? (ffs(mask) - 1) : 0;
1081 0 : soft_max_level = mask ? (fls(mask) - 1) : 0;
1082 :
1083 : switch (clk_type) {
1084 : case SMU_SOCCLK:
1085 : case SMU_FCLK:
1086 : case SMU_VCLK:
1087 : case SMU_DCLK:
1088 0 : ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1089 0 : if (ret)
1090 : goto force_level_out;
1091 :
1092 0 : ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1093 0 : if (ret)
1094 : goto force_level_out;
1095 :
1096 0 : ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1097 : if (ret)
1098 : goto force_level_out;
1099 : break;
1100 : default:
1101 : ret = -EINVAL;
1102 : break;
1103 : }
1104 :
1105 : force_level_out:
1106 0 : return ret;
1107 : }
1108 :
1109 0 : static int yellow_carp_set_performance_level(struct smu_context *smu,
1110 : enum amd_dpm_forced_level level)
1111 : {
1112 0 : struct amdgpu_device *adev = smu->adev;
1113 0 : uint32_t sclk_min = 0, sclk_max = 0;
1114 0 : uint32_t fclk_min = 0, fclk_max = 0;
1115 0 : uint32_t socclk_min = 0, socclk_max = 0;
1116 0 : int ret = 0;
1117 :
1118 0 : switch (level) {
1119 : case AMD_DPM_FORCED_LEVEL_HIGH:
1120 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1121 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
1122 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
1123 0 : sclk_min = sclk_max;
1124 0 : fclk_min = fclk_max;
1125 0 : socclk_min = socclk_max;
1126 0 : break;
1127 : case AMD_DPM_FORCED_LEVEL_LOW:
1128 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1129 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
1130 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
1131 0 : sclk_max = sclk_min;
1132 0 : fclk_max = fclk_min;
1133 0 : socclk_max = socclk_min;
1134 0 : break;
1135 : case AMD_DPM_FORCED_LEVEL_AUTO:
1136 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1137 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
1138 0 : yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1139 0 : break;
1140 : case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1141 : case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1142 : case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1143 : case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1144 : /* Temporarily do nothing since the optimal clocks haven't been provided yet */
1145 : break;
1146 : case AMD_DPM_FORCED_LEVEL_MANUAL:
1147 : case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1148 : return 0;
1149 : default:
1150 0 : dev_err(adev->dev, "Invalid performance level %d\n", level);
1151 0 : return -EINVAL;
1152 : }
1153 :
1154 0 : if (sclk_min && sclk_max) {
1155 0 : ret = yellow_carp_set_soft_freq_limited_range(smu,
1156 : SMU_SCLK,
1157 : sclk_min,
1158 : sclk_max);
1159 0 : if (ret)
1160 : return ret;
1161 :
1162 0 : smu->gfx_actual_hard_min_freq = sclk_min;
1163 0 : smu->gfx_actual_soft_max_freq = sclk_max;
1164 : }
1165 :
1166 0 : if (fclk_min && fclk_max) {
1167 0 : ret = yellow_carp_set_soft_freq_limited_range(smu,
1168 : SMU_FCLK,
1169 : fclk_min,
1170 : fclk_max);
1171 0 : if (ret)
1172 : return ret;
1173 : }
1174 :
1175 0 : if (socclk_min && socclk_max) {
1176 0 : ret = yellow_carp_set_soft_freq_limited_range(smu,
1177 : SMU_SOCCLK,
1178 : socclk_min,
1179 : socclk_max);
1180 0 : if (ret)
1181 : return ret;
1182 : }
1183 :
1184 : return ret;
1185 : }
1186 :
1187 0 : static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1188 : {
1189 0 : DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1190 :
1191 0 : smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1192 0 : smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1193 0 : smu->gfx_actual_hard_min_freq = 0;
1194 0 : smu->gfx_actual_soft_max_freq = 0;
1195 :
1196 0 : return 0;
1197 : }
1198 :
1199 : static const struct pptable_funcs yellow_carp_ppt_funcs = {
1200 : .check_fw_status = smu_v13_0_check_fw_status,
1201 : .check_fw_version = smu_v13_0_check_fw_version,
1202 : .init_smc_tables = yellow_carp_init_smc_tables,
1203 : .fini_smc_tables = yellow_carp_fini_smc_tables,
1204 : .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1205 : .system_features_control = yellow_carp_system_features_control,
1206 : .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1207 : .send_smc_msg = smu_cmn_send_smc_msg,
1208 : .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable,
1209 : .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable,
1210 : .set_default_dpm_table = yellow_carp_set_default_dpm_tables,
1211 : .read_sensor = yellow_carp_read_sensor,
1212 : .is_dpm_running = yellow_carp_is_dpm_running,
1213 : .set_watermarks_table = yellow_carp_set_watermarks_table,
1214 : .get_gpu_metrics = yellow_carp_get_gpu_metrics,
1215 : .get_enabled_mask = smu_cmn_get_enabled_mask,
1216 : .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1217 : .set_driver_table_location = smu_v13_0_set_driver_table_location,
1218 : .gfx_off_control = smu_v13_0_gfx_off_control,
1219 : .get_gfx_off_status = yellow_carp_get_gfxoff_status,
1220 : .post_init = yellow_carp_post_smu_init,
1221 : .mode2_reset = yellow_carp_mode2_reset,
1222 : .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
1223 : .od_edit_dpm_table = yellow_carp_od_edit_dpm_table,
1224 : .print_clk_levels = yellow_carp_print_clk_levels,
1225 : .force_clk_levels = yellow_carp_force_clk_levels,
1226 : .set_performance_level = yellow_carp_set_performance_level,
1227 : .set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters,
1228 : };
1229 :
1230 0 : void yellow_carp_set_ppt_funcs(struct smu_context *smu)
1231 : {
1232 0 : smu->ppt_funcs = &yellow_carp_ppt_funcs;
1233 0 : smu->message_map = yellow_carp_message_map;
1234 0 : smu->feature_map = yellow_carp_feature_mask_map;
1235 0 : smu->table_map = yellow_carp_table_map;
1236 0 : smu->is_apu = true;
1237 0 : smu_v13_0_set_smu_mailbox_registers(smu);
1238 0 : }
|
