Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * Enable PCIe link L0s/L1 state and Clock Power Management
4 : *
5 : * Copyright (C) 2007 Intel
6 : * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 : * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 : */
9 :
10 : #include <linux/kernel.h>
11 : #include <linux/module.h>
12 : #include <linux/moduleparam.h>
13 : #include <linux/pci.h>
14 : #include <linux/pci_regs.h>
15 : #include <linux/errno.h>
16 : #include <linux/pm.h>
17 : #include <linux/init.h>
18 : #include <linux/slab.h>
19 : #include <linux/jiffies.h>
20 : #include <linux/delay.h>
21 : #include "../pci.h"
22 :
23 : #ifdef MODULE_PARAM_PREFIX
24 : #undef MODULE_PARAM_PREFIX
25 : #endif
26 : #define MODULE_PARAM_PREFIX "pcie_aspm."
27 :
28 : /* Note: those are not register definitions */
29 : #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
30 : #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
31 : #define ASPM_STATE_L1 (4) /* L1 state */
32 : #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33 : #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
34 : #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
35 : #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
36 : #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
37 : #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
38 : #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
39 : ASPM_STATE_L1_2_MASK)
40 : #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
41 : #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
42 : ASPM_STATE_L1SS)
43 :
44 : struct pcie_link_state {
45 : struct pci_dev *pdev; /* Upstream component of the Link */
46 : struct pci_dev *downstream; /* Downstream component, function 0 */
47 : struct pcie_link_state *root; /* pointer to the root port link */
48 : struct pcie_link_state *parent; /* pointer to the parent Link state */
49 : struct list_head sibling; /* node in link_list */
50 :
51 : /* ASPM state */
52 : u32 aspm_support:7; /* Supported ASPM state */
53 : u32 aspm_enabled:7; /* Enabled ASPM state */
54 : u32 aspm_capable:7; /* Capable ASPM state with latency */
55 : u32 aspm_default:7; /* Default ASPM state by BIOS */
56 : u32 aspm_disable:7; /* Disabled ASPM state */
57 :
58 : /* Clock PM state */
59 : u32 clkpm_capable:1; /* Clock PM capable? */
60 : u32 clkpm_enabled:1; /* Current Clock PM state */
61 : u32 clkpm_default:1; /* Default Clock PM state by BIOS */
62 : u32 clkpm_disable:1; /* Clock PM disabled */
63 : };
64 :
65 : static int aspm_disabled, aspm_force;
66 : static bool aspm_support_enabled = true;
67 : static DEFINE_MUTEX(aspm_lock);
68 : static LIST_HEAD(link_list);
69 :
70 : #define POLICY_DEFAULT 0 /* BIOS default setting */
71 : #define POLICY_PERFORMANCE 1 /* high performance */
72 : #define POLICY_POWERSAVE 2 /* high power saving */
73 : #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
74 :
75 : #ifdef CONFIG_PCIEASPM_PERFORMANCE
76 : static int aspm_policy = POLICY_PERFORMANCE;
77 : #elif defined CONFIG_PCIEASPM_POWERSAVE
78 : static int aspm_policy = POLICY_POWERSAVE;
79 : #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
80 : static int aspm_policy = POLICY_POWER_SUPERSAVE;
81 : #else
82 : static int aspm_policy;
83 : #endif
84 :
85 : static const char *policy_str[] = {
86 : [POLICY_DEFAULT] = "default",
87 : [POLICY_PERFORMANCE] = "performance",
88 : [POLICY_POWERSAVE] = "powersave",
89 : [POLICY_POWER_SUPERSAVE] = "powersupersave"
90 : };
91 :
92 : #define LINK_RETRAIN_TIMEOUT HZ
93 :
94 : /*
95 : * The L1 PM substate capability is only implemented in function 0 in a
96 : * multi function device.
97 : */
98 : static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
99 : {
100 : struct pci_dev *child;
101 :
102 0 : list_for_each_entry(child, &linkbus->devices, bus_list)
103 0 : if (PCI_FUNC(child->devfn) == 0)
104 : return child;
105 : return NULL;
106 : }
107 :
108 : static int policy_to_aspm_state(struct pcie_link_state *link)
109 : {
110 0 : switch (aspm_policy) {
111 : case POLICY_PERFORMANCE:
112 : /* Disable ASPM and Clock PM */
113 : return 0;
114 : case POLICY_POWERSAVE:
115 : /* Enable ASPM L0s/L1 */
116 : return (ASPM_STATE_L0S | ASPM_STATE_L1);
117 : case POLICY_POWER_SUPERSAVE:
118 : /* Enable Everything */
119 : return ASPM_STATE_ALL;
120 : case POLICY_DEFAULT:
121 0 : return link->aspm_default;
122 : }
123 : return 0;
124 : }
125 :
126 : static int policy_to_clkpm_state(struct pcie_link_state *link)
127 : {
128 0 : switch (aspm_policy) {
129 : case POLICY_PERFORMANCE:
130 : /* Disable ASPM and Clock PM */
131 : return 0;
132 : case POLICY_POWERSAVE:
133 : case POLICY_POWER_SUPERSAVE:
134 : /* Enable Clock PM */
135 : return 1;
136 : case POLICY_DEFAULT:
137 0 : return link->clkpm_default;
138 : }
139 : return 0;
140 : }
141 :
142 0 : static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
143 : {
144 : struct pci_dev *child;
145 0 : struct pci_bus *linkbus = link->pdev->subordinate;
146 0 : u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
147 :
148 0 : list_for_each_entry(child, &linkbus->devices, bus_list)
149 0 : pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
150 : PCI_EXP_LNKCTL_CLKREQ_EN,
151 : val);
152 0 : link->clkpm_enabled = !!enable;
153 0 : }
154 :
155 : static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
156 : {
157 : /*
158 : * Don't enable Clock PM if the link is not Clock PM capable
159 : * or Clock PM is disabled
160 : */
161 0 : if (!link->clkpm_capable || link->clkpm_disable)
162 0 : enable = 0;
163 : /* Need nothing if the specified equals to current state */
164 0 : if (link->clkpm_enabled == enable)
165 : return;
166 0 : pcie_set_clkpm_nocheck(link, enable);
167 : }
168 :
169 0 : static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
170 : {
171 0 : int capable = 1, enabled = 1;
172 : u32 reg32;
173 : u16 reg16;
174 : struct pci_dev *child;
175 0 : struct pci_bus *linkbus = link->pdev->subordinate;
176 :
177 : /* All functions should have the same cap and state, take the worst */
178 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
179 0 : pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
180 0 : if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
181 : capable = 0;
182 : enabled = 0;
183 : break;
184 : }
185 0 : pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
186 0 : if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
187 0 : enabled = 0;
188 : }
189 0 : link->clkpm_enabled = enabled;
190 0 : link->clkpm_default = enabled;
191 0 : link->clkpm_capable = capable;
192 0 : link->clkpm_disable = blacklist ? 1 : 0;
193 0 : }
194 :
195 0 : static bool pcie_retrain_link(struct pcie_link_state *link)
196 : {
197 0 : struct pci_dev *parent = link->pdev;
198 : unsigned long end_jiffies;
199 : u16 reg16;
200 :
201 0 : pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
202 0 : reg16 |= PCI_EXP_LNKCTL_RL;
203 0 : pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
204 0 : if (parent->clear_retrain_link) {
205 : /*
206 : * Due to an erratum in some devices the Retrain Link bit
207 : * needs to be cleared again manually to allow the link
208 : * training to succeed.
209 : */
210 0 : reg16 &= ~PCI_EXP_LNKCTL_RL;
211 0 : pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
212 : }
213 :
214 : /* Wait for link training end. Break out after waiting for timeout */
215 0 : end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
216 : do {
217 0 : pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
218 0 : if (!(reg16 & PCI_EXP_LNKSTA_LT))
219 : break;
220 0 : msleep(1);
221 0 : } while (time_before(jiffies, end_jiffies));
222 0 : return !(reg16 & PCI_EXP_LNKSTA_LT);
223 : }
224 :
225 : /*
226 : * pcie_aspm_configure_common_clock: check if the 2 ends of a link
227 : * could use common clock. If they are, configure them to use the
228 : * common clock. That will reduce the ASPM state exit latency.
229 : */
230 0 : static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
231 : {
232 0 : int same_clock = 1;
233 : u16 reg16, parent_reg, child_reg[8];
234 0 : struct pci_dev *child, *parent = link->pdev;
235 0 : struct pci_bus *linkbus = parent->subordinate;
236 : /*
237 : * All functions of a slot should have the same Slot Clock
238 : * Configuration, so just check one function
239 : */
240 0 : child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
241 0 : BUG_ON(!pci_is_pcie(child));
242 :
243 : /* Check downstream component if bit Slot Clock Configuration is 1 */
244 0 : pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
245 0 : if (!(reg16 & PCI_EXP_LNKSTA_SLC))
246 0 : same_clock = 0;
247 :
248 : /* Check upstream component if bit Slot Clock Configuration is 1 */
249 0 : pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
250 0 : if (!(reg16 & PCI_EXP_LNKSTA_SLC))
251 0 : same_clock = 0;
252 :
253 : /* Port might be already in common clock mode */
254 0 : pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
255 0 : if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
256 0 : bool consistent = true;
257 :
258 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
259 0 : pcie_capability_read_word(child, PCI_EXP_LNKCTL,
260 : ®16);
261 0 : if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
262 : consistent = false;
263 : break;
264 : }
265 : }
266 0 : if (consistent)
267 0 : return;
268 0 : pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
269 : }
270 :
271 : /* Configure downstream component, all functions */
272 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
273 0 : pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
274 0 : child_reg[PCI_FUNC(child->devfn)] = reg16;
275 0 : if (same_clock)
276 0 : reg16 |= PCI_EXP_LNKCTL_CCC;
277 : else
278 0 : reg16 &= ~PCI_EXP_LNKCTL_CCC;
279 0 : pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
280 : }
281 :
282 : /* Configure upstream component */
283 0 : pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
284 0 : parent_reg = reg16;
285 0 : if (same_clock)
286 0 : reg16 |= PCI_EXP_LNKCTL_CCC;
287 : else
288 0 : reg16 &= ~PCI_EXP_LNKCTL_CCC;
289 0 : pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
290 :
291 0 : if (pcie_retrain_link(link))
292 : return;
293 :
294 : /* Training failed. Restore common clock configurations */
295 0 : pci_err(parent, "ASPM: Could not configure common clock\n");
296 0 : list_for_each_entry(child, &linkbus->devices, bus_list)
297 0 : pcie_capability_write_word(child, PCI_EXP_LNKCTL,
298 0 : child_reg[PCI_FUNC(child->devfn)]);
299 0 : pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
300 : }
301 :
302 : /* Convert L0s latency encoding to ns */
303 : static u32 calc_l0s_latency(u32 lnkcap)
304 : {
305 0 : u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
306 :
307 0 : if (encoding == 0x7)
308 : return (5 * 1000); /* > 4us */
309 0 : return (64 << encoding);
310 : }
311 :
312 : /* Convert L0s acceptable latency encoding to ns */
313 : static u32 calc_l0s_acceptable(u32 encoding)
314 : {
315 0 : if (encoding == 0x7)
316 : return -1U;
317 0 : return (64 << encoding);
318 : }
319 :
320 : /* Convert L1 latency encoding to ns */
321 : static u32 calc_l1_latency(u32 lnkcap)
322 : {
323 0 : u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
324 :
325 0 : if (encoding == 0x7)
326 : return (65 * 1000); /* > 64us */
327 0 : return (1000 << encoding);
328 : }
329 :
330 : /* Convert L1 acceptable latency encoding to ns */
331 : static u32 calc_l1_acceptable(u32 encoding)
332 : {
333 0 : if (encoding == 0x7)
334 : return -1U;
335 0 : return (1000 << encoding);
336 : }
337 :
338 : /* Convert L1SS T_pwr encoding to usec */
339 0 : static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
340 : {
341 0 : switch (scale) {
342 : case 0:
343 0 : return val * 2;
344 : case 1:
345 0 : return val * 10;
346 : case 2:
347 0 : return val * 100;
348 : }
349 0 : pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
350 0 : return 0;
351 : }
352 :
353 0 : static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
354 : {
355 0 : u32 threshold_ns = threshold_us * 1000;
356 :
357 : /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
358 0 : if (threshold_ns < 32) {
359 0 : *scale = 0;
360 0 : *value = threshold_ns;
361 0 : } else if (threshold_ns < 1024) {
362 0 : *scale = 1;
363 0 : *value = threshold_ns >> 5;
364 0 : } else if (threshold_ns < 32768) {
365 0 : *scale = 2;
366 0 : *value = threshold_ns >> 10;
367 0 : } else if (threshold_ns < 1048576) {
368 0 : *scale = 3;
369 0 : *value = threshold_ns >> 15;
370 0 : } else if (threshold_ns < 33554432) {
371 0 : *scale = 4;
372 0 : *value = threshold_ns >> 20;
373 : } else {
374 0 : *scale = 5;
375 0 : *value = threshold_ns >> 25;
376 : }
377 0 : }
378 :
379 0 : static void pcie_aspm_check_latency(struct pci_dev *endpoint)
380 : {
381 : u32 latency, encoding, lnkcap_up, lnkcap_dw;
382 0 : u32 l1_switch_latency = 0, latency_up_l0s;
383 : u32 latency_up_l1, latency_dw_l0s, latency_dw_l1;
384 : u32 acceptable_l0s, acceptable_l1;
385 : struct pcie_link_state *link;
386 :
387 : /* Device not in D0 doesn't need latency check */
388 0 : if ((endpoint->current_state != PCI_D0) &&
389 : (endpoint->current_state != PCI_UNKNOWN))
390 0 : return;
391 :
392 0 : link = endpoint->bus->self->link_state;
393 :
394 : /* Calculate endpoint L0s acceptable latency */
395 0 : encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L0S) >> 6;
396 0 : acceptable_l0s = calc_l0s_acceptable(encoding);
397 :
398 : /* Calculate endpoint L1 acceptable latency */
399 0 : encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L1) >> 9;
400 0 : acceptable_l1 = calc_l1_acceptable(encoding);
401 :
402 0 : while (link) {
403 0 : struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
404 :
405 : /* Read direction exit latencies */
406 0 : pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP,
407 : &lnkcap_up);
408 0 : pcie_capability_read_dword(dev, PCI_EXP_LNKCAP,
409 : &lnkcap_dw);
410 0 : latency_up_l0s = calc_l0s_latency(lnkcap_up);
411 0 : latency_up_l1 = calc_l1_latency(lnkcap_up);
412 0 : latency_dw_l0s = calc_l0s_latency(lnkcap_dw);
413 0 : latency_dw_l1 = calc_l1_latency(lnkcap_dw);
414 :
415 : /* Check upstream direction L0s latency */
416 0 : if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
417 : (latency_up_l0s > acceptable_l0s))
418 0 : link->aspm_capable &= ~ASPM_STATE_L0S_UP;
419 :
420 : /* Check downstream direction L0s latency */
421 0 : if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
422 : (latency_dw_l0s > acceptable_l0s))
423 0 : link->aspm_capable &= ~ASPM_STATE_L0S_DW;
424 : /*
425 : * Check L1 latency.
426 : * Every switch on the path to root complex need 1
427 : * more microsecond for L1. Spec doesn't mention L0s.
428 : *
429 : * The exit latencies for L1 substates are not advertised
430 : * by a device. Since the spec also doesn't mention a way
431 : * to determine max latencies introduced by enabling L1
432 : * substates on the components, it is not clear how to do
433 : * a L1 substate exit latency check. We assume that the
434 : * L1 exit latencies advertised by a device include L1
435 : * substate latencies (and hence do not do any check).
436 : */
437 0 : latency = max_t(u32, latency_up_l1, latency_dw_l1);
438 0 : if ((link->aspm_capable & ASPM_STATE_L1) &&
439 0 : (latency + l1_switch_latency > acceptable_l1))
440 0 : link->aspm_capable &= ~ASPM_STATE_L1;
441 0 : l1_switch_latency += 1000;
442 :
443 0 : link = link->parent;
444 : }
445 : }
446 :
447 0 : static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
448 : u32 clear, u32 set)
449 : {
450 : u32 val;
451 :
452 0 : pci_read_config_dword(pdev, pos, &val);
453 0 : val &= ~clear;
454 0 : val |= set;
455 0 : pci_write_config_dword(pdev, pos, val);
456 0 : }
457 :
458 : /* Calculate L1.2 PM substate timing parameters */
459 0 : static void aspm_calc_l1ss_info(struct pcie_link_state *link,
460 : u32 parent_l1ss_cap, u32 child_l1ss_cap)
461 : {
462 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
463 : u32 val1, val2, scale1, scale2;
464 : u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
465 0 : u32 ctl1 = 0, ctl2 = 0;
466 : u32 pctl1, pctl2, cctl1, cctl2;
467 : u32 pl1_2_enables, cl1_2_enables;
468 :
469 0 : if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
470 0 : return;
471 :
472 : /* Choose the greater of the two Port Common_Mode_Restore_Times */
473 0 : val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
474 0 : val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
475 0 : t_common_mode = max(val1, val2);
476 :
477 : /* Choose the greater of the two Port T_POWER_ON times */
478 0 : val1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
479 0 : scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
480 0 : val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
481 0 : scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
482 :
483 0 : if (calc_l1ss_pwron(parent, scale1, val1) >
484 0 : calc_l1ss_pwron(child, scale2, val2)) {
485 0 : ctl2 |= scale1 | (val1 << 3);
486 0 : t_power_on = calc_l1ss_pwron(parent, scale1, val1);
487 : } else {
488 0 : ctl2 |= scale2 | (val2 << 3);
489 0 : t_power_on = calc_l1ss_pwron(child, scale2, val2);
490 : }
491 :
492 : /*
493 : * Set LTR_L1.2_THRESHOLD to the time required to transition the
494 : * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
495 : * downstream devices report (via LTR) that they can tolerate at
496 : * least that much latency.
497 : *
498 : * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
499 : * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
500 : * least 4us.
501 : */
502 0 : l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
503 0 : encode_l12_threshold(l1_2_threshold, &scale, &value);
504 0 : ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
505 :
506 : /* Some broken devices only support dword access to L1 SS */
507 0 : pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
508 0 : pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
509 0 : pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
510 0 : pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
511 :
512 0 : if (ctl1 == pctl1 && ctl1 == cctl1 &&
513 0 : ctl2 == pctl2 && ctl2 == cctl2)
514 : return;
515 :
516 : /* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
517 0 : pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
518 0 : cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
519 :
520 0 : if (pl1_2_enables || cl1_2_enables) {
521 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
522 : PCI_L1SS_CTL1_L1_2_MASK, 0);
523 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
524 : PCI_L1SS_CTL1_L1_2_MASK, 0);
525 : }
526 :
527 : /* Program T_POWER_ON times in both ports */
528 0 : pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
529 0 : pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
530 :
531 : /* Program Common_Mode_Restore_Time in upstream device */
532 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
533 : PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
534 :
535 : /* Program LTR_L1.2_THRESHOLD time in both ports */
536 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
537 : PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
538 : PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
539 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
540 : PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
541 : PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
542 :
543 0 : if (pl1_2_enables || cl1_2_enables) {
544 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
545 : pl1_2_enables);
546 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
547 : cl1_2_enables);
548 : }
549 : }
550 :
551 0 : static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
552 : {
553 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
554 : u32 parent_lnkcap, child_lnkcap;
555 : u16 parent_lnkctl, child_lnkctl;
556 : u32 parent_l1ss_cap, child_l1ss_cap;
557 0 : u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
558 0 : struct pci_bus *linkbus = parent->subordinate;
559 :
560 0 : if (blacklist) {
561 : /* Set enabled/disable so that we will disable ASPM later */
562 0 : link->aspm_enabled = ASPM_STATE_ALL;
563 0 : link->aspm_disable = ASPM_STATE_ALL;
564 0 : return;
565 : }
566 :
567 : /*
568 : * If ASPM not supported, don't mess with the clocks and link,
569 : * bail out now.
570 : */
571 0 : pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
572 0 : pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
573 0 : if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
574 : return;
575 :
576 : /* Configure common clock before checking latencies */
577 0 : pcie_aspm_configure_common_clock(link);
578 :
579 : /*
580 : * Re-read upstream/downstream components' register state after
581 : * clock configuration. L0s & L1 exit latencies in the otherwise
582 : * read-only Link Capabilities may change depending on common clock
583 : * configuration (PCIe r5.0, sec 7.5.3.6).
584 : */
585 0 : pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
586 0 : pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
587 0 : pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
588 0 : pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
589 :
590 : /*
591 : * Setup L0s state
592 : *
593 : * Note that we must not enable L0s in either direction on a
594 : * given link unless components on both sides of the link each
595 : * support L0s.
596 : */
597 0 : if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
598 0 : link->aspm_support |= ASPM_STATE_L0S;
599 :
600 0 : if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
601 0 : link->aspm_enabled |= ASPM_STATE_L0S_UP;
602 0 : if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
603 0 : link->aspm_enabled |= ASPM_STATE_L0S_DW;
604 :
605 : /* Setup L1 state */
606 0 : if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
607 0 : link->aspm_support |= ASPM_STATE_L1;
608 :
609 0 : if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
610 0 : link->aspm_enabled |= ASPM_STATE_L1;
611 :
612 : /* Setup L1 substate */
613 0 : pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
614 : &parent_l1ss_cap);
615 0 : pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
616 : &child_l1ss_cap);
617 :
618 0 : if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
619 0 : parent_l1ss_cap = 0;
620 0 : if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
621 0 : child_l1ss_cap = 0;
622 :
623 : /*
624 : * If we don't have LTR for the entire path from the Root Complex
625 : * to this device, we can't use ASPM L1.2 because it relies on the
626 : * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
627 : */
628 0 : if (!child->ltr_path)
629 0 : child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
630 :
631 0 : if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
632 0 : link->aspm_support |= ASPM_STATE_L1_1;
633 0 : if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
634 0 : link->aspm_support |= ASPM_STATE_L1_2;
635 0 : if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
636 0 : link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
637 0 : if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
638 0 : link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
639 :
640 0 : if (parent_l1ss_cap)
641 0 : pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
642 : &parent_l1ss_ctl1);
643 0 : if (child_l1ss_cap)
644 0 : pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
645 : &child_l1ss_ctl1);
646 :
647 0 : if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
648 0 : link->aspm_enabled |= ASPM_STATE_L1_1;
649 0 : if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
650 0 : link->aspm_enabled |= ASPM_STATE_L1_2;
651 0 : if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
652 0 : link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
653 0 : if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
654 0 : link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
655 :
656 0 : if (link->aspm_support & ASPM_STATE_L1SS)
657 0 : aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);
658 :
659 : /* Save default state */
660 0 : link->aspm_default = link->aspm_enabled;
661 :
662 : /* Setup initial capable state. Will be updated later */
663 0 : link->aspm_capable = link->aspm_support;
664 :
665 : /* Get and check endpoint acceptable latencies */
666 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
667 0 : if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
668 0 : pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
669 0 : continue;
670 :
671 0 : pcie_aspm_check_latency(child);
672 : }
673 : }
674 :
675 : /* Configure the ASPM L1 substates */
676 0 : static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
677 : {
678 : u32 val, enable_req;
679 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
680 :
681 0 : enable_req = (link->aspm_enabled ^ state) & state;
682 :
683 : /*
684 : * Here are the rules specified in the PCIe spec for enabling L1SS:
685 : * - When enabling L1.x, enable bit at parent first, then at child
686 : * - When disabling L1.x, disable bit at child first, then at parent
687 : * - When enabling ASPM L1.x, need to disable L1
688 : * (at child followed by parent).
689 : * - The ASPM/PCIPM L1.2 must be disabled while programming timing
690 : * parameters
691 : *
692 : * To keep it simple, disable all L1SS bits first, and later enable
693 : * what is needed.
694 : */
695 :
696 : /* Disable all L1 substates */
697 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
698 : PCI_L1SS_CTL1_L1SS_MASK, 0);
699 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
700 : PCI_L1SS_CTL1_L1SS_MASK, 0);
701 : /*
702 : * If needed, disable L1, and it gets enabled later
703 : * in pcie_config_aspm_link().
704 : */
705 0 : if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
706 0 : pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
707 : PCI_EXP_LNKCTL_ASPM_L1, 0);
708 0 : pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
709 : PCI_EXP_LNKCTL_ASPM_L1, 0);
710 : }
711 :
712 0 : val = 0;
713 0 : if (state & ASPM_STATE_L1_1)
714 0 : val |= PCI_L1SS_CTL1_ASPM_L1_1;
715 0 : if (state & ASPM_STATE_L1_2)
716 0 : val |= PCI_L1SS_CTL1_ASPM_L1_2;
717 0 : if (state & ASPM_STATE_L1_1_PCIPM)
718 0 : val |= PCI_L1SS_CTL1_PCIPM_L1_1;
719 0 : if (state & ASPM_STATE_L1_2_PCIPM)
720 0 : val |= PCI_L1SS_CTL1_PCIPM_L1_2;
721 :
722 : /* Enable what we need to enable */
723 0 : pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
724 : PCI_L1SS_CTL1_L1SS_MASK, val);
725 0 : pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
726 : PCI_L1SS_CTL1_L1SS_MASK, val);
727 0 : }
728 :
729 : static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
730 : {
731 0 : pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
732 : PCI_EXP_LNKCTL_ASPMC, val);
733 : }
734 :
735 0 : static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
736 : {
737 0 : u32 upstream = 0, dwstream = 0;
738 0 : struct pci_dev *child = link->downstream, *parent = link->pdev;
739 0 : struct pci_bus *linkbus = parent->subordinate;
740 :
741 : /* Enable only the states that were not explicitly disabled */
742 0 : state &= (link->aspm_capable & ~link->aspm_disable);
743 :
744 : /* Can't enable any substates if L1 is not enabled */
745 0 : if (!(state & ASPM_STATE_L1))
746 0 : state &= ~ASPM_STATE_L1SS;
747 :
748 : /* Spec says both ports must be in D0 before enabling PCI PM substates*/
749 0 : if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
750 0 : state &= ~ASPM_STATE_L1_SS_PCIPM;
751 0 : state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
752 : }
753 :
754 : /* Nothing to do if the link is already in the requested state */
755 0 : if (link->aspm_enabled == state)
756 : return;
757 : /* Convert ASPM state to upstream/downstream ASPM register state */
758 0 : if (state & ASPM_STATE_L0S_UP)
759 0 : dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
760 0 : if (state & ASPM_STATE_L0S_DW)
761 0 : upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
762 0 : if (state & ASPM_STATE_L1) {
763 0 : upstream |= PCI_EXP_LNKCTL_ASPM_L1;
764 0 : dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
765 : }
766 :
767 0 : if (link->aspm_capable & ASPM_STATE_L1SS)
768 0 : pcie_config_aspm_l1ss(link, state);
769 :
770 : /*
771 : * Spec 2.0 suggests all functions should be configured the
772 : * same setting for ASPM. Enabling ASPM L1 should be done in
773 : * upstream component first and then downstream, and vice
774 : * versa for disabling ASPM L1. Spec doesn't mention L0S.
775 : */
776 0 : if (state & ASPM_STATE_L1)
777 : pcie_config_aspm_dev(parent, upstream);
778 0 : list_for_each_entry(child, &linkbus->devices, bus_list)
779 0 : pcie_config_aspm_dev(child, dwstream);
780 0 : if (!(state & ASPM_STATE_L1))
781 : pcie_config_aspm_dev(parent, upstream);
782 :
783 0 : link->aspm_enabled = state;
784 : }
785 :
786 0 : static void pcie_config_aspm_path(struct pcie_link_state *link)
787 : {
788 0 : while (link) {
789 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
790 0 : link = link->parent;
791 : }
792 0 : }
793 :
794 : static void free_link_state(struct pcie_link_state *link)
795 : {
796 0 : link->pdev->link_state = NULL;
797 0 : kfree(link);
798 : }
799 :
800 0 : static int pcie_aspm_sanity_check(struct pci_dev *pdev)
801 : {
802 : struct pci_dev *child;
803 : u32 reg32;
804 :
805 : /*
806 : * Some functions in a slot might not all be PCIe functions,
807 : * very strange. Disable ASPM for the whole slot
808 : */
809 0 : list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
810 0 : if (!pci_is_pcie(child))
811 : return -EINVAL;
812 :
813 : /*
814 : * If ASPM is disabled then we're not going to change
815 : * the BIOS state. It's safe to continue even if it's a
816 : * pre-1.1 device
817 : */
818 :
819 0 : if (aspm_disabled)
820 0 : continue;
821 :
822 : /*
823 : * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
824 : * RBER bit to determine if a function is 1.1 version device
825 : */
826 0 : pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
827 0 : if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
828 0 : pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
829 : return -EINVAL;
830 : }
831 : }
832 : return 0;
833 : }
834 :
835 0 : static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
836 : {
837 : struct pcie_link_state *link;
838 :
839 0 : link = kzalloc(sizeof(*link), GFP_KERNEL);
840 0 : if (!link)
841 : return NULL;
842 :
843 0 : INIT_LIST_HEAD(&link->sibling);
844 0 : link->pdev = pdev;
845 0 : link->downstream = pci_function_0(pdev->subordinate);
846 :
847 : /*
848 : * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
849 : * hierarchies. Note that some PCIe host implementations omit
850 : * the root ports entirely, in which case a downstream port on
851 : * a switch may become the root of the link state chain for all
852 : * its subordinate endpoints.
853 : */
854 0 : if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
855 0 : pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
856 0 : !pdev->bus->parent->self) {
857 0 : link->root = link;
858 : } else {
859 : struct pcie_link_state *parent;
860 :
861 0 : parent = pdev->bus->parent->self->link_state;
862 0 : if (!parent) {
863 0 : kfree(link);
864 0 : return NULL;
865 : }
866 :
867 0 : link->parent = parent;
868 0 : link->root = link->parent->root;
869 : }
870 :
871 0 : list_add(&link->sibling, &link_list);
872 0 : pdev->link_state = link;
873 0 : return link;
874 : }
875 :
876 : static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)
877 : {
878 : struct pci_dev *child;
879 :
880 0 : list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
881 0 : sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group);
882 : }
883 :
884 : /*
885 : * pcie_aspm_init_link_state: Initiate PCI express link state.
886 : * It is called after the pcie and its children devices are scanned.
887 : * @pdev: the root port or switch downstream port
888 : */
889 0 : void pcie_aspm_init_link_state(struct pci_dev *pdev)
890 : {
891 : struct pcie_link_state *link;
892 0 : int blacklist = !!pcie_aspm_sanity_check(pdev);
893 :
894 0 : if (!aspm_support_enabled)
895 : return;
896 :
897 0 : if (pdev->link_state)
898 : return;
899 :
900 : /*
901 : * We allocate pcie_link_state for the component on the upstream
902 : * end of a Link, so there's nothing to do unless this device is
903 : * downstream port.
904 : */
905 0 : if (!pcie_downstream_port(pdev))
906 : return;
907 :
908 : /* VIA has a strange chipset, root port is under a bridge */
909 0 : if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
910 0 : pdev->bus->self)
911 : return;
912 :
913 0 : down_read(&pci_bus_sem);
914 0 : if (list_empty(&pdev->subordinate->devices))
915 : goto out;
916 :
917 0 : mutex_lock(&aspm_lock);
918 0 : link = alloc_pcie_link_state(pdev);
919 0 : if (!link)
920 : goto unlock;
921 : /*
922 : * Setup initial ASPM state. Note that we need to configure
923 : * upstream links also because capable state of them can be
924 : * update through pcie_aspm_cap_init().
925 : */
926 0 : pcie_aspm_cap_init(link, blacklist);
927 :
928 : /* Setup initial Clock PM state */
929 0 : pcie_clkpm_cap_init(link, blacklist);
930 :
931 : /*
932 : * At this stage drivers haven't had an opportunity to change the
933 : * link policy setting. Enabling ASPM on broken hardware can cripple
934 : * it even before the driver has had a chance to disable ASPM, so
935 : * default to a safe level right now. If we're enabling ASPM beyond
936 : * the BIOS's expectation, we'll do so once pci_enable_device() is
937 : * called.
938 : */
939 0 : if (aspm_policy != POLICY_POWERSAVE &&
940 : aspm_policy != POLICY_POWER_SUPERSAVE) {
941 0 : pcie_config_aspm_path(link);
942 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
943 : }
944 :
945 0 : pcie_aspm_update_sysfs_visibility(pdev);
946 :
947 : unlock:
948 0 : mutex_unlock(&aspm_lock);
949 : out:
950 0 : up_read(&pci_bus_sem);
951 : }
952 :
953 : /* Recheck latencies and update aspm_capable for links under the root */
954 0 : static void pcie_update_aspm_capable(struct pcie_link_state *root)
955 : {
956 : struct pcie_link_state *link;
957 0 : BUG_ON(root->parent);
958 0 : list_for_each_entry(link, &link_list, sibling) {
959 0 : if (link->root != root)
960 0 : continue;
961 0 : link->aspm_capable = link->aspm_support;
962 : }
963 0 : list_for_each_entry(link, &link_list, sibling) {
964 : struct pci_dev *child;
965 0 : struct pci_bus *linkbus = link->pdev->subordinate;
966 0 : if (link->root != root)
967 0 : continue;
968 0 : list_for_each_entry(child, &linkbus->devices, bus_list) {
969 0 : if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
970 0 : (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
971 0 : continue;
972 0 : pcie_aspm_check_latency(child);
973 : }
974 : }
975 0 : }
976 :
977 : /* @pdev: the endpoint device */
978 0 : void pcie_aspm_exit_link_state(struct pci_dev *pdev)
979 : {
980 0 : struct pci_dev *parent = pdev->bus->self;
981 : struct pcie_link_state *link, *root, *parent_link;
982 :
983 0 : if (!parent || !parent->link_state)
984 : return;
985 :
986 0 : down_read(&pci_bus_sem);
987 0 : mutex_lock(&aspm_lock);
988 : /*
989 : * All PCIe functions are in one slot, remove one function will remove
990 : * the whole slot, so just wait until we are the last function left.
991 : */
992 0 : if (!list_empty(&parent->subordinate->devices))
993 : goto out;
994 :
995 0 : link = parent->link_state;
996 0 : root = link->root;
997 0 : parent_link = link->parent;
998 :
999 : /* All functions are removed, so just disable ASPM for the link */
1000 0 : pcie_config_aspm_link(link, 0);
1001 0 : list_del(&link->sibling);
1002 : /* Clock PM is for endpoint device */
1003 0 : free_link_state(link);
1004 :
1005 : /* Recheck latencies and configure upstream links */
1006 0 : if (parent_link) {
1007 0 : pcie_update_aspm_capable(root);
1008 0 : pcie_config_aspm_path(parent_link);
1009 : }
1010 : out:
1011 0 : mutex_unlock(&aspm_lock);
1012 0 : up_read(&pci_bus_sem);
1013 : }
1014 :
1015 : /* @pdev: the root port or switch downstream port */
1016 0 : void pcie_aspm_pm_state_change(struct pci_dev *pdev)
1017 : {
1018 0 : struct pcie_link_state *link = pdev->link_state;
1019 :
1020 0 : if (aspm_disabled || !link)
1021 : return;
1022 : /*
1023 : * Devices changed PM state, we should recheck if latency
1024 : * meets all functions' requirement
1025 : */
1026 0 : down_read(&pci_bus_sem);
1027 0 : mutex_lock(&aspm_lock);
1028 0 : pcie_update_aspm_capable(link->root);
1029 0 : pcie_config_aspm_path(link);
1030 0 : mutex_unlock(&aspm_lock);
1031 0 : up_read(&pci_bus_sem);
1032 : }
1033 :
1034 0 : void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1035 : {
1036 0 : struct pcie_link_state *link = pdev->link_state;
1037 :
1038 0 : if (aspm_disabled || !link)
1039 : return;
1040 :
1041 0 : if (aspm_policy != POLICY_POWERSAVE &&
1042 : aspm_policy != POLICY_POWER_SUPERSAVE)
1043 : return;
1044 :
1045 0 : down_read(&pci_bus_sem);
1046 0 : mutex_lock(&aspm_lock);
1047 0 : pcie_config_aspm_path(link);
1048 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1049 0 : mutex_unlock(&aspm_lock);
1050 0 : up_read(&pci_bus_sem);
1051 : }
1052 :
1053 : static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
1054 : {
1055 : struct pci_dev *bridge;
1056 :
1057 0 : if (!pci_is_pcie(pdev))
1058 : return NULL;
1059 :
1060 0 : bridge = pci_upstream_bridge(pdev);
1061 0 : if (!bridge || !pci_is_pcie(bridge))
1062 : return NULL;
1063 :
1064 0 : return bridge->link_state;
1065 : }
1066 :
1067 0 : static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1068 : {
1069 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1070 :
1071 0 : if (!link)
1072 : return -EINVAL;
1073 : /*
1074 : * A driver requested that ASPM be disabled on this device, but
1075 : * if we don't have permission to manage ASPM (e.g., on ACPI
1076 : * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1077 : * the _OSC method), we can't honor that request. Windows has
1078 : * a similar mechanism using "PciASPMOptOut", which is also
1079 : * ignored in this situation.
1080 : */
1081 0 : if (aspm_disabled) {
1082 0 : pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1083 0 : return -EPERM;
1084 : }
1085 :
1086 0 : if (sem)
1087 0 : down_read(&pci_bus_sem);
1088 0 : mutex_lock(&aspm_lock);
1089 0 : if (state & PCIE_LINK_STATE_L0S)
1090 0 : link->aspm_disable |= ASPM_STATE_L0S;
1091 0 : if (state & PCIE_LINK_STATE_L1)
1092 : /* L1 PM substates require L1 */
1093 0 : link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
1094 0 : if (state & PCIE_LINK_STATE_L1_1)
1095 0 : link->aspm_disable |= ASPM_STATE_L1_1;
1096 0 : if (state & PCIE_LINK_STATE_L1_2)
1097 0 : link->aspm_disable |= ASPM_STATE_L1_2;
1098 0 : if (state & PCIE_LINK_STATE_L1_1_PCIPM)
1099 0 : link->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
1100 0 : if (state & PCIE_LINK_STATE_L1_2_PCIPM)
1101 0 : link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
1102 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
1103 :
1104 0 : if (state & PCIE_LINK_STATE_CLKPM)
1105 0 : link->clkpm_disable = 1;
1106 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1107 0 : mutex_unlock(&aspm_lock);
1108 0 : if (sem)
1109 0 : up_read(&pci_bus_sem);
1110 :
1111 : return 0;
1112 : }
1113 :
1114 0 : int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1115 : {
1116 0 : return __pci_disable_link_state(pdev, state, false);
1117 : }
1118 : EXPORT_SYMBOL(pci_disable_link_state_locked);
1119 :
1120 : /**
1121 : * pci_disable_link_state - Disable device's link state, so the link will
1122 : * never enter specific states. Note that if the BIOS didn't grant ASPM
1123 : * control to the OS, this does nothing because we can't touch the LNKCTL
1124 : * register. Returns 0 or a negative errno.
1125 : *
1126 : * @pdev: PCI device
1127 : * @state: ASPM link state to disable
1128 : */
1129 0 : int pci_disable_link_state(struct pci_dev *pdev, int state)
1130 : {
1131 0 : return __pci_disable_link_state(pdev, state, true);
1132 : }
1133 : EXPORT_SYMBOL(pci_disable_link_state);
1134 :
1135 0 : static int pcie_aspm_set_policy(const char *val,
1136 : const struct kernel_param *kp)
1137 : {
1138 : int i;
1139 : struct pcie_link_state *link;
1140 :
1141 0 : if (aspm_disabled)
1142 : return -EPERM;
1143 0 : i = sysfs_match_string(policy_str, val);
1144 0 : if (i < 0)
1145 : return i;
1146 0 : if (i == aspm_policy)
1147 : return 0;
1148 :
1149 0 : down_read(&pci_bus_sem);
1150 0 : mutex_lock(&aspm_lock);
1151 0 : aspm_policy = i;
1152 0 : list_for_each_entry(link, &link_list, sibling) {
1153 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
1154 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1155 : }
1156 0 : mutex_unlock(&aspm_lock);
1157 0 : up_read(&pci_bus_sem);
1158 0 : return 0;
1159 : }
1160 :
1161 0 : static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1162 : {
1163 0 : int i, cnt = 0;
1164 0 : for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1165 0 : if (i == aspm_policy)
1166 0 : cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1167 : else
1168 0 : cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1169 0 : cnt += sprintf(buffer + cnt, "\n");
1170 0 : return cnt;
1171 : }
1172 :
1173 : module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1174 : NULL, 0644);
1175 :
1176 : /**
1177 : * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1178 : * @pdev: Target device.
1179 : *
1180 : * Relies on the upstream bridge's link_state being valid. The link_state
1181 : * is deallocated only when the last child of the bridge (i.e., @pdev or a
1182 : * sibling) is removed, and the caller should be holding a reference to
1183 : * @pdev, so this should be safe.
1184 : */
1185 0 : bool pcie_aspm_enabled(struct pci_dev *pdev)
1186 : {
1187 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1188 :
1189 0 : if (!link)
1190 : return false;
1191 :
1192 0 : return link->aspm_enabled;
1193 : }
1194 : EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1195 :
1196 0 : static ssize_t aspm_attr_show_common(struct device *dev,
1197 : struct device_attribute *attr,
1198 : char *buf, u8 state)
1199 : {
1200 0 : struct pci_dev *pdev = to_pci_dev(dev);
1201 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1202 :
1203 0 : return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0);
1204 : }
1205 :
1206 0 : static ssize_t aspm_attr_store_common(struct device *dev,
1207 : struct device_attribute *attr,
1208 : const char *buf, size_t len, u8 state)
1209 : {
1210 0 : struct pci_dev *pdev = to_pci_dev(dev);
1211 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1212 : bool state_enable;
1213 :
1214 0 : if (kstrtobool(buf, &state_enable) < 0)
1215 : return -EINVAL;
1216 :
1217 0 : down_read(&pci_bus_sem);
1218 0 : mutex_lock(&aspm_lock);
1219 :
1220 0 : if (state_enable) {
1221 0 : link->aspm_disable &= ~state;
1222 : /* need to enable L1 for substates */
1223 0 : if (state & ASPM_STATE_L1SS)
1224 0 : link->aspm_disable &= ~ASPM_STATE_L1;
1225 : } else {
1226 0 : link->aspm_disable |= state;
1227 : }
1228 :
1229 0 : pcie_config_aspm_link(link, policy_to_aspm_state(link));
1230 :
1231 0 : mutex_unlock(&aspm_lock);
1232 0 : up_read(&pci_bus_sem);
1233 :
1234 0 : return len;
1235 : }
1236 :
1237 : #define ASPM_ATTR(_f, _s) \
1238 : static ssize_t _f##_show(struct device *dev, \
1239 : struct device_attribute *attr, char *buf) \
1240 : { return aspm_attr_show_common(dev, attr, buf, ASPM_STATE_##_s); } \
1241 : \
1242 : static ssize_t _f##_store(struct device *dev, \
1243 : struct device_attribute *attr, \
1244 : const char *buf, size_t len) \
1245 : { return aspm_attr_store_common(dev, attr, buf, len, ASPM_STATE_##_s); }
1246 :
1247 0 : ASPM_ATTR(l0s_aspm, L0S)
1248 0 : ASPM_ATTR(l1_aspm, L1)
1249 0 : ASPM_ATTR(l1_1_aspm, L1_1)
1250 0 : ASPM_ATTR(l1_2_aspm, L1_2)
1251 0 : ASPM_ATTR(l1_1_pcipm, L1_1_PCIPM)
1252 0 : ASPM_ATTR(l1_2_pcipm, L1_2_PCIPM)
1253 :
1254 0 : static ssize_t clkpm_show(struct device *dev,
1255 : struct device_attribute *attr, char *buf)
1256 : {
1257 0 : struct pci_dev *pdev = to_pci_dev(dev);
1258 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1259 :
1260 0 : return sysfs_emit(buf, "%d\n", link->clkpm_enabled);
1261 : }
1262 :
1263 0 : static ssize_t clkpm_store(struct device *dev,
1264 : struct device_attribute *attr,
1265 : const char *buf, size_t len)
1266 : {
1267 0 : struct pci_dev *pdev = to_pci_dev(dev);
1268 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1269 : bool state_enable;
1270 :
1271 0 : if (kstrtobool(buf, &state_enable) < 0)
1272 : return -EINVAL;
1273 :
1274 0 : down_read(&pci_bus_sem);
1275 0 : mutex_lock(&aspm_lock);
1276 :
1277 0 : link->clkpm_disable = !state_enable;
1278 0 : pcie_set_clkpm(link, policy_to_clkpm_state(link));
1279 :
1280 0 : mutex_unlock(&aspm_lock);
1281 0 : up_read(&pci_bus_sem);
1282 :
1283 0 : return len;
1284 : }
1285 :
1286 : static DEVICE_ATTR_RW(clkpm);
1287 : static DEVICE_ATTR_RW(l0s_aspm);
1288 : static DEVICE_ATTR_RW(l1_aspm);
1289 : static DEVICE_ATTR_RW(l1_1_aspm);
1290 : static DEVICE_ATTR_RW(l1_2_aspm);
1291 : static DEVICE_ATTR_RW(l1_1_pcipm);
1292 : static DEVICE_ATTR_RW(l1_2_pcipm);
1293 :
1294 : static struct attribute *aspm_ctrl_attrs[] = {
1295 : &dev_attr_clkpm.attr,
1296 : &dev_attr_l0s_aspm.attr,
1297 : &dev_attr_l1_aspm.attr,
1298 : &dev_attr_l1_1_aspm.attr,
1299 : &dev_attr_l1_2_aspm.attr,
1300 : &dev_attr_l1_1_pcipm.attr,
1301 : &dev_attr_l1_2_pcipm.attr,
1302 : NULL
1303 : };
1304 :
1305 0 : static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
1306 : struct attribute *a, int n)
1307 : {
1308 0 : struct device *dev = kobj_to_dev(kobj);
1309 0 : struct pci_dev *pdev = to_pci_dev(dev);
1310 0 : struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1311 : static const u8 aspm_state_map[] = {
1312 : ASPM_STATE_L0S,
1313 : ASPM_STATE_L1,
1314 : ASPM_STATE_L1_1,
1315 : ASPM_STATE_L1_2,
1316 : ASPM_STATE_L1_1_PCIPM,
1317 : ASPM_STATE_L1_2_PCIPM,
1318 : };
1319 :
1320 0 : if (aspm_disabled || !link)
1321 : return 0;
1322 :
1323 0 : if (n == 0)
1324 0 : return link->clkpm_capable ? a->mode : 0;
1325 :
1326 0 : return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
1327 : }
1328 :
1329 : const struct attribute_group aspm_ctrl_attr_group = {
1330 : .name = "link",
1331 : .attrs = aspm_ctrl_attrs,
1332 : .is_visible = aspm_ctrl_attrs_are_visible,
1333 : };
1334 :
1335 0 : static int __init pcie_aspm_disable(char *str)
1336 : {
1337 0 : if (!strcmp(str, "off")) {
1338 0 : aspm_policy = POLICY_DEFAULT;
1339 0 : aspm_disabled = 1;
1340 0 : aspm_support_enabled = false;
1341 0 : printk(KERN_INFO "PCIe ASPM is disabled\n");
1342 0 : } else if (!strcmp(str, "force")) {
1343 0 : aspm_force = 1;
1344 0 : printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1345 : }
1346 0 : return 1;
1347 : }
1348 :
1349 : __setup("pcie_aspm=", pcie_aspm_disable);
1350 :
1351 0 : void pcie_no_aspm(void)
1352 : {
1353 : /*
1354 : * Disabling ASPM is intended to prevent the kernel from modifying
1355 : * existing hardware state, not to clear existing state. To that end:
1356 : * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1357 : * (b) prevent userspace from changing policy
1358 : */
1359 0 : if (!aspm_force) {
1360 0 : aspm_policy = POLICY_DEFAULT;
1361 0 : aspm_disabled = 1;
1362 : }
1363 0 : }
1364 :
1365 0 : bool pcie_aspm_support_enabled(void)
1366 : {
1367 0 : return aspm_support_enabled;
1368 : }
1369 : EXPORT_SYMBOL(pcie_aspm_support_enabled);
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