Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * PCI detection and setup code
4 : */
5 :
6 : #include <linux/kernel.h>
7 : #include <linux/delay.h>
8 : #include <linux/init.h>
9 : #include <linux/pci.h>
10 : #include <linux/msi.h>
11 : #include <linux/of_device.h>
12 : #include <linux/of_pci.h>
13 : #include <linux/pci_hotplug.h>
14 : #include <linux/slab.h>
15 : #include <linux/module.h>
16 : #include <linux/cpumask.h>
17 : #include <linux/aer.h>
18 : #include <linux/acpi.h>
19 : #include <linux/hypervisor.h>
20 : #include <linux/irqdomain.h>
21 : #include <linux/pm_runtime.h>
22 : #include <linux/bitfield.h>
23 : #include "pci.h"
24 :
25 : #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
26 : #define CARDBUS_RESERVE_BUSNR 3
27 :
28 : static struct resource busn_resource = {
29 : .name = "PCI busn",
30 : .start = 0,
31 : .end = 255,
32 : .flags = IORESOURCE_BUS,
33 : };
34 :
35 : /* Ugh. Need to stop exporting this to modules. */
36 : LIST_HEAD(pci_root_buses);
37 : EXPORT_SYMBOL(pci_root_buses);
38 :
39 : static LIST_HEAD(pci_domain_busn_res_list);
40 :
41 : struct pci_domain_busn_res {
42 : struct list_head list;
43 : struct resource res;
44 : int domain_nr;
45 : };
46 :
47 0 : static struct resource *get_pci_domain_busn_res(int domain_nr)
48 : {
49 : struct pci_domain_busn_res *r;
50 :
51 0 : list_for_each_entry(r, &pci_domain_busn_res_list, list)
52 0 : if (r->domain_nr == domain_nr)
53 0 : return &r->res;
54 :
55 0 : r = kzalloc(sizeof(*r), GFP_KERNEL);
56 0 : if (!r)
57 : return NULL;
58 :
59 0 : r->domain_nr = domain_nr;
60 0 : r->res.start = 0;
61 0 : r->res.end = 0xff;
62 0 : r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63 :
64 0 : list_add_tail(&r->list, &pci_domain_busn_res_list);
65 :
66 0 : return &r->res;
67 : }
68 :
69 : /*
70 : * Some device drivers need know if PCI is initiated.
71 : * Basically, we think PCI is not initiated when there
72 : * is no device to be found on the pci_bus_type.
73 : */
74 0 : int no_pci_devices(void)
75 : {
76 : struct device *dev;
77 : int no_devices;
78 :
79 0 : dev = bus_find_next_device(&pci_bus_type, NULL);
80 0 : no_devices = (dev == NULL);
81 0 : put_device(dev);
82 0 : return no_devices;
83 : }
84 : EXPORT_SYMBOL(no_pci_devices);
85 :
86 : /*
87 : * PCI Bus Class
88 : */
89 0 : static void release_pcibus_dev(struct device *dev)
90 : {
91 0 : struct pci_bus *pci_bus = to_pci_bus(dev);
92 :
93 0 : put_device(pci_bus->bridge);
94 0 : pci_bus_remove_resources(pci_bus);
95 0 : pci_release_bus_of_node(pci_bus);
96 0 : kfree(pci_bus);
97 0 : }
98 :
99 : static struct class pcibus_class = {
100 : .name = "pci_bus",
101 : .dev_release = &release_pcibus_dev,
102 : .dev_groups = pcibus_groups,
103 : };
104 :
105 1 : static int __init pcibus_class_init(void)
106 : {
107 1 : return class_register(&pcibus_class);
108 : }
109 : postcore_initcall(pcibus_class_init);
110 :
111 : static u64 pci_size(u64 base, u64 maxbase, u64 mask)
112 : {
113 0 : u64 size = mask & maxbase; /* Find the significant bits */
114 0 : if (!size)
115 : return 0;
116 :
117 : /*
118 : * Get the lowest of them to find the decode size, and from that
119 : * the extent.
120 : */
121 0 : size = size & ~(size-1);
122 :
123 : /*
124 : * base == maxbase can be valid only if the BAR has already been
125 : * programmed with all 1s.
126 : */
127 0 : if (base == maxbase && ((base | (size - 1)) & mask) != mask)
128 : return 0;
129 :
130 : return size;
131 : }
132 :
133 : static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
134 : {
135 : u32 mem_type;
136 : unsigned long flags;
137 :
138 0 : if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
139 0 : flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
140 0 : flags |= IORESOURCE_IO;
141 : return flags;
142 : }
143 :
144 0 : flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
145 0 : flags |= IORESOURCE_MEM;
146 0 : if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
147 0 : flags |= IORESOURCE_PREFETCH;
148 :
149 0 : mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
150 0 : switch (mem_type) {
151 : case PCI_BASE_ADDRESS_MEM_TYPE_32:
152 : break;
153 : case PCI_BASE_ADDRESS_MEM_TYPE_1M:
154 : /* 1M mem BAR treated as 32-bit BAR */
155 : break;
156 : case PCI_BASE_ADDRESS_MEM_TYPE_64:
157 0 : flags |= IORESOURCE_MEM_64;
158 : break;
159 : default:
160 : /* mem unknown type treated as 32-bit BAR */
161 : break;
162 : }
163 : return flags;
164 : }
165 :
166 : #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 :
168 : /**
169 : * __pci_read_base - Read a PCI BAR
170 : * @dev: the PCI device
171 : * @type: type of the BAR
172 : * @res: resource buffer to be filled in
173 : * @pos: BAR position in the config space
174 : *
175 : * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
176 : */
177 0 : int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
178 : struct resource *res, unsigned int pos)
179 : {
180 0 : u32 l = 0, sz = 0, mask;
181 : u64 l64, sz64, mask64;
182 : u16 orig_cmd;
183 : struct pci_bus_region region, inverted_region;
184 :
185 0 : mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186 :
187 : /* No printks while decoding is disabled! */
188 0 : if (!dev->mmio_always_on) {
189 0 : pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 0 : if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 0 : pci_write_config_word(dev, PCI_COMMAND,
192 : orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 : }
194 : }
195 :
196 0 : res->name = pci_name(dev);
197 :
198 0 : pci_read_config_dword(dev, pos, &l);
199 0 : pci_write_config_dword(dev, pos, l | mask);
200 0 : pci_read_config_dword(dev, pos, &sz);
201 0 : pci_write_config_dword(dev, pos, l);
202 :
203 : /*
204 : * All bits set in sz means the device isn't working properly.
205 : * If the BAR isn't implemented, all bits must be 0. If it's a
206 : * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 : * 1 must be clear.
208 : */
209 0 : if (PCI_POSSIBLE_ERROR(sz))
210 0 : sz = 0;
211 :
212 : /*
213 : * I don't know how l can have all bits set. Copied from old code.
214 : * Maybe it fixes a bug on some ancient platform.
215 : */
216 0 : if (PCI_POSSIBLE_ERROR(l))
217 0 : l = 0;
218 :
219 0 : if (type == pci_bar_unknown) {
220 0 : res->flags = decode_bar(dev, l);
221 0 : res->flags |= IORESOURCE_SIZEALIGN;
222 0 : if (res->flags & IORESOURCE_IO) {
223 0 : l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 0 : sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 0 : mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 : } else {
227 0 : l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 0 : sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 0 : mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 : }
231 : } else {
232 0 : if (l & PCI_ROM_ADDRESS_ENABLE)
233 0 : res->flags |= IORESOURCE_ROM_ENABLE;
234 0 : l64 = l & PCI_ROM_ADDRESS_MASK;
235 0 : sz64 = sz & PCI_ROM_ADDRESS_MASK;
236 0 : mask64 = PCI_ROM_ADDRESS_MASK;
237 : }
238 :
239 0 : if (res->flags & IORESOURCE_MEM_64) {
240 0 : pci_read_config_dword(dev, pos + 4, &l);
241 0 : pci_write_config_dword(dev, pos + 4, ~0);
242 0 : pci_read_config_dword(dev, pos + 4, &sz);
243 0 : pci_write_config_dword(dev, pos + 4, l);
244 :
245 0 : l64 |= ((u64)l << 32);
246 0 : sz64 |= ((u64)sz << 32);
247 0 : mask64 |= ((u64)~0 << 32);
248 : }
249 :
250 0 : if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
251 0 : pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252 :
253 0 : if (!sz64)
254 : goto fail;
255 :
256 0 : sz64 = pci_size(l64, sz64, mask64);
257 0 : if (!sz64) {
258 0 : pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
259 : pos);
260 0 : goto fail;
261 : }
262 :
263 : if (res->flags & IORESOURCE_MEM_64) {
264 : if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
265 : && sz64 > 0x100000000ULL) {
266 : res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
267 : res->start = 0;
268 : res->end = 0;
269 : pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
270 : pos, (unsigned long long)sz64);
271 : goto out;
272 : }
273 :
274 : if ((sizeof(pci_bus_addr_t) < 8) && l) {
275 : /* Above 32-bit boundary; try to reallocate */
276 : res->flags |= IORESOURCE_UNSET;
277 : res->start = 0;
278 : res->end = sz64 - 1;
279 : pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
280 : pos, (unsigned long long)l64);
281 : goto out;
282 : }
283 : }
284 :
285 0 : region.start = l64;
286 0 : region.end = l64 + sz64 - 1;
287 :
288 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
289 0 : pcibios_resource_to_bus(dev->bus, &inverted_region, res);
290 :
291 : /*
292 : * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
293 : * the corresponding resource address (the physical address used by
294 : * the CPU. Converting that resource address back to a bus address
295 : * should yield the original BAR value:
296 : *
297 : * resource_to_bus(bus_to_resource(A)) == A
298 : *
299 : * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
300 : * be claimed by the device.
301 : */
302 0 : if (inverted_region.start != region.start) {
303 0 : res->flags |= IORESOURCE_UNSET;
304 0 : res->start = 0;
305 0 : res->end = region.end - region.start;
306 0 : pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
307 : pos, (unsigned long long)region.start);
308 : }
309 :
310 : goto out;
311 :
312 :
313 : fail:
314 0 : res->flags = 0;
315 : out:
316 0 : if (res->flags)
317 0 : pci_info(dev, "reg 0x%x: %pR\n", pos, res);
318 :
319 0 : return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
320 : }
321 :
322 0 : static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
323 : {
324 : unsigned int pos, reg;
325 :
326 0 : if (dev->non_compliant_bars)
327 : return;
328 :
329 : /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
330 0 : if (dev->is_virtfn)
331 : return;
332 :
333 0 : for (pos = 0; pos < howmany; pos++) {
334 0 : struct resource *res = &dev->resource[pos];
335 0 : reg = PCI_BASE_ADDRESS_0 + (pos << 2);
336 0 : pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
337 : }
338 :
339 0 : if (rom) {
340 0 : struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
341 0 : dev->rom_base_reg = rom;
342 0 : res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
343 : IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
344 0 : __pci_read_base(dev, pci_bar_mem32, res, rom);
345 : }
346 : }
347 :
348 0 : static void pci_read_bridge_windows(struct pci_dev *bridge)
349 : {
350 : u16 io;
351 : u32 pmem, tmp;
352 :
353 0 : pci_read_config_word(bridge, PCI_IO_BASE, &io);
354 0 : if (!io) {
355 0 : pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
356 0 : pci_read_config_word(bridge, PCI_IO_BASE, &io);
357 0 : pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
358 : }
359 0 : if (io)
360 0 : bridge->io_window = 1;
361 :
362 : /*
363 : * DECchip 21050 pass 2 errata: the bridge may miss an address
364 : * disconnect boundary by one PCI data phase. Workaround: do not
365 : * use prefetching on this device.
366 : */
367 0 : if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
368 0 : return;
369 :
370 0 : pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
371 0 : if (!pmem) {
372 0 : pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
373 : 0xffe0fff0);
374 0 : pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
375 0 : pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
376 : }
377 0 : if (!pmem)
378 : return;
379 :
380 0 : bridge->pref_window = 1;
381 :
382 0 : if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
383 :
384 : /*
385 : * Bridge claims to have a 64-bit prefetchable memory
386 : * window; verify that the upper bits are actually
387 : * writable.
388 : */
389 0 : pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
390 0 : pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
391 : 0xffffffff);
392 0 : pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
393 0 : pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
394 0 : if (tmp)
395 0 : bridge->pref_64_window = 1;
396 : }
397 : }
398 :
399 0 : static void pci_read_bridge_io(struct pci_bus *child)
400 : {
401 0 : struct pci_dev *dev = child->self;
402 : u8 io_base_lo, io_limit_lo;
403 : unsigned long io_mask, io_granularity, base, limit;
404 : struct pci_bus_region region;
405 : struct resource *res;
406 :
407 0 : io_mask = PCI_IO_RANGE_MASK;
408 0 : io_granularity = 0x1000;
409 0 : if (dev->io_window_1k) {
410 : /* Support 1K I/O space granularity */
411 0 : io_mask = PCI_IO_1K_RANGE_MASK;
412 0 : io_granularity = 0x400;
413 : }
414 :
415 0 : res = child->resource[0];
416 0 : pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
417 0 : pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
418 0 : base = (io_base_lo & io_mask) << 8;
419 0 : limit = (io_limit_lo & io_mask) << 8;
420 :
421 0 : if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
422 : u16 io_base_hi, io_limit_hi;
423 :
424 0 : pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
425 0 : pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
426 0 : base |= ((unsigned long) io_base_hi << 16);
427 0 : limit |= ((unsigned long) io_limit_hi << 16);
428 : }
429 :
430 0 : if (base <= limit) {
431 0 : res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
432 0 : region.start = base;
433 0 : region.end = limit + io_granularity - 1;
434 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
435 0 : pci_info(dev, " bridge window %pR\n", res);
436 : }
437 0 : }
438 :
439 0 : static void pci_read_bridge_mmio(struct pci_bus *child)
440 : {
441 0 : struct pci_dev *dev = child->self;
442 : u16 mem_base_lo, mem_limit_lo;
443 : unsigned long base, limit;
444 : struct pci_bus_region region;
445 : struct resource *res;
446 :
447 0 : res = child->resource[1];
448 0 : pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
449 0 : pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
450 0 : base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 0 : limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
452 0 : if (base <= limit) {
453 0 : res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
454 0 : region.start = base;
455 0 : region.end = limit + 0xfffff;
456 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
457 0 : pci_info(dev, " bridge window %pR\n", res);
458 : }
459 0 : }
460 :
461 0 : static void pci_read_bridge_mmio_pref(struct pci_bus *child)
462 : {
463 0 : struct pci_dev *dev = child->self;
464 : u16 mem_base_lo, mem_limit_lo;
465 : u64 base64, limit64;
466 : pci_bus_addr_t base, limit;
467 : struct pci_bus_region region;
468 : struct resource *res;
469 :
470 0 : res = child->resource[2];
471 0 : pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
472 0 : pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
473 0 : base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
474 0 : limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
475 :
476 0 : if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
477 : u32 mem_base_hi, mem_limit_hi;
478 :
479 0 : pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
480 0 : pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
481 :
482 : /*
483 : * Some bridges set the base > limit by default, and some
484 : * (broken) BIOSes do not initialize them. If we find
485 : * this, just assume they are not being used.
486 : */
487 0 : if (mem_base_hi <= mem_limit_hi) {
488 0 : base64 |= (u64) mem_base_hi << 32;
489 0 : limit64 |= (u64) mem_limit_hi << 32;
490 : }
491 : }
492 :
493 0 : base = (pci_bus_addr_t) base64;
494 0 : limit = (pci_bus_addr_t) limit64;
495 :
496 : if (base != base64) {
497 : pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
498 : (unsigned long long) base64);
499 : return;
500 : }
501 :
502 0 : if (base <= limit) {
503 0 : res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
504 0 : IORESOURCE_MEM | IORESOURCE_PREFETCH;
505 0 : if (res->flags & PCI_PREF_RANGE_TYPE_64)
506 0 : res->flags |= IORESOURCE_MEM_64;
507 0 : region.start = base;
508 0 : region.end = limit + 0xfffff;
509 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
510 0 : pci_info(dev, " bridge window %pR\n", res);
511 : }
512 : }
513 :
514 0 : void pci_read_bridge_bases(struct pci_bus *child)
515 : {
516 0 : struct pci_dev *dev = child->self;
517 : struct resource *res;
518 : int i;
519 :
520 0 : if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
521 : return;
522 :
523 0 : pci_info(dev, "PCI bridge to %pR%s\n",
524 : &child->busn_res,
525 : dev->transparent ? " (subtractive decode)" : "");
526 :
527 0 : pci_bus_remove_resources(child);
528 0 : for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
529 0 : child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
530 :
531 0 : pci_read_bridge_io(child);
532 0 : pci_read_bridge_mmio(child);
533 0 : pci_read_bridge_mmio_pref(child);
534 :
535 0 : if (dev->transparent) {
536 0 : pci_bus_for_each_resource(child->parent, res, i) {
537 0 : if (res && res->flags) {
538 0 : pci_bus_add_resource(child, res,
539 : PCI_SUBTRACTIVE_DECODE);
540 0 : pci_info(dev, " bridge window %pR (subtractive decode)\n",
541 : res);
542 : }
543 : }
544 : }
545 : }
546 :
547 0 : static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
548 : {
549 : struct pci_bus *b;
550 :
551 0 : b = kzalloc(sizeof(*b), GFP_KERNEL);
552 0 : if (!b)
553 : return NULL;
554 :
555 0 : INIT_LIST_HEAD(&b->node);
556 0 : INIT_LIST_HEAD(&b->children);
557 0 : INIT_LIST_HEAD(&b->devices);
558 0 : INIT_LIST_HEAD(&b->slots);
559 0 : INIT_LIST_HEAD(&b->resources);
560 0 : b->max_bus_speed = PCI_SPEED_UNKNOWN;
561 0 : b->cur_bus_speed = PCI_SPEED_UNKNOWN;
562 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
563 : if (parent)
564 : b->domain_nr = parent->domain_nr;
565 : #endif
566 : return b;
567 : }
568 :
569 0 : static void pci_release_host_bridge_dev(struct device *dev)
570 : {
571 0 : struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
572 :
573 0 : if (bridge->release_fn)
574 0 : bridge->release_fn(bridge);
575 :
576 0 : pci_free_resource_list(&bridge->windows);
577 0 : pci_free_resource_list(&bridge->dma_ranges);
578 0 : kfree(bridge);
579 0 : }
580 :
581 : static void pci_init_host_bridge(struct pci_host_bridge *bridge)
582 : {
583 0 : INIT_LIST_HEAD(&bridge->windows);
584 0 : INIT_LIST_HEAD(&bridge->dma_ranges);
585 :
586 : /*
587 : * We assume we can manage these PCIe features. Some systems may
588 : * reserve these for use by the platform itself, e.g., an ACPI BIOS
589 : * may implement its own AER handling and use _OSC to prevent the
590 : * OS from interfering.
591 : */
592 0 : bridge->native_aer = 1;
593 0 : bridge->native_pcie_hotplug = 1;
594 0 : bridge->native_shpc_hotplug = 1;
595 0 : bridge->native_pme = 1;
596 0 : bridge->native_ltr = 1;
597 0 : bridge->native_dpc = 1;
598 0 : bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
599 :
600 0 : device_initialize(&bridge->dev);
601 : }
602 :
603 0 : struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
604 : {
605 : struct pci_host_bridge *bridge;
606 :
607 0 : bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
608 0 : if (!bridge)
609 : return NULL;
610 :
611 0 : pci_init_host_bridge(bridge);
612 0 : bridge->dev.release = pci_release_host_bridge_dev;
613 :
614 0 : return bridge;
615 : }
616 : EXPORT_SYMBOL(pci_alloc_host_bridge);
617 :
618 0 : static void devm_pci_alloc_host_bridge_release(void *data)
619 : {
620 0 : pci_free_host_bridge(data);
621 0 : }
622 :
623 0 : struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
624 : size_t priv)
625 : {
626 : int ret;
627 : struct pci_host_bridge *bridge;
628 :
629 0 : bridge = pci_alloc_host_bridge(priv);
630 0 : if (!bridge)
631 : return NULL;
632 :
633 0 : bridge->dev.parent = dev;
634 :
635 0 : ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
636 : bridge);
637 0 : if (ret)
638 : return NULL;
639 :
640 0 : ret = devm_of_pci_bridge_init(dev, bridge);
641 : if (ret)
642 : return NULL;
643 :
644 0 : return bridge;
645 : }
646 : EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
647 :
648 0 : void pci_free_host_bridge(struct pci_host_bridge *bridge)
649 : {
650 0 : put_device(&bridge->dev);
651 0 : }
652 : EXPORT_SYMBOL(pci_free_host_bridge);
653 :
654 : /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
655 : static const unsigned char pcix_bus_speed[] = {
656 : PCI_SPEED_UNKNOWN, /* 0 */
657 : PCI_SPEED_66MHz_PCIX, /* 1 */
658 : PCI_SPEED_100MHz_PCIX, /* 2 */
659 : PCI_SPEED_133MHz_PCIX, /* 3 */
660 : PCI_SPEED_UNKNOWN, /* 4 */
661 : PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
662 : PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
663 : PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
664 : PCI_SPEED_UNKNOWN, /* 8 */
665 : PCI_SPEED_66MHz_PCIX_266, /* 9 */
666 : PCI_SPEED_100MHz_PCIX_266, /* A */
667 : PCI_SPEED_133MHz_PCIX_266, /* B */
668 : PCI_SPEED_UNKNOWN, /* C */
669 : PCI_SPEED_66MHz_PCIX_533, /* D */
670 : PCI_SPEED_100MHz_PCIX_533, /* E */
671 : PCI_SPEED_133MHz_PCIX_533 /* F */
672 : };
673 :
674 : /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
675 : const unsigned char pcie_link_speed[] = {
676 : PCI_SPEED_UNKNOWN, /* 0 */
677 : PCIE_SPEED_2_5GT, /* 1 */
678 : PCIE_SPEED_5_0GT, /* 2 */
679 : PCIE_SPEED_8_0GT, /* 3 */
680 : PCIE_SPEED_16_0GT, /* 4 */
681 : PCIE_SPEED_32_0GT, /* 5 */
682 : PCIE_SPEED_64_0GT, /* 6 */
683 : PCI_SPEED_UNKNOWN, /* 7 */
684 : PCI_SPEED_UNKNOWN, /* 8 */
685 : PCI_SPEED_UNKNOWN, /* 9 */
686 : PCI_SPEED_UNKNOWN, /* A */
687 : PCI_SPEED_UNKNOWN, /* B */
688 : PCI_SPEED_UNKNOWN, /* C */
689 : PCI_SPEED_UNKNOWN, /* D */
690 : PCI_SPEED_UNKNOWN, /* E */
691 : PCI_SPEED_UNKNOWN /* F */
692 : };
693 : EXPORT_SYMBOL_GPL(pcie_link_speed);
694 :
695 0 : const char *pci_speed_string(enum pci_bus_speed speed)
696 : {
697 : /* Indexed by the pci_bus_speed enum */
698 : static const char *speed_strings[] = {
699 : "33 MHz PCI", /* 0x00 */
700 : "66 MHz PCI", /* 0x01 */
701 : "66 MHz PCI-X", /* 0x02 */
702 : "100 MHz PCI-X", /* 0x03 */
703 : "133 MHz PCI-X", /* 0x04 */
704 : NULL, /* 0x05 */
705 : NULL, /* 0x06 */
706 : NULL, /* 0x07 */
707 : NULL, /* 0x08 */
708 : "66 MHz PCI-X 266", /* 0x09 */
709 : "100 MHz PCI-X 266", /* 0x0a */
710 : "133 MHz PCI-X 266", /* 0x0b */
711 : "Unknown AGP", /* 0x0c */
712 : "1x AGP", /* 0x0d */
713 : "2x AGP", /* 0x0e */
714 : "4x AGP", /* 0x0f */
715 : "8x AGP", /* 0x10 */
716 : "66 MHz PCI-X 533", /* 0x11 */
717 : "100 MHz PCI-X 533", /* 0x12 */
718 : "133 MHz PCI-X 533", /* 0x13 */
719 : "2.5 GT/s PCIe", /* 0x14 */
720 : "5.0 GT/s PCIe", /* 0x15 */
721 : "8.0 GT/s PCIe", /* 0x16 */
722 : "16.0 GT/s PCIe", /* 0x17 */
723 : "32.0 GT/s PCIe", /* 0x18 */
724 : "64.0 GT/s PCIe", /* 0x19 */
725 : };
726 :
727 0 : if (speed < ARRAY_SIZE(speed_strings))
728 0 : return speed_strings[speed];
729 : return "Unknown";
730 : }
731 : EXPORT_SYMBOL_GPL(pci_speed_string);
732 :
733 0 : void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
734 : {
735 0 : bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
736 0 : }
737 : EXPORT_SYMBOL_GPL(pcie_update_link_speed);
738 :
739 : static unsigned char agp_speeds[] = {
740 : AGP_UNKNOWN,
741 : AGP_1X,
742 : AGP_2X,
743 : AGP_4X,
744 : AGP_8X
745 : };
746 :
747 : static enum pci_bus_speed agp_speed(int agp3, int agpstat)
748 : {
749 0 : int index = 0;
750 :
751 0 : if (agpstat & 4)
752 : index = 3;
753 0 : else if (agpstat & 2)
754 : index = 2;
755 0 : else if (agpstat & 1)
756 : index = 1;
757 : else
758 : goto out;
759 :
760 0 : if (agp3) {
761 0 : index += 2;
762 0 : if (index == 5)
763 0 : index = 0;
764 : }
765 :
766 : out:
767 0 : return agp_speeds[index];
768 : }
769 :
770 0 : static void pci_set_bus_speed(struct pci_bus *bus)
771 : {
772 0 : struct pci_dev *bridge = bus->self;
773 : int pos;
774 :
775 0 : pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
776 0 : if (!pos)
777 0 : pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
778 0 : if (pos) {
779 : u32 agpstat, agpcmd;
780 :
781 0 : pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
782 0 : bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
783 :
784 0 : pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
785 0 : bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
786 : }
787 :
788 0 : pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
789 0 : if (pos) {
790 : u16 status;
791 : enum pci_bus_speed max;
792 :
793 0 : pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
794 : &status);
795 :
796 0 : if (status & PCI_X_SSTATUS_533MHZ) {
797 : max = PCI_SPEED_133MHz_PCIX_533;
798 0 : } else if (status & PCI_X_SSTATUS_266MHZ) {
799 : max = PCI_SPEED_133MHz_PCIX_266;
800 0 : } else if (status & PCI_X_SSTATUS_133MHZ) {
801 0 : if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
802 : max = PCI_SPEED_133MHz_PCIX_ECC;
803 : else
804 0 : max = PCI_SPEED_133MHz_PCIX;
805 : } else {
806 : max = PCI_SPEED_66MHz_PCIX;
807 : }
808 :
809 0 : bus->max_bus_speed = max;
810 0 : bus->cur_bus_speed = pcix_bus_speed[
811 0 : (status & PCI_X_SSTATUS_FREQ) >> 6];
812 :
813 : return;
814 : }
815 :
816 0 : if (pci_is_pcie(bridge)) {
817 : u32 linkcap;
818 : u16 linksta;
819 :
820 0 : pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
821 0 : bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
822 0 : bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
823 :
824 0 : pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
825 0 : pcie_update_link_speed(bus, linksta);
826 : }
827 : }
828 :
829 0 : static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
830 : {
831 : struct irq_domain *d;
832 :
833 : /* If the host bridge driver sets a MSI domain of the bridge, use it */
834 0 : d = dev_get_msi_domain(bus->bridge);
835 :
836 : /*
837 : * Any firmware interface that can resolve the msi_domain
838 : * should be called from here.
839 : */
840 0 : if (!d)
841 0 : d = pci_host_bridge_of_msi_domain(bus);
842 0 : if (!d)
843 0 : d = pci_host_bridge_acpi_msi_domain(bus);
844 :
845 : #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
846 : /*
847 : * If no IRQ domain was found via the OF tree, try looking it up
848 : * directly through the fwnode_handle.
849 : */
850 0 : if (!d) {
851 0 : struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
852 :
853 0 : if (fwnode)
854 0 : d = irq_find_matching_fwnode(fwnode,
855 : DOMAIN_BUS_PCI_MSI);
856 : }
857 : #endif
858 :
859 0 : return d;
860 : }
861 :
862 0 : static void pci_set_bus_msi_domain(struct pci_bus *bus)
863 : {
864 : struct irq_domain *d;
865 : struct pci_bus *b;
866 :
867 : /*
868 : * The bus can be a root bus, a subordinate bus, or a virtual bus
869 : * created by an SR-IOV device. Walk up to the first bridge device
870 : * found or derive the domain from the host bridge.
871 : */
872 0 : for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
873 0 : if (b->self)
874 0 : d = dev_get_msi_domain(&b->self->dev);
875 : }
876 :
877 0 : if (!d)
878 0 : d = pci_host_bridge_msi_domain(b);
879 :
880 0 : dev_set_msi_domain(&bus->dev, d);
881 0 : }
882 :
883 0 : static int pci_register_host_bridge(struct pci_host_bridge *bridge)
884 : {
885 0 : struct device *parent = bridge->dev.parent;
886 : struct resource_entry *window, *next, *n;
887 : struct pci_bus *bus, *b;
888 : resource_size_t offset, next_offset;
889 0 : LIST_HEAD(resources);
890 : struct resource *res, *next_res;
891 : char addr[64], *fmt;
892 : const char *name;
893 : int err;
894 :
895 0 : bus = pci_alloc_bus(NULL);
896 0 : if (!bus)
897 : return -ENOMEM;
898 :
899 0 : bridge->bus = bus;
900 :
901 0 : bus->sysdata = bridge->sysdata;
902 0 : bus->ops = bridge->ops;
903 0 : bus->number = bus->busn_res.start = bridge->busnr;
904 : #ifdef CONFIG_PCI_DOMAINS_GENERIC
905 : if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
906 : bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
907 : else
908 : bus->domain_nr = bridge->domain_nr;
909 : #endif
910 :
911 0 : b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
912 0 : if (b) {
913 : /* Ignore it if we already got here via a different bridge */
914 : dev_dbg(&b->dev, "bus already known\n");
915 : err = -EEXIST;
916 : goto free;
917 : }
918 :
919 0 : dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
920 : bridge->busnr);
921 :
922 0 : err = pcibios_root_bridge_prepare(bridge);
923 0 : if (err)
924 : goto free;
925 :
926 : /* Temporarily move resources off the list */
927 0 : list_splice_init(&bridge->windows, &resources);
928 0 : err = device_add(&bridge->dev);
929 0 : if (err) {
930 0 : put_device(&bridge->dev);
931 0 : goto free;
932 : }
933 0 : bus->bridge = get_device(&bridge->dev);
934 0 : device_enable_async_suspend(bus->bridge);
935 0 : pci_set_bus_of_node(bus);
936 0 : pci_set_bus_msi_domain(bus);
937 0 : if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
938 0 : !pci_host_of_has_msi_map(parent))
939 0 : bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
940 :
941 : if (!parent)
942 : set_dev_node(bus->bridge, pcibus_to_node(bus));
943 :
944 0 : bus->dev.class = &pcibus_class;
945 0 : bus->dev.parent = bus->bridge;
946 :
947 0 : dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
948 0 : name = dev_name(&bus->dev);
949 :
950 0 : err = device_register(&bus->dev);
951 0 : if (err)
952 : goto unregister;
953 :
954 0 : pcibios_add_bus(bus);
955 :
956 0 : if (bus->ops->add_bus) {
957 0 : err = bus->ops->add_bus(bus);
958 0 : if (WARN_ON(err < 0))
959 0 : dev_err(&bus->dev, "failed to add bus: %d\n", err);
960 : }
961 :
962 : /* Create legacy_io and legacy_mem files for this bus */
963 0 : pci_create_legacy_files(bus);
964 :
965 0 : if (parent)
966 0 : dev_info(parent, "PCI host bridge to bus %s\n", name);
967 : else
968 0 : pr_info("PCI host bridge to bus %s\n", name);
969 :
970 : if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
971 : dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
972 :
973 : /* Coalesce contiguous windows */
974 0 : resource_list_for_each_entry_safe(window, n, &resources) {
975 0 : if (list_is_last(&window->node, &resources))
976 : break;
977 :
978 0 : next = list_next_entry(window, node);
979 0 : offset = window->offset;
980 0 : res = window->res;
981 0 : next_offset = next->offset;
982 0 : next_res = next->res;
983 :
984 0 : if (res->flags != next_res->flags || offset != next_offset)
985 0 : continue;
986 :
987 0 : if (res->end + 1 == next_res->start) {
988 0 : next_res->start = res->start;
989 0 : res->flags = res->start = res->end = 0;
990 : }
991 : }
992 :
993 : /* Add initial resources to the bus */
994 0 : resource_list_for_each_entry_safe(window, n, &resources) {
995 0 : offset = window->offset;
996 0 : res = window->res;
997 0 : if (!res->end)
998 0 : continue;
999 :
1000 0 : list_move_tail(&window->node, &bridge->windows);
1001 :
1002 0 : if (res->flags & IORESOURCE_BUS)
1003 0 : pci_bus_insert_busn_res(bus, bus->number, res->end);
1004 : else
1005 0 : pci_bus_add_resource(bus, res, 0);
1006 :
1007 0 : if (offset) {
1008 0 : if (resource_type(res) == IORESOURCE_IO)
1009 : fmt = " (bus address [%#06llx-%#06llx])";
1010 : else
1011 0 : fmt = " (bus address [%#010llx-%#010llx])";
1012 :
1013 0 : snprintf(addr, sizeof(addr), fmt,
1014 0 : (unsigned long long)(res->start - offset),
1015 0 : (unsigned long long)(res->end - offset));
1016 : } else
1017 0 : addr[0] = '\0';
1018 :
1019 0 : dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1020 : }
1021 :
1022 0 : down_write(&pci_bus_sem);
1023 0 : list_add_tail(&bus->node, &pci_root_buses);
1024 0 : up_write(&pci_bus_sem);
1025 :
1026 0 : return 0;
1027 :
1028 : unregister:
1029 0 : put_device(&bridge->dev);
1030 0 : device_del(&bridge->dev);
1031 :
1032 : free:
1033 0 : kfree(bus);
1034 0 : return err;
1035 : }
1036 :
1037 0 : static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1038 : {
1039 : int pos;
1040 : u32 status;
1041 :
1042 : /*
1043 : * If extended config space isn't accessible on a bridge's primary
1044 : * bus, we certainly can't access it on the secondary bus.
1045 : */
1046 0 : if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1047 : return false;
1048 :
1049 : /*
1050 : * PCIe Root Ports and switch ports are PCIe on both sides, so if
1051 : * extended config space is accessible on the primary, it's also
1052 : * accessible on the secondary.
1053 : */
1054 0 : if (pci_is_pcie(bridge) &&
1055 0 : (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1056 0 : pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1057 0 : pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1058 : return true;
1059 :
1060 : /*
1061 : * For the other bridge types:
1062 : * - PCI-to-PCI bridges
1063 : * - PCIe-to-PCI/PCI-X forward bridges
1064 : * - PCI/PCI-X-to-PCIe reverse bridges
1065 : * extended config space on the secondary side is only accessible
1066 : * if the bridge supports PCI-X Mode 2.
1067 : */
1068 0 : pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1069 0 : if (!pos)
1070 : return false;
1071 :
1072 0 : pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1073 0 : return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1074 : }
1075 :
1076 0 : static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1077 : struct pci_dev *bridge, int busnr)
1078 : {
1079 : struct pci_bus *child;
1080 : struct pci_host_bridge *host;
1081 : int i;
1082 : int ret;
1083 :
1084 : /* Allocate a new bus and inherit stuff from the parent */
1085 0 : child = pci_alloc_bus(parent);
1086 0 : if (!child)
1087 : return NULL;
1088 :
1089 0 : child->parent = parent;
1090 0 : child->sysdata = parent->sysdata;
1091 0 : child->bus_flags = parent->bus_flags;
1092 :
1093 0 : host = pci_find_host_bridge(parent);
1094 0 : if (host->child_ops)
1095 0 : child->ops = host->child_ops;
1096 : else
1097 0 : child->ops = parent->ops;
1098 :
1099 : /*
1100 : * Initialize some portions of the bus device, but don't register
1101 : * it now as the parent is not properly set up yet.
1102 : */
1103 0 : child->dev.class = &pcibus_class;
1104 0 : dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1105 :
1106 : /* Set up the primary, secondary and subordinate bus numbers */
1107 0 : child->number = child->busn_res.start = busnr;
1108 0 : child->primary = parent->busn_res.start;
1109 0 : child->busn_res.end = 0xff;
1110 :
1111 0 : if (!bridge) {
1112 0 : child->dev.parent = parent->bridge;
1113 0 : goto add_dev;
1114 : }
1115 :
1116 0 : child->self = bridge;
1117 0 : child->bridge = get_device(&bridge->dev);
1118 0 : child->dev.parent = child->bridge;
1119 0 : pci_set_bus_of_node(child);
1120 0 : pci_set_bus_speed(child);
1121 :
1122 : /*
1123 : * Check whether extended config space is accessible on the child
1124 : * bus. Note that we currently assume it is always accessible on
1125 : * the root bus.
1126 : */
1127 0 : if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1128 0 : child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1129 0 : pci_info(child, "extended config space not accessible\n");
1130 : }
1131 :
1132 : /* Set up default resource pointers and names */
1133 0 : for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1134 0 : child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1135 0 : child->resource[i]->name = child->name;
1136 : }
1137 0 : bridge->subordinate = child;
1138 :
1139 : add_dev:
1140 0 : pci_set_bus_msi_domain(child);
1141 0 : ret = device_register(&child->dev);
1142 0 : WARN_ON(ret < 0);
1143 :
1144 0 : pcibios_add_bus(child);
1145 :
1146 0 : if (child->ops->add_bus) {
1147 0 : ret = child->ops->add_bus(child);
1148 0 : if (WARN_ON(ret < 0))
1149 0 : dev_err(&child->dev, "failed to add bus: %d\n", ret);
1150 : }
1151 :
1152 : /* Create legacy_io and legacy_mem files for this bus */
1153 : pci_create_legacy_files(child);
1154 :
1155 : return child;
1156 : }
1157 :
1158 0 : struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1159 : int busnr)
1160 : {
1161 : struct pci_bus *child;
1162 :
1163 0 : child = pci_alloc_child_bus(parent, dev, busnr);
1164 0 : if (child) {
1165 0 : down_write(&pci_bus_sem);
1166 0 : list_add_tail(&child->node, &parent->children);
1167 0 : up_write(&pci_bus_sem);
1168 : }
1169 0 : return child;
1170 : }
1171 : EXPORT_SYMBOL(pci_add_new_bus);
1172 :
1173 0 : static void pci_enable_crs(struct pci_dev *pdev)
1174 : {
1175 0 : u16 root_cap = 0;
1176 :
1177 : /* Enable CRS Software Visibility if supported */
1178 0 : pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1179 0 : if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1180 : pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1181 : PCI_EXP_RTCTL_CRSSVE);
1182 0 : }
1183 :
1184 : static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1185 : unsigned int available_buses);
1186 : /**
1187 : * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1188 : * numbers from EA capability.
1189 : * @dev: Bridge
1190 : * @sec: updated with secondary bus number from EA
1191 : * @sub: updated with subordinate bus number from EA
1192 : *
1193 : * If @dev is a bridge with EA capability that specifies valid secondary
1194 : * and subordinate bus numbers, return true with the bus numbers in @sec
1195 : * and @sub. Otherwise return false.
1196 : */
1197 0 : static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1198 : {
1199 : int ea, offset;
1200 : u32 dw;
1201 : u8 ea_sec, ea_sub;
1202 :
1203 0 : if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1204 : return false;
1205 :
1206 : /* find PCI EA capability in list */
1207 0 : ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1208 0 : if (!ea)
1209 : return false;
1210 :
1211 0 : offset = ea + PCI_EA_FIRST_ENT;
1212 0 : pci_read_config_dword(dev, offset, &dw);
1213 0 : ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1214 0 : ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1215 0 : if (ea_sec == 0 || ea_sub < ea_sec)
1216 : return false;
1217 :
1218 0 : *sec = ea_sec;
1219 0 : *sub = ea_sub;
1220 0 : return true;
1221 : }
1222 :
1223 : /*
1224 : * pci_scan_bridge_extend() - Scan buses behind a bridge
1225 : * @bus: Parent bus the bridge is on
1226 : * @dev: Bridge itself
1227 : * @max: Starting subordinate number of buses behind this bridge
1228 : * @available_buses: Total number of buses available for this bridge and
1229 : * the devices below. After the minimal bus space has
1230 : * been allocated the remaining buses will be
1231 : * distributed equally between hotplug-capable bridges.
1232 : * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1233 : * that need to be reconfigured.
1234 : *
1235 : * If it's a bridge, configure it and scan the bus behind it.
1236 : * For CardBus bridges, we don't scan behind as the devices will
1237 : * be handled by the bridge driver itself.
1238 : *
1239 : * We need to process bridges in two passes -- first we scan those
1240 : * already configured by the BIOS and after we are done with all of
1241 : * them, we proceed to assigning numbers to the remaining buses in
1242 : * order to avoid overlaps between old and new bus numbers.
1243 : *
1244 : * Return: New subordinate number covering all buses behind this bridge.
1245 : */
1246 0 : static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1247 : int max, unsigned int available_buses,
1248 : int pass)
1249 : {
1250 : struct pci_bus *child;
1251 0 : int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1252 0 : u32 buses, i, j = 0;
1253 : u16 bctl;
1254 : u8 primary, secondary, subordinate;
1255 0 : int broken = 0;
1256 : bool fixed_buses;
1257 : u8 fixed_sec, fixed_sub;
1258 : int next_busnr;
1259 :
1260 : /*
1261 : * Make sure the bridge is powered on to be able to access config
1262 : * space of devices below it.
1263 : */
1264 0 : pm_runtime_get_sync(&dev->dev);
1265 :
1266 0 : pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1267 0 : primary = buses & 0xFF;
1268 0 : secondary = (buses >> 8) & 0xFF;
1269 0 : subordinate = (buses >> 16) & 0xFF;
1270 :
1271 : pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1272 : secondary, subordinate, pass);
1273 :
1274 0 : if (!primary && (primary != bus->number) && secondary && subordinate) {
1275 0 : pci_warn(dev, "Primary bus is hard wired to 0\n");
1276 0 : primary = bus->number;
1277 : }
1278 :
1279 : /* Check if setup is sensible at all */
1280 0 : if (!pass &&
1281 0 : (primary != bus->number || secondary <= bus->number ||
1282 : secondary > subordinate)) {
1283 0 : pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1284 : secondary, subordinate);
1285 0 : broken = 1;
1286 : }
1287 :
1288 : /*
1289 : * Disable Master-Abort Mode during probing to avoid reporting of
1290 : * bus errors in some architectures.
1291 : */
1292 0 : pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1293 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1294 0 : bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1295 :
1296 0 : pci_enable_crs(dev);
1297 :
1298 : if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1299 : !is_cardbus && !broken) {
1300 : unsigned int cmax;
1301 :
1302 : /*
1303 : * Bus already configured by firmware, process it in the
1304 : * first pass and just note the configuration.
1305 : */
1306 : if (pass)
1307 : goto out;
1308 :
1309 : /*
1310 : * The bus might already exist for two reasons: Either we
1311 : * are rescanning the bus or the bus is reachable through
1312 : * more than one bridge. The second case can happen with
1313 : * the i450NX chipset.
1314 : */
1315 : child = pci_find_bus(pci_domain_nr(bus), secondary);
1316 : if (!child) {
1317 : child = pci_add_new_bus(bus, dev, secondary);
1318 : if (!child)
1319 : goto out;
1320 : child->primary = primary;
1321 : pci_bus_insert_busn_res(child, secondary, subordinate);
1322 : child->bridge_ctl = bctl;
1323 : }
1324 :
1325 : cmax = pci_scan_child_bus(child);
1326 : if (cmax > subordinate)
1327 : pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1328 : subordinate, cmax);
1329 :
1330 : /* Subordinate should equal child->busn_res.end */
1331 : if (subordinate > max)
1332 : max = subordinate;
1333 : } else {
1334 :
1335 : /*
1336 : * We need to assign a number to this bus which we always
1337 : * do in the second pass.
1338 : */
1339 0 : if (!pass) {
1340 : if (pcibios_assign_all_busses() || broken || is_cardbus)
1341 :
1342 : /*
1343 : * Temporarily disable forwarding of the
1344 : * configuration cycles on all bridges in
1345 : * this bus segment to avoid possible
1346 : * conflicts in the second pass between two
1347 : * bridges programmed with overlapping bus
1348 : * ranges.
1349 : */
1350 0 : pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1351 : buses & ~0xffffff);
1352 0 : goto out;
1353 : }
1354 :
1355 : /* Clear errors */
1356 0 : pci_write_config_word(dev, PCI_STATUS, 0xffff);
1357 :
1358 : /* Read bus numbers from EA Capability (if present) */
1359 0 : fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1360 0 : if (fixed_buses)
1361 0 : next_busnr = fixed_sec;
1362 : else
1363 0 : next_busnr = max + 1;
1364 :
1365 : /*
1366 : * Prevent assigning a bus number that already exists.
1367 : * This can happen when a bridge is hot-plugged, so in this
1368 : * case we only re-scan this bus.
1369 : */
1370 0 : child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1371 0 : if (!child) {
1372 0 : child = pci_add_new_bus(bus, dev, next_busnr);
1373 0 : if (!child)
1374 : goto out;
1375 0 : pci_bus_insert_busn_res(child, next_busnr,
1376 0 : bus->busn_res.end);
1377 : }
1378 0 : max++;
1379 0 : if (available_buses)
1380 0 : available_buses--;
1381 :
1382 0 : buses = (buses & 0xff000000)
1383 0 : | ((unsigned int)(child->primary) << 0)
1384 0 : | ((unsigned int)(child->busn_res.start) << 8)
1385 0 : | ((unsigned int)(child->busn_res.end) << 16);
1386 :
1387 : /*
1388 : * yenta.c forces a secondary latency timer of 176.
1389 : * Copy that behaviour here.
1390 : */
1391 0 : if (is_cardbus) {
1392 0 : buses &= ~0xff000000;
1393 0 : buses |= CARDBUS_LATENCY_TIMER << 24;
1394 : }
1395 :
1396 : /* We need to blast all three values with a single write */
1397 0 : pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1398 :
1399 0 : if (!is_cardbus) {
1400 0 : child->bridge_ctl = bctl;
1401 0 : max = pci_scan_child_bus_extend(child, available_buses);
1402 : } else {
1403 :
1404 : /*
1405 : * For CardBus bridges, we leave 4 bus numbers as
1406 : * cards with a PCI-to-PCI bridge can be inserted
1407 : * later.
1408 : */
1409 0 : for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1410 0 : struct pci_bus *parent = bus;
1411 0 : if (pci_find_bus(pci_domain_nr(bus),
1412 0 : max+i+1))
1413 : break;
1414 0 : while (parent->parent) {
1415 : if ((!pcibios_assign_all_busses()) &&
1416 : (parent->busn_res.end > max) &&
1417 : (parent->busn_res.end <= max+i)) {
1418 : j = 1;
1419 : }
1420 : parent = parent->parent;
1421 : }
1422 : if (j) {
1423 :
1424 : /*
1425 : * Often, there are two CardBus
1426 : * bridges -- try to leave one
1427 : * valid bus number for each one.
1428 : */
1429 : i /= 2;
1430 : break;
1431 : }
1432 : }
1433 0 : max += i;
1434 : }
1435 :
1436 : /*
1437 : * Set subordinate bus number to its real value.
1438 : * If fixed subordinate bus number exists from EA
1439 : * capability then use it.
1440 : */
1441 0 : if (fixed_buses)
1442 0 : max = fixed_sub;
1443 0 : pci_bus_update_busn_res_end(child, max);
1444 0 : pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1445 : }
1446 :
1447 0 : sprintf(child->name,
1448 : (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1449 0 : pci_domain_nr(bus), child->number);
1450 :
1451 : /* Check that all devices are accessible */
1452 0 : while (bus->parent) {
1453 0 : if ((child->busn_res.end > bus->busn_res.end) ||
1454 0 : (child->number > bus->busn_res.end) ||
1455 0 : (child->number < bus->number) ||
1456 0 : (child->busn_res.end < bus->number)) {
1457 0 : dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1458 : &child->busn_res);
1459 0 : break;
1460 : }
1461 : bus = bus->parent;
1462 : }
1463 :
1464 : out:
1465 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1466 :
1467 0 : pm_runtime_put(&dev->dev);
1468 :
1469 0 : return max;
1470 : }
1471 :
1472 : /*
1473 : * pci_scan_bridge() - Scan buses behind a bridge
1474 : * @bus: Parent bus the bridge is on
1475 : * @dev: Bridge itself
1476 : * @max: Starting subordinate number of buses behind this bridge
1477 : * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1478 : * that need to be reconfigured.
1479 : *
1480 : * If it's a bridge, configure it and scan the bus behind it.
1481 : * For CardBus bridges, we don't scan behind as the devices will
1482 : * be handled by the bridge driver itself.
1483 : *
1484 : * We need to process bridges in two passes -- first we scan those
1485 : * already configured by the BIOS and after we are done with all of
1486 : * them, we proceed to assigning numbers to the remaining buses in
1487 : * order to avoid overlaps between old and new bus numbers.
1488 : *
1489 : * Return: New subordinate number covering all buses behind this bridge.
1490 : */
1491 0 : int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1492 : {
1493 0 : return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1494 : }
1495 : EXPORT_SYMBOL(pci_scan_bridge);
1496 :
1497 : /*
1498 : * Read interrupt line and base address registers.
1499 : * The architecture-dependent code can tweak these, of course.
1500 : */
1501 0 : static void pci_read_irq(struct pci_dev *dev)
1502 : {
1503 : unsigned char irq;
1504 :
1505 : /* VFs are not allowed to use INTx, so skip the config reads */
1506 0 : if (dev->is_virtfn) {
1507 0 : dev->pin = 0;
1508 0 : dev->irq = 0;
1509 0 : return;
1510 : }
1511 :
1512 0 : pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1513 0 : dev->pin = irq;
1514 0 : if (irq)
1515 0 : pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1516 0 : dev->irq = irq;
1517 : }
1518 :
1519 0 : void set_pcie_port_type(struct pci_dev *pdev)
1520 : {
1521 : int pos;
1522 : u16 reg16;
1523 : int type;
1524 : struct pci_dev *parent;
1525 :
1526 0 : pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1527 0 : if (!pos)
1528 0 : return;
1529 :
1530 0 : pdev->pcie_cap = pos;
1531 0 : pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1532 0 : pdev->pcie_flags_reg = reg16;
1533 0 : pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1534 0 : pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1535 :
1536 0 : parent = pci_upstream_bridge(pdev);
1537 0 : if (!parent)
1538 : return;
1539 :
1540 : /*
1541 : * Some systems do not identify their upstream/downstream ports
1542 : * correctly so detect impossible configurations here and correct
1543 : * the port type accordingly.
1544 : */
1545 0 : type = pci_pcie_type(pdev);
1546 0 : if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1547 : /*
1548 : * If pdev claims to be downstream port but the parent
1549 : * device is also downstream port assume pdev is actually
1550 : * upstream port.
1551 : */
1552 0 : if (pcie_downstream_port(parent)) {
1553 0 : pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1554 0 : pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1555 0 : pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1556 : }
1557 0 : } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1558 : /*
1559 : * If pdev claims to be upstream port but the parent
1560 : * device is also upstream port assume pdev is actually
1561 : * downstream port.
1562 : */
1563 0 : if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1564 0 : pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1565 0 : pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1566 0 : pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1567 : }
1568 : }
1569 : }
1570 :
1571 0 : void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1572 : {
1573 : u32 reg32;
1574 :
1575 0 : pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1576 0 : if (reg32 & PCI_EXP_SLTCAP_HPC)
1577 0 : pdev->is_hotplug_bridge = 1;
1578 0 : }
1579 :
1580 : static void set_pcie_thunderbolt(struct pci_dev *dev)
1581 : {
1582 : u16 vsec;
1583 :
1584 : /* Is the device part of a Thunderbolt controller? */
1585 0 : vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);
1586 0 : if (vsec)
1587 0 : dev->is_thunderbolt = 1;
1588 : }
1589 :
1590 : static void set_pcie_untrusted(struct pci_dev *dev)
1591 : {
1592 : struct pci_dev *parent;
1593 :
1594 : /*
1595 : * If the upstream bridge is untrusted we treat this device
1596 : * untrusted as well.
1597 : */
1598 0 : parent = pci_upstream_bridge(dev);
1599 0 : if (parent && (parent->untrusted || parent->external_facing))
1600 0 : dev->untrusted = true;
1601 : }
1602 :
1603 : static void pci_set_removable(struct pci_dev *dev)
1604 : {
1605 0 : struct pci_dev *parent = pci_upstream_bridge(dev);
1606 :
1607 : /*
1608 : * We (only) consider everything downstream from an external_facing
1609 : * device to be removable by the user. We're mainly concerned with
1610 : * consumer platforms with user accessible thunderbolt ports that are
1611 : * vulnerable to DMA attacks, and we expect those ports to be marked by
1612 : * the firmware as external_facing. Devices in traditional hotplug
1613 : * slots can technically be removed, but the expectation is that unless
1614 : * the port is marked with external_facing, such devices are less
1615 : * accessible to user / may not be removed by end user, and thus not
1616 : * exposed as "removable" to userspace.
1617 : */
1618 0 : if (parent &&
1619 0 : (parent->external_facing || dev_is_removable(&parent->dev)))
1620 0 : dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1621 : }
1622 :
1623 : /**
1624 : * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1625 : * @dev: PCI device
1626 : *
1627 : * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1628 : * when forwarding a type1 configuration request the bridge must check that
1629 : * the extended register address field is zero. The bridge is not permitted
1630 : * to forward the transactions and must handle it as an Unsupported Request.
1631 : * Some bridges do not follow this rule and simply drop the extended register
1632 : * bits, resulting in the standard config space being aliased, every 256
1633 : * bytes across the entire configuration space. Test for this condition by
1634 : * comparing the first dword of each potential alias to the vendor/device ID.
1635 : * Known offenders:
1636 : * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1637 : * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1638 : */
1639 0 : static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1640 : {
1641 : #ifdef CONFIG_PCI_QUIRKS
1642 : int pos;
1643 : u32 header, tmp;
1644 :
1645 0 : pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1646 :
1647 0 : for (pos = PCI_CFG_SPACE_SIZE;
1648 0 : pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1649 0 : if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1650 0 : || header != tmp)
1651 : return false;
1652 : }
1653 :
1654 : return true;
1655 : #else
1656 : return false;
1657 : #endif
1658 : }
1659 :
1660 : /**
1661 : * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1662 : * @dev: PCI device
1663 : *
1664 : * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1665 : * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1666 : * access it. Maybe we don't have a way to generate extended config space
1667 : * accesses, or the device is behind a reverse Express bridge. So we try
1668 : * reading the dword at 0x100 which must either be 0 or a valid extended
1669 : * capability header.
1670 : */
1671 0 : static int pci_cfg_space_size_ext(struct pci_dev *dev)
1672 : {
1673 : u32 status;
1674 0 : int pos = PCI_CFG_SPACE_SIZE;
1675 :
1676 0 : if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1677 : return PCI_CFG_SPACE_SIZE;
1678 0 : if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
1679 : return PCI_CFG_SPACE_SIZE;
1680 :
1681 : return PCI_CFG_SPACE_EXP_SIZE;
1682 : }
1683 :
1684 0 : int pci_cfg_space_size(struct pci_dev *dev)
1685 : {
1686 : int pos;
1687 : u32 status;
1688 : u16 class;
1689 :
1690 : #ifdef CONFIG_PCI_IOV
1691 : /*
1692 : * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1693 : * implement a PCIe capability and therefore must implement extended
1694 : * config space. We can skip the NO_EXTCFG test below and the
1695 : * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1696 : * the fact that the SR-IOV capability on the PF resides in extended
1697 : * config space and must be accessible and non-aliased to have enabled
1698 : * support for this VF. This is a micro performance optimization for
1699 : * systems supporting many VFs.
1700 : */
1701 : if (dev->is_virtfn)
1702 : return PCI_CFG_SPACE_EXP_SIZE;
1703 : #endif
1704 :
1705 0 : if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1706 : return PCI_CFG_SPACE_SIZE;
1707 :
1708 0 : class = dev->class >> 8;
1709 0 : if (class == PCI_CLASS_BRIDGE_HOST)
1710 0 : return pci_cfg_space_size_ext(dev);
1711 :
1712 0 : if (pci_is_pcie(dev))
1713 0 : return pci_cfg_space_size_ext(dev);
1714 :
1715 0 : pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1716 0 : if (!pos)
1717 : return PCI_CFG_SPACE_SIZE;
1718 :
1719 0 : pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1720 0 : if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1721 0 : return pci_cfg_space_size_ext(dev);
1722 :
1723 : return PCI_CFG_SPACE_SIZE;
1724 : }
1725 :
1726 : static u32 pci_class(struct pci_dev *dev)
1727 : {
1728 : u32 class;
1729 :
1730 : #ifdef CONFIG_PCI_IOV
1731 : if (dev->is_virtfn)
1732 : return dev->physfn->sriov->class;
1733 : #endif
1734 0 : pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1735 0 : return class;
1736 : }
1737 :
1738 : static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1739 : {
1740 : #ifdef CONFIG_PCI_IOV
1741 : if (dev->is_virtfn) {
1742 : *vendor = dev->physfn->sriov->subsystem_vendor;
1743 : *device = dev->physfn->sriov->subsystem_device;
1744 : return;
1745 : }
1746 : #endif
1747 0 : pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1748 0 : pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1749 : }
1750 :
1751 : static u8 pci_hdr_type(struct pci_dev *dev)
1752 : {
1753 : u8 hdr_type;
1754 :
1755 : #ifdef CONFIG_PCI_IOV
1756 : if (dev->is_virtfn)
1757 : return dev->physfn->sriov->hdr_type;
1758 : #endif
1759 0 : pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1760 0 : return hdr_type;
1761 : }
1762 :
1763 : #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1764 :
1765 : /**
1766 : * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1767 : * @dev: PCI device
1768 : *
1769 : * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1770 : * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1771 : */
1772 0 : static int pci_intx_mask_broken(struct pci_dev *dev)
1773 : {
1774 : u16 orig, toggle, new;
1775 :
1776 0 : pci_read_config_word(dev, PCI_COMMAND, &orig);
1777 0 : toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1778 0 : pci_write_config_word(dev, PCI_COMMAND, toggle);
1779 0 : pci_read_config_word(dev, PCI_COMMAND, &new);
1780 :
1781 0 : pci_write_config_word(dev, PCI_COMMAND, orig);
1782 :
1783 : /*
1784 : * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1785 : * r2.3, so strictly speaking, a device is not *broken* if it's not
1786 : * writable. But we'll live with the misnomer for now.
1787 : */
1788 0 : if (new != toggle)
1789 : return 1;
1790 0 : return 0;
1791 : }
1792 :
1793 0 : static void early_dump_pci_device(struct pci_dev *pdev)
1794 : {
1795 : u32 value[256 / 4];
1796 : int i;
1797 :
1798 0 : pci_info(pdev, "config space:\n");
1799 :
1800 0 : for (i = 0; i < 256; i += 4)
1801 0 : pci_read_config_dword(pdev, i, &value[i / 4]);
1802 :
1803 0 : print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1804 : value, 256, false);
1805 0 : }
1806 :
1807 : /**
1808 : * pci_setup_device - Fill in class and map information of a device
1809 : * @dev: the device structure to fill
1810 : *
1811 : * Initialize the device structure with information about the device's
1812 : * vendor,class,memory and IO-space addresses, IRQ lines etc.
1813 : * Called at initialisation of the PCI subsystem and by CardBus services.
1814 : * Returns 0 on success and negative if unknown type of device (not normal,
1815 : * bridge or CardBus).
1816 : */
1817 0 : int pci_setup_device(struct pci_dev *dev)
1818 : {
1819 : u32 class;
1820 : u16 cmd;
1821 : u8 hdr_type;
1822 0 : int pos = 0;
1823 : struct pci_bus_region region;
1824 : struct resource *res;
1825 :
1826 0 : hdr_type = pci_hdr_type(dev);
1827 :
1828 0 : dev->sysdata = dev->bus->sysdata;
1829 0 : dev->dev.parent = dev->bus->bridge;
1830 0 : dev->dev.bus = &pci_bus_type;
1831 0 : dev->hdr_type = hdr_type & 0x7f;
1832 0 : dev->multifunction = !!(hdr_type & 0x80);
1833 0 : dev->error_state = pci_channel_io_normal;
1834 0 : set_pcie_port_type(dev);
1835 :
1836 0 : pci_set_of_node(dev);
1837 0 : pci_set_acpi_fwnode(dev);
1838 :
1839 0 : pci_dev_assign_slot(dev);
1840 :
1841 : /*
1842 : * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1843 : * set this higher, assuming the system even supports it.
1844 : */
1845 0 : dev->dma_mask = 0xffffffff;
1846 :
1847 0 : dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1848 0 : dev->bus->number, PCI_SLOT(dev->devfn),
1849 0 : PCI_FUNC(dev->devfn));
1850 :
1851 0 : class = pci_class(dev);
1852 :
1853 0 : dev->revision = class & 0xff;
1854 0 : dev->class = class >> 8; /* upper 3 bytes */
1855 :
1856 0 : if (pci_early_dump)
1857 0 : early_dump_pci_device(dev);
1858 :
1859 : /* Need to have dev->class ready */
1860 0 : dev->cfg_size = pci_cfg_space_size(dev);
1861 :
1862 : /* Need to have dev->cfg_size ready */
1863 0 : set_pcie_thunderbolt(dev);
1864 :
1865 0 : set_pcie_untrusted(dev);
1866 :
1867 : /* "Unknown power state" */
1868 0 : dev->current_state = PCI_UNKNOWN;
1869 :
1870 : /* Early fixups, before probing the BARs */
1871 0 : pci_fixup_device(pci_fixup_early, dev);
1872 :
1873 0 : pci_set_removable(dev);
1874 :
1875 0 : pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1876 : dev->vendor, dev->device, dev->hdr_type, dev->class);
1877 :
1878 : /* Device class may be changed after fixup */
1879 0 : class = dev->class >> 8;
1880 :
1881 0 : if (dev->non_compliant_bars && !dev->mmio_always_on) {
1882 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
1883 0 : if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1884 0 : pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1885 0 : cmd &= ~PCI_COMMAND_IO;
1886 0 : cmd &= ~PCI_COMMAND_MEMORY;
1887 0 : pci_write_config_word(dev, PCI_COMMAND, cmd);
1888 : }
1889 : }
1890 :
1891 0 : dev->broken_intx_masking = pci_intx_mask_broken(dev);
1892 :
1893 0 : switch (dev->hdr_type) { /* header type */
1894 : case PCI_HEADER_TYPE_NORMAL: /* standard header */
1895 0 : if (class == PCI_CLASS_BRIDGE_PCI)
1896 : goto bad;
1897 0 : pci_read_irq(dev);
1898 0 : pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1899 :
1900 0 : pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1901 :
1902 : /*
1903 : * Do the ugly legacy mode stuff here rather than broken chip
1904 : * quirk code. Legacy mode ATA controllers have fixed
1905 : * addresses. These are not always echoed in BAR0-3, and
1906 : * BAR0-3 in a few cases contain junk!
1907 : */
1908 0 : if (class == PCI_CLASS_STORAGE_IDE) {
1909 : u8 progif;
1910 0 : pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1911 0 : if ((progif & 1) == 0) {
1912 0 : region.start = 0x1F0;
1913 0 : region.end = 0x1F7;
1914 0 : res = &dev->resource[0];
1915 0 : res->flags = LEGACY_IO_RESOURCE;
1916 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
1917 0 : pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1918 : res);
1919 0 : region.start = 0x3F6;
1920 0 : region.end = 0x3F6;
1921 0 : res = &dev->resource[1];
1922 0 : res->flags = LEGACY_IO_RESOURCE;
1923 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
1924 0 : pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1925 : res);
1926 : }
1927 0 : if ((progif & 4) == 0) {
1928 0 : region.start = 0x170;
1929 0 : region.end = 0x177;
1930 0 : res = &dev->resource[2];
1931 0 : res->flags = LEGACY_IO_RESOURCE;
1932 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
1933 0 : pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1934 : res);
1935 0 : region.start = 0x376;
1936 0 : region.end = 0x376;
1937 0 : res = &dev->resource[3];
1938 0 : res->flags = LEGACY_IO_RESOURCE;
1939 0 : pcibios_bus_to_resource(dev->bus, res, ®ion);
1940 0 : pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1941 : res);
1942 : }
1943 : }
1944 : break;
1945 :
1946 : case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1947 : /*
1948 : * The PCI-to-PCI bridge spec requires that subtractive
1949 : * decoding (i.e. transparent) bridge must have programming
1950 : * interface code of 0x01.
1951 : */
1952 0 : pci_read_irq(dev);
1953 0 : dev->transparent = ((dev->class & 0xff) == 1);
1954 0 : pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1955 0 : pci_read_bridge_windows(dev);
1956 0 : set_pcie_hotplug_bridge(dev);
1957 0 : pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1958 0 : if (pos) {
1959 0 : pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1960 0 : pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1961 : }
1962 : break;
1963 :
1964 : case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1965 0 : if (class != PCI_CLASS_BRIDGE_CARDBUS)
1966 : goto bad;
1967 0 : pci_read_irq(dev);
1968 0 : pci_read_bases(dev, 1, 0);
1969 0 : pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1970 0 : pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1971 0 : break;
1972 :
1973 : default: /* unknown header */
1974 0 : pci_err(dev, "unknown header type %02x, ignoring device\n",
1975 : dev->hdr_type);
1976 0 : pci_release_of_node(dev);
1977 0 : return -EIO;
1978 :
1979 : bad:
1980 0 : pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1981 : dev->class, dev->hdr_type);
1982 0 : dev->class = PCI_CLASS_NOT_DEFINED << 8;
1983 : }
1984 :
1985 : /* We found a fine healthy device, go go go... */
1986 : return 0;
1987 : }
1988 :
1989 0 : static void pci_configure_mps(struct pci_dev *dev)
1990 : {
1991 0 : struct pci_dev *bridge = pci_upstream_bridge(dev);
1992 : int mps, mpss, p_mps, rc;
1993 :
1994 0 : if (!pci_is_pcie(dev))
1995 : return;
1996 :
1997 : /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1998 0 : if (dev->is_virtfn)
1999 : return;
2000 :
2001 : /*
2002 : * For Root Complex Integrated Endpoints, program the maximum
2003 : * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2004 : */
2005 0 : if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
2006 0 : if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2007 : mps = 128;
2008 : else
2009 0 : mps = 128 << dev->pcie_mpss;
2010 0 : rc = pcie_set_mps(dev, mps);
2011 0 : if (rc) {
2012 0 : pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2013 : mps);
2014 : }
2015 : return;
2016 : }
2017 :
2018 0 : if (!bridge || !pci_is_pcie(bridge))
2019 : return;
2020 :
2021 0 : mps = pcie_get_mps(dev);
2022 0 : p_mps = pcie_get_mps(bridge);
2023 :
2024 0 : if (mps == p_mps)
2025 : return;
2026 :
2027 0 : if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
2028 0 : pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2029 : mps, pci_name(bridge), p_mps);
2030 0 : return;
2031 : }
2032 :
2033 : /*
2034 : * Fancier MPS configuration is done later by
2035 : * pcie_bus_configure_settings()
2036 : */
2037 0 : if (pcie_bus_config != PCIE_BUS_DEFAULT)
2038 : return;
2039 :
2040 0 : mpss = 128 << dev->pcie_mpss;
2041 0 : if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2042 0 : pcie_set_mps(bridge, mpss);
2043 0 : pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2044 : mpss, p_mps, 128 << bridge->pcie_mpss);
2045 0 : p_mps = pcie_get_mps(bridge);
2046 : }
2047 :
2048 0 : rc = pcie_set_mps(dev, p_mps);
2049 0 : if (rc) {
2050 0 : pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2051 : p_mps);
2052 0 : return;
2053 : }
2054 :
2055 0 : pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2056 : p_mps, mps, mpss);
2057 : }
2058 :
2059 0 : int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2060 : {
2061 : struct pci_host_bridge *host;
2062 : u32 cap;
2063 : u16 ctl;
2064 : int ret;
2065 :
2066 0 : if (!pci_is_pcie(dev))
2067 : return 0;
2068 :
2069 0 : ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2070 0 : if (ret)
2071 : return 0;
2072 :
2073 0 : if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2074 : return 0;
2075 :
2076 0 : ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2077 0 : if (ret)
2078 : return 0;
2079 :
2080 0 : host = pci_find_host_bridge(dev->bus);
2081 0 : if (!host)
2082 : return 0;
2083 :
2084 : /*
2085 : * If some device in the hierarchy doesn't handle Extended Tags
2086 : * correctly, make sure they're disabled.
2087 : */
2088 0 : if (host->no_ext_tags) {
2089 0 : if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2090 0 : pci_info(dev, "disabling Extended Tags\n");
2091 : pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2092 : PCI_EXP_DEVCTL_EXT_TAG);
2093 : }
2094 : return 0;
2095 : }
2096 :
2097 0 : if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2098 0 : pci_info(dev, "enabling Extended Tags\n");
2099 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2100 : PCI_EXP_DEVCTL_EXT_TAG);
2101 : }
2102 : return 0;
2103 : }
2104 :
2105 : /**
2106 : * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2107 : * @dev: PCI device to query
2108 : *
2109 : * Returns true if the device has enabled relaxed ordering attribute.
2110 : */
2111 0 : bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2112 : {
2113 : u16 v;
2114 :
2115 0 : pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2116 :
2117 0 : return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2118 : }
2119 : EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2120 :
2121 0 : static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2122 : {
2123 : struct pci_dev *root;
2124 :
2125 : /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2126 0 : if (dev->is_virtfn)
2127 : return;
2128 :
2129 0 : if (!pcie_relaxed_ordering_enabled(dev))
2130 : return;
2131 :
2132 : /*
2133 : * For now, we only deal with Relaxed Ordering issues with Root
2134 : * Ports. Peer-to-Peer DMA is another can of worms.
2135 : */
2136 0 : root = pcie_find_root_port(dev);
2137 0 : if (!root)
2138 : return;
2139 :
2140 0 : if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2141 0 : pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2142 : PCI_EXP_DEVCTL_RELAX_EN);
2143 0 : pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2144 : }
2145 : }
2146 :
2147 0 : static void pci_configure_ltr(struct pci_dev *dev)
2148 : {
2149 : #ifdef CONFIG_PCIEASPM
2150 0 : struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2151 : struct pci_dev *bridge;
2152 : u32 cap, ctl;
2153 :
2154 0 : if (!pci_is_pcie(dev))
2155 0 : return;
2156 :
2157 : /* Read L1 PM substate capabilities */
2158 0 : dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2159 :
2160 0 : pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2161 0 : if (!(cap & PCI_EXP_DEVCAP2_LTR))
2162 : return;
2163 :
2164 0 : pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2165 0 : if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2166 0 : if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2167 0 : dev->ltr_path = 1;
2168 0 : return;
2169 : }
2170 :
2171 0 : bridge = pci_upstream_bridge(dev);
2172 0 : if (bridge && bridge->ltr_path)
2173 0 : dev->ltr_path = 1;
2174 :
2175 : return;
2176 : }
2177 :
2178 0 : if (!host->native_ltr)
2179 : return;
2180 :
2181 : /*
2182 : * Software must not enable LTR in an Endpoint unless the Root
2183 : * Complex and all intermediate Switches indicate support for LTR.
2184 : * PCIe r4.0, sec 6.18.
2185 : */
2186 0 : if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2187 0 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2188 : PCI_EXP_DEVCTL2_LTR_EN);
2189 0 : dev->ltr_path = 1;
2190 0 : return;
2191 : }
2192 :
2193 : /*
2194 : * If we're configuring a hot-added device, LTR was likely
2195 : * disabled in the upstream bridge, so re-enable it before enabling
2196 : * it in the new device.
2197 : */
2198 0 : bridge = pci_upstream_bridge(dev);
2199 0 : if (bridge && bridge->ltr_path) {
2200 0 : pci_bridge_reconfigure_ltr(dev);
2201 0 : pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2202 : PCI_EXP_DEVCTL2_LTR_EN);
2203 0 : dev->ltr_path = 1;
2204 : }
2205 : #endif
2206 : }
2207 :
2208 : static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2209 : {
2210 : #ifdef CONFIG_PCI_PASID
2211 : struct pci_dev *bridge;
2212 : int pcie_type;
2213 : u32 cap;
2214 :
2215 : if (!pci_is_pcie(dev))
2216 : return;
2217 :
2218 : pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2219 : if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2220 : return;
2221 :
2222 : pcie_type = pci_pcie_type(dev);
2223 : if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2224 : pcie_type == PCI_EXP_TYPE_RC_END)
2225 : dev->eetlp_prefix_path = 1;
2226 : else {
2227 : bridge = pci_upstream_bridge(dev);
2228 : if (bridge && bridge->eetlp_prefix_path)
2229 : dev->eetlp_prefix_path = 1;
2230 : }
2231 : #endif
2232 : }
2233 :
2234 0 : static void pci_configure_serr(struct pci_dev *dev)
2235 : {
2236 : u16 control;
2237 :
2238 0 : if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2239 :
2240 : /*
2241 : * A bridge will not forward ERR_ messages coming from an
2242 : * endpoint unless SERR# forwarding is enabled.
2243 : */
2244 0 : pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2245 0 : if (!(control & PCI_BRIDGE_CTL_SERR)) {
2246 0 : control |= PCI_BRIDGE_CTL_SERR;
2247 0 : pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2248 : }
2249 : }
2250 0 : }
2251 :
2252 0 : static void pci_configure_device(struct pci_dev *dev)
2253 : {
2254 0 : pci_configure_mps(dev);
2255 0 : pci_configure_extended_tags(dev, NULL);
2256 0 : pci_configure_relaxed_ordering(dev);
2257 0 : pci_configure_ltr(dev);
2258 0 : pci_configure_eetlp_prefix(dev);
2259 0 : pci_configure_serr(dev);
2260 :
2261 0 : pci_acpi_program_hp_params(dev);
2262 0 : }
2263 :
2264 : static void pci_release_capabilities(struct pci_dev *dev)
2265 : {
2266 0 : pci_aer_exit(dev);
2267 0 : pci_rcec_exit(dev);
2268 0 : pci_iov_release(dev);
2269 0 : pci_free_cap_save_buffers(dev);
2270 : }
2271 :
2272 : /**
2273 : * pci_release_dev - Free a PCI device structure when all users of it are
2274 : * finished
2275 : * @dev: device that's been disconnected
2276 : *
2277 : * Will be called only by the device core when all users of this PCI device are
2278 : * done.
2279 : */
2280 0 : static void pci_release_dev(struct device *dev)
2281 : {
2282 : struct pci_dev *pci_dev;
2283 :
2284 0 : pci_dev = to_pci_dev(dev);
2285 0 : pci_release_capabilities(pci_dev);
2286 0 : pci_release_of_node(pci_dev);
2287 0 : pcibios_release_device(pci_dev);
2288 0 : pci_bus_put(pci_dev->bus);
2289 0 : kfree(pci_dev->driver_override);
2290 0 : bitmap_free(pci_dev->dma_alias_mask);
2291 : dev_dbg(dev, "device released\n");
2292 0 : kfree(pci_dev);
2293 0 : }
2294 :
2295 0 : struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2296 : {
2297 : struct pci_dev *dev;
2298 :
2299 0 : dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2300 0 : if (!dev)
2301 : return NULL;
2302 :
2303 0 : INIT_LIST_HEAD(&dev->bus_list);
2304 0 : dev->dev.type = &pci_dev_type;
2305 0 : dev->bus = pci_bus_get(bus);
2306 : #ifdef CONFIG_PCI_MSI
2307 : raw_spin_lock_init(&dev->msi_lock);
2308 : #endif
2309 0 : return dev;
2310 : }
2311 : EXPORT_SYMBOL(pci_alloc_dev);
2312 :
2313 : static bool pci_bus_crs_vendor_id(u32 l)
2314 : {
2315 0 : return (l & 0xffff) == 0x0001;
2316 : }
2317 :
2318 0 : static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2319 : int timeout)
2320 : {
2321 0 : int delay = 1;
2322 :
2323 0 : if (!pci_bus_crs_vendor_id(*l))
2324 : return true; /* not a CRS completion */
2325 :
2326 0 : if (!timeout)
2327 : return false; /* CRS, but caller doesn't want to wait */
2328 :
2329 : /*
2330 : * We got the reserved Vendor ID that indicates a completion with
2331 : * Configuration Request Retry Status (CRS). Retry until we get a
2332 : * valid Vendor ID or we time out.
2333 : */
2334 0 : while (pci_bus_crs_vendor_id(*l)) {
2335 0 : if (delay > timeout) {
2336 0 : pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2337 : pci_domain_nr(bus), bus->number,
2338 : PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2339 :
2340 0 : return false;
2341 : }
2342 0 : if (delay >= 1000)
2343 0 : pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2344 : pci_domain_nr(bus), bus->number,
2345 : PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2346 :
2347 0 : msleep(delay);
2348 0 : delay *= 2;
2349 :
2350 0 : if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2351 : return false;
2352 : }
2353 :
2354 0 : if (delay >= 1000)
2355 0 : pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2356 : pci_domain_nr(bus), bus->number,
2357 : PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2358 :
2359 : return true;
2360 : }
2361 :
2362 0 : bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2363 : int timeout)
2364 : {
2365 0 : if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2366 : return false;
2367 :
2368 : /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
2369 0 : if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
2370 0 : *l == 0x0000ffff || *l == 0xffff0000)
2371 : return false;
2372 :
2373 0 : if (pci_bus_crs_vendor_id(*l))
2374 0 : return pci_bus_wait_crs(bus, devfn, l, timeout);
2375 :
2376 : return true;
2377 : }
2378 :
2379 0 : bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2380 : int timeout)
2381 : {
2382 : #ifdef CONFIG_PCI_QUIRKS
2383 0 : struct pci_dev *bridge = bus->self;
2384 :
2385 : /*
2386 : * Certain IDT switches have an issue where they improperly trigger
2387 : * ACS Source Validation errors on completions for config reads.
2388 : */
2389 0 : if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2390 : bridge->device == 0x80b5)
2391 0 : return pci_idt_bus_quirk(bus, devfn, l, timeout);
2392 : #endif
2393 :
2394 0 : return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2395 : }
2396 : EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2397 :
2398 : /*
2399 : * Read the config data for a PCI device, sanity-check it,
2400 : * and fill in the dev structure.
2401 : */
2402 0 : static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2403 : {
2404 : struct pci_dev *dev;
2405 : u32 l;
2406 :
2407 0 : if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2408 : return NULL;
2409 :
2410 0 : dev = pci_alloc_dev(bus);
2411 0 : if (!dev)
2412 : return NULL;
2413 :
2414 0 : dev->devfn = devfn;
2415 0 : dev->vendor = l & 0xffff;
2416 0 : dev->device = (l >> 16) & 0xffff;
2417 :
2418 0 : if (pci_setup_device(dev)) {
2419 0 : pci_bus_put(dev->bus);
2420 0 : kfree(dev);
2421 0 : return NULL;
2422 : }
2423 :
2424 : return dev;
2425 : }
2426 :
2427 0 : void pcie_report_downtraining(struct pci_dev *dev)
2428 : {
2429 0 : if (!pci_is_pcie(dev))
2430 : return;
2431 :
2432 : /* Look from the device up to avoid downstream ports with no devices */
2433 0 : if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2434 0 : (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2435 0 : (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2436 : return;
2437 :
2438 : /* Multi-function PCIe devices share the same link/status */
2439 0 : if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2440 : return;
2441 :
2442 : /* Print link status only if the device is constrained by the fabric */
2443 0 : __pcie_print_link_status(dev, false);
2444 : }
2445 :
2446 0 : static void pci_init_capabilities(struct pci_dev *dev)
2447 : {
2448 0 : pci_ea_init(dev); /* Enhanced Allocation */
2449 0 : pci_msi_init(dev); /* Disable MSI */
2450 0 : pci_msix_init(dev); /* Disable MSI-X */
2451 :
2452 : /* Buffers for saving PCIe and PCI-X capabilities */
2453 0 : pci_allocate_cap_save_buffers(dev);
2454 :
2455 0 : pci_pm_init(dev); /* Power Management */
2456 0 : pci_vpd_init(dev); /* Vital Product Data */
2457 0 : pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2458 0 : pci_iov_init(dev); /* Single Root I/O Virtualization */
2459 0 : pci_ats_init(dev); /* Address Translation Services */
2460 0 : pci_pri_init(dev); /* Page Request Interface */
2461 0 : pci_pasid_init(dev); /* Process Address Space ID */
2462 0 : pci_acs_init(dev); /* Access Control Services */
2463 0 : pci_ptm_init(dev); /* Precision Time Measurement */
2464 0 : pci_aer_init(dev); /* Advanced Error Reporting */
2465 0 : pci_dpc_init(dev); /* Downstream Port Containment */
2466 0 : pci_rcec_init(dev); /* Root Complex Event Collector */
2467 :
2468 0 : pcie_report_downtraining(dev);
2469 0 : pci_init_reset_methods(dev);
2470 0 : }
2471 :
2472 : /*
2473 : * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2474 : * devices. Firmware interfaces that can select the MSI domain on a
2475 : * per-device basis should be called from here.
2476 : */
2477 : static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2478 : {
2479 : struct irq_domain *d;
2480 :
2481 : /*
2482 : * If a domain has been set through the pcibios_device_add()
2483 : * callback, then this is the one (platform code knows best).
2484 : */
2485 0 : d = dev_get_msi_domain(&dev->dev);
2486 0 : if (d)
2487 : return d;
2488 :
2489 : /*
2490 : * Let's see if we have a firmware interface able to provide
2491 : * the domain.
2492 : */
2493 0 : d = pci_msi_get_device_domain(dev);
2494 0 : if (d)
2495 : return d;
2496 :
2497 : return NULL;
2498 : }
2499 :
2500 0 : static void pci_set_msi_domain(struct pci_dev *dev)
2501 : {
2502 : struct irq_domain *d;
2503 :
2504 : /*
2505 : * If the platform or firmware interfaces cannot supply a
2506 : * device-specific MSI domain, then inherit the default domain
2507 : * from the host bridge itself.
2508 : */
2509 0 : d = pci_dev_msi_domain(dev);
2510 0 : if (!d)
2511 0 : d = dev_get_msi_domain(&dev->bus->dev);
2512 :
2513 0 : dev_set_msi_domain(&dev->dev, d);
2514 0 : }
2515 :
2516 0 : void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2517 : {
2518 : int ret;
2519 :
2520 0 : pci_configure_device(dev);
2521 :
2522 0 : device_initialize(&dev->dev);
2523 0 : dev->dev.release = pci_release_dev;
2524 :
2525 0 : set_dev_node(&dev->dev, pcibus_to_node(bus));
2526 0 : dev->dev.dma_mask = &dev->dma_mask;
2527 0 : dev->dev.dma_parms = &dev->dma_parms;
2528 0 : dev->dev.coherent_dma_mask = 0xffffffffull;
2529 :
2530 0 : dma_set_max_seg_size(&dev->dev, 65536);
2531 0 : dma_set_seg_boundary(&dev->dev, 0xffffffff);
2532 :
2533 : /* Fix up broken headers */
2534 0 : pci_fixup_device(pci_fixup_header, dev);
2535 :
2536 0 : pci_reassigndev_resource_alignment(dev);
2537 :
2538 0 : dev->state_saved = false;
2539 :
2540 0 : pci_init_capabilities(dev);
2541 :
2542 : /*
2543 : * Add the device to our list of discovered devices
2544 : * and the bus list for fixup functions, etc.
2545 : */
2546 0 : down_write(&pci_bus_sem);
2547 0 : list_add_tail(&dev->bus_list, &bus->devices);
2548 0 : up_write(&pci_bus_sem);
2549 :
2550 0 : ret = pcibios_device_add(dev);
2551 0 : WARN_ON(ret < 0);
2552 :
2553 : /* Set up MSI IRQ domain */
2554 0 : pci_set_msi_domain(dev);
2555 :
2556 : /* Notifier could use PCI capabilities */
2557 0 : dev->match_driver = false;
2558 0 : ret = device_add(&dev->dev);
2559 0 : WARN_ON(ret < 0);
2560 0 : }
2561 :
2562 0 : struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2563 : {
2564 : struct pci_dev *dev;
2565 :
2566 0 : dev = pci_get_slot(bus, devfn);
2567 0 : if (dev) {
2568 0 : pci_dev_put(dev);
2569 0 : return dev;
2570 : }
2571 :
2572 0 : dev = pci_scan_device(bus, devfn);
2573 0 : if (!dev)
2574 : return NULL;
2575 :
2576 0 : pci_device_add(dev, bus);
2577 :
2578 0 : return dev;
2579 : }
2580 : EXPORT_SYMBOL(pci_scan_single_device);
2581 :
2582 0 : static unsigned int next_fn(struct pci_bus *bus, struct pci_dev *dev,
2583 : unsigned int fn)
2584 : {
2585 : int pos;
2586 0 : u16 cap = 0;
2587 : unsigned int next_fn;
2588 :
2589 0 : if (pci_ari_enabled(bus)) {
2590 0 : if (!dev)
2591 : return 0;
2592 0 : pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2593 0 : if (!pos)
2594 : return 0;
2595 :
2596 0 : pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2597 0 : next_fn = PCI_ARI_CAP_NFN(cap);
2598 0 : if (next_fn <= fn)
2599 : return 0; /* protect against malformed list */
2600 :
2601 0 : return next_fn;
2602 : }
2603 :
2604 : /* dev may be NULL for non-contiguous multifunction devices */
2605 0 : if (!dev || dev->multifunction)
2606 0 : return (fn + 1) % 8;
2607 :
2608 : return 0;
2609 : }
2610 :
2611 0 : static int only_one_child(struct pci_bus *bus)
2612 : {
2613 0 : struct pci_dev *bridge = bus->self;
2614 :
2615 : /*
2616 : * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2617 : * we scan for all possible devices, not just Device 0.
2618 : */
2619 0 : if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2620 : return 0;
2621 :
2622 : /*
2623 : * A PCIe Downstream Port normally leads to a Link with only Device
2624 : * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2625 : * only for Device 0 in that situation.
2626 : */
2627 0 : if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2628 : return 1;
2629 :
2630 : return 0;
2631 : }
2632 :
2633 : /**
2634 : * pci_scan_slot - Scan a PCI slot on a bus for devices
2635 : * @bus: PCI bus to scan
2636 : * @devfn: slot number to scan (must have zero function)
2637 : *
2638 : * Scan a PCI slot on the specified PCI bus for devices, adding
2639 : * discovered devices to the @bus->devices list. New devices
2640 : * will not have is_added set.
2641 : *
2642 : * Returns the number of new devices found.
2643 : */
2644 0 : int pci_scan_slot(struct pci_bus *bus, int devfn)
2645 : {
2646 0 : unsigned int fn, nr = 0;
2647 : struct pci_dev *dev;
2648 :
2649 0 : if (only_one_child(bus) && (devfn > 0))
2650 : return 0; /* Already scanned the entire slot */
2651 :
2652 0 : dev = pci_scan_single_device(bus, devfn);
2653 0 : if (!dev)
2654 : return 0;
2655 0 : if (!pci_dev_is_added(dev))
2656 0 : nr++;
2657 :
2658 0 : for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2659 0 : dev = pci_scan_single_device(bus, devfn + fn);
2660 0 : if (dev) {
2661 0 : if (!pci_dev_is_added(dev))
2662 0 : nr++;
2663 0 : dev->multifunction = 1;
2664 : }
2665 : }
2666 :
2667 : /* Only one slot has PCIe device */
2668 0 : if (bus->self && nr)
2669 0 : pcie_aspm_init_link_state(bus->self);
2670 :
2671 0 : return nr;
2672 : }
2673 : EXPORT_SYMBOL(pci_scan_slot);
2674 :
2675 0 : static int pcie_find_smpss(struct pci_dev *dev, void *data)
2676 : {
2677 0 : u8 *smpss = data;
2678 :
2679 0 : if (!pci_is_pcie(dev))
2680 : return 0;
2681 :
2682 : /*
2683 : * We don't have a way to change MPS settings on devices that have
2684 : * drivers attached. A hot-added device might support only the minimum
2685 : * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2686 : * where devices may be hot-added, we limit the fabric MPS to 128 so
2687 : * hot-added devices will work correctly.
2688 : *
2689 : * However, if we hot-add a device to a slot directly below a Root
2690 : * Port, it's impossible for there to be other existing devices below
2691 : * the port. We don't limit the MPS in this case because we can
2692 : * reconfigure MPS on both the Root Port and the hot-added device,
2693 : * and there are no other devices involved.
2694 : *
2695 : * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2696 : */
2697 0 : if (dev->is_hotplug_bridge &&
2698 0 : pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2699 0 : *smpss = 0;
2700 :
2701 0 : if (*smpss > dev->pcie_mpss)
2702 0 : *smpss = dev->pcie_mpss;
2703 :
2704 : return 0;
2705 : }
2706 :
2707 0 : static void pcie_write_mps(struct pci_dev *dev, int mps)
2708 : {
2709 : int rc;
2710 :
2711 0 : if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2712 0 : mps = 128 << dev->pcie_mpss;
2713 :
2714 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2715 0 : dev->bus->self)
2716 :
2717 : /*
2718 : * For "Performance", the assumption is made that
2719 : * downstream communication will never be larger than
2720 : * the MRRS. So, the MPS only needs to be configured
2721 : * for the upstream communication. This being the case,
2722 : * walk from the top down and set the MPS of the child
2723 : * to that of the parent bus.
2724 : *
2725 : * Configure the device MPS with the smaller of the
2726 : * device MPSS or the bridge MPS (which is assumed to be
2727 : * properly configured at this point to the largest
2728 : * allowable MPS based on its parent bus).
2729 : */
2730 0 : mps = min(mps, pcie_get_mps(dev->bus->self));
2731 : }
2732 :
2733 0 : rc = pcie_set_mps(dev, mps);
2734 0 : if (rc)
2735 0 : pci_err(dev, "Failed attempting to set the MPS\n");
2736 0 : }
2737 :
2738 0 : static void pcie_write_mrrs(struct pci_dev *dev)
2739 : {
2740 : int rc, mrrs;
2741 :
2742 : /*
2743 : * In the "safe" case, do not configure the MRRS. There appear to be
2744 : * issues with setting MRRS to 0 on a number of devices.
2745 : */
2746 0 : if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2747 : return;
2748 :
2749 : /*
2750 : * For max performance, the MRRS must be set to the largest supported
2751 : * value. However, it cannot be configured larger than the MPS the
2752 : * device or the bus can support. This should already be properly
2753 : * configured by a prior call to pcie_write_mps().
2754 : */
2755 0 : mrrs = pcie_get_mps(dev);
2756 :
2757 : /*
2758 : * MRRS is a R/W register. Invalid values can be written, but a
2759 : * subsequent read will verify if the value is acceptable or not.
2760 : * If the MRRS value provided is not acceptable (e.g., too large),
2761 : * shrink the value until it is acceptable to the HW.
2762 : */
2763 0 : while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2764 0 : rc = pcie_set_readrq(dev, mrrs);
2765 0 : if (!rc)
2766 : break;
2767 :
2768 0 : pci_warn(dev, "Failed attempting to set the MRRS\n");
2769 0 : mrrs /= 2;
2770 : }
2771 :
2772 0 : if (mrrs < 128)
2773 0 : pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2774 : }
2775 :
2776 0 : static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2777 : {
2778 : int mps, orig_mps;
2779 :
2780 0 : if (!pci_is_pcie(dev))
2781 : return 0;
2782 :
2783 0 : if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2784 : pcie_bus_config == PCIE_BUS_DEFAULT)
2785 : return 0;
2786 :
2787 0 : mps = 128 << *(u8 *)data;
2788 0 : orig_mps = pcie_get_mps(dev);
2789 :
2790 0 : pcie_write_mps(dev, mps);
2791 0 : pcie_write_mrrs(dev);
2792 :
2793 0 : pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2794 : pcie_get_mps(dev), 128 << dev->pcie_mpss,
2795 : orig_mps, pcie_get_readrq(dev));
2796 :
2797 0 : return 0;
2798 : }
2799 :
2800 : /*
2801 : * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2802 : * parents then children fashion. If this changes, then this code will not
2803 : * work as designed.
2804 : */
2805 0 : void pcie_bus_configure_settings(struct pci_bus *bus)
2806 : {
2807 0 : u8 smpss = 0;
2808 :
2809 0 : if (!bus->self)
2810 0 : return;
2811 :
2812 0 : if (!pci_is_pcie(bus->self))
2813 : return;
2814 :
2815 : /*
2816 : * FIXME - Peer to peer DMA is possible, though the endpoint would need
2817 : * to be aware of the MPS of the destination. To work around this,
2818 : * simply force the MPS of the entire system to the smallest possible.
2819 : */
2820 0 : if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2821 : smpss = 0;
2822 :
2823 0 : if (pcie_bus_config == PCIE_BUS_SAFE) {
2824 0 : smpss = bus->self->pcie_mpss;
2825 :
2826 0 : pcie_find_smpss(bus->self, &smpss);
2827 0 : pci_walk_bus(bus, pcie_find_smpss, &smpss);
2828 : }
2829 :
2830 0 : pcie_bus_configure_set(bus->self, &smpss);
2831 0 : pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2832 : }
2833 : EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2834 :
2835 : /*
2836 : * Called after each bus is probed, but before its children are examined. This
2837 : * is marked as __weak because multiple architectures define it.
2838 : */
2839 0 : void __weak pcibios_fixup_bus(struct pci_bus *bus)
2840 : {
2841 : /* nothing to do, expected to be removed in the future */
2842 0 : }
2843 :
2844 : /**
2845 : * pci_scan_child_bus_extend() - Scan devices below a bus
2846 : * @bus: Bus to scan for devices
2847 : * @available_buses: Total number of buses available (%0 does not try to
2848 : * extend beyond the minimal)
2849 : *
2850 : * Scans devices below @bus including subordinate buses. Returns new
2851 : * subordinate number including all the found devices. Passing
2852 : * @available_buses causes the remaining bus space to be distributed
2853 : * equally between hotplug-capable bridges to allow future extension of the
2854 : * hierarchy.
2855 : */
2856 0 : static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2857 : unsigned int available_buses)
2858 : {
2859 0 : unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2860 0 : unsigned int start = bus->busn_res.start;
2861 0 : unsigned int devfn, fn, cmax, max = start;
2862 : struct pci_dev *dev;
2863 : int nr_devs;
2864 :
2865 : dev_dbg(&bus->dev, "scanning bus\n");
2866 :
2867 : /* Go find them, Rover! */
2868 0 : for (devfn = 0; devfn < 256; devfn += 8) {
2869 0 : nr_devs = pci_scan_slot(bus, devfn);
2870 :
2871 : /*
2872 : * The Jailhouse hypervisor may pass individual functions of a
2873 : * multi-function device to a guest without passing function 0.
2874 : * Look for them as well.
2875 : */
2876 : if (jailhouse_paravirt() && nr_devs == 0) {
2877 : for (fn = 1; fn < 8; fn++) {
2878 : dev = pci_scan_single_device(bus, devfn + fn);
2879 : if (dev)
2880 : dev->multifunction = 1;
2881 : }
2882 : }
2883 : }
2884 :
2885 : /* Reserve buses for SR-IOV capability */
2886 0 : used_buses = pci_iov_bus_range(bus);
2887 0 : max += used_buses;
2888 :
2889 : /*
2890 : * After performing arch-dependent fixup of the bus, look behind
2891 : * all PCI-to-PCI bridges on this bus.
2892 : */
2893 0 : if (!bus->is_added) {
2894 : dev_dbg(&bus->dev, "fixups for bus\n");
2895 0 : pcibios_fixup_bus(bus);
2896 0 : bus->is_added = 1;
2897 : }
2898 :
2899 : /*
2900 : * Calculate how many hotplug bridges and normal bridges there
2901 : * are on this bus. We will distribute the additional available
2902 : * buses between hotplug bridges.
2903 : */
2904 0 : for_each_pci_bridge(dev, bus) {
2905 0 : if (dev->is_hotplug_bridge)
2906 0 : hotplug_bridges++;
2907 : else
2908 0 : normal_bridges++;
2909 : }
2910 :
2911 : /*
2912 : * Scan bridges that are already configured. We don't touch them
2913 : * unless they are misconfigured (which will be done in the second
2914 : * scan below).
2915 : */
2916 0 : for_each_pci_bridge(dev, bus) {
2917 0 : cmax = max;
2918 0 : max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2919 :
2920 : /*
2921 : * Reserve one bus for each bridge now to avoid extending
2922 : * hotplug bridges too much during the second scan below.
2923 : */
2924 0 : used_buses++;
2925 0 : if (cmax - max > 1)
2926 0 : used_buses += cmax - max - 1;
2927 : }
2928 :
2929 : /* Scan bridges that need to be reconfigured */
2930 0 : for_each_pci_bridge(dev, bus) {
2931 0 : unsigned int buses = 0;
2932 :
2933 0 : if (!hotplug_bridges && normal_bridges == 1) {
2934 :
2935 : /*
2936 : * There is only one bridge on the bus (upstream
2937 : * port) so it gets all available buses which it
2938 : * can then distribute to the possible hotplug
2939 : * bridges below.
2940 : */
2941 : buses = available_buses;
2942 0 : } else if (dev->is_hotplug_bridge) {
2943 :
2944 : /*
2945 : * Distribute the extra buses between hotplug
2946 : * bridges if any.
2947 : */
2948 0 : buses = available_buses / hotplug_bridges;
2949 0 : buses = min(buses, available_buses - used_buses + 1);
2950 : }
2951 :
2952 0 : cmax = max;
2953 0 : max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2954 : /* One bus is already accounted so don't add it again */
2955 0 : if (max - cmax > 1)
2956 0 : used_buses += max - cmax - 1;
2957 : }
2958 :
2959 : /*
2960 : * Make sure a hotplug bridge has at least the minimum requested
2961 : * number of buses but allow it to grow up to the maximum available
2962 : * bus number of there is room.
2963 : */
2964 0 : if (bus->self && bus->self->is_hotplug_bridge) {
2965 0 : used_buses = max_t(unsigned int, available_buses,
2966 : pci_hotplug_bus_size - 1);
2967 0 : if (max - start < used_buses) {
2968 0 : max = start + used_buses;
2969 :
2970 : /* Do not allocate more buses than we have room left */
2971 0 : if (max > bus->busn_res.end)
2972 0 : max = bus->busn_res.end;
2973 :
2974 : dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2975 : &bus->busn_res, max - start);
2976 : }
2977 : }
2978 :
2979 : /*
2980 : * We've scanned the bus and so we know all about what's on
2981 : * the other side of any bridges that may be on this bus plus
2982 : * any devices.
2983 : *
2984 : * Return how far we've got finding sub-buses.
2985 : */
2986 : dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2987 0 : return max;
2988 : }
2989 :
2990 : /**
2991 : * pci_scan_child_bus() - Scan devices below a bus
2992 : * @bus: Bus to scan for devices
2993 : *
2994 : * Scans devices below @bus including subordinate buses. Returns new
2995 : * subordinate number including all the found devices.
2996 : */
2997 0 : unsigned int pci_scan_child_bus(struct pci_bus *bus)
2998 : {
2999 0 : return pci_scan_child_bus_extend(bus, 0);
3000 : }
3001 : EXPORT_SYMBOL_GPL(pci_scan_child_bus);
3002 :
3003 : /**
3004 : * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3005 : * @bridge: Host bridge to set up
3006 : *
3007 : * Default empty implementation. Replace with an architecture-specific setup
3008 : * routine, if necessary.
3009 : */
3010 0 : int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3011 : {
3012 0 : return 0;
3013 : }
3014 :
3015 0 : void __weak pcibios_add_bus(struct pci_bus *bus)
3016 : {
3017 0 : }
3018 :
3019 0 : void __weak pcibios_remove_bus(struct pci_bus *bus)
3020 : {
3021 0 : }
3022 :
3023 0 : struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3024 : struct pci_ops *ops, void *sysdata, struct list_head *resources)
3025 : {
3026 : int error;
3027 : struct pci_host_bridge *bridge;
3028 :
3029 0 : bridge = pci_alloc_host_bridge(0);
3030 0 : if (!bridge)
3031 : return NULL;
3032 :
3033 0 : bridge->dev.parent = parent;
3034 :
3035 0 : list_splice_init(resources, &bridge->windows);
3036 0 : bridge->sysdata = sysdata;
3037 0 : bridge->busnr = bus;
3038 0 : bridge->ops = ops;
3039 :
3040 0 : error = pci_register_host_bridge(bridge);
3041 0 : if (error < 0)
3042 : goto err_out;
3043 :
3044 0 : return bridge->bus;
3045 :
3046 : err_out:
3047 0 : put_device(&bridge->dev);
3048 0 : return NULL;
3049 : }
3050 : EXPORT_SYMBOL_GPL(pci_create_root_bus);
3051 :
3052 0 : int pci_host_probe(struct pci_host_bridge *bridge)
3053 : {
3054 : struct pci_bus *bus, *child;
3055 : int ret;
3056 :
3057 0 : ret = pci_scan_root_bus_bridge(bridge);
3058 0 : if (ret < 0) {
3059 0 : dev_err(bridge->dev.parent, "Scanning root bridge failed");
3060 0 : return ret;
3061 : }
3062 :
3063 0 : bus = bridge->bus;
3064 :
3065 : /*
3066 : * We insert PCI resources into the iomem_resource and
3067 : * ioport_resource trees in either pci_bus_claim_resources()
3068 : * or pci_bus_assign_resources().
3069 : */
3070 0 : if (pci_has_flag(PCI_PROBE_ONLY)) {
3071 0 : pci_bus_claim_resources(bus);
3072 : } else {
3073 0 : pci_bus_size_bridges(bus);
3074 0 : pci_bus_assign_resources(bus);
3075 :
3076 0 : list_for_each_entry(child, &bus->children, node)
3077 0 : pcie_bus_configure_settings(child);
3078 : }
3079 :
3080 0 : pci_bus_add_devices(bus);
3081 0 : return 0;
3082 : }
3083 : EXPORT_SYMBOL_GPL(pci_host_probe);
3084 :
3085 0 : int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3086 : {
3087 0 : struct resource *res = &b->busn_res;
3088 : struct resource *parent_res, *conflict;
3089 :
3090 0 : res->start = bus;
3091 0 : res->end = bus_max;
3092 0 : res->flags = IORESOURCE_BUS;
3093 :
3094 0 : if (!pci_is_root_bus(b))
3095 0 : parent_res = &b->parent->busn_res;
3096 : else {
3097 0 : parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3098 0 : res->flags |= IORESOURCE_PCI_FIXED;
3099 : }
3100 :
3101 0 : conflict = request_resource_conflict(parent_res, res);
3102 :
3103 0 : if (conflict)
3104 0 : dev_info(&b->dev,
3105 : "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3106 : res, pci_is_root_bus(b) ? "domain " : "",
3107 : parent_res, conflict->name, conflict);
3108 :
3109 0 : return conflict == NULL;
3110 : }
3111 :
3112 0 : int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3113 : {
3114 0 : struct resource *res = &b->busn_res;
3115 0 : struct resource old_res = *res;
3116 : resource_size_t size;
3117 : int ret;
3118 :
3119 0 : if (res->start > bus_max)
3120 : return -EINVAL;
3121 :
3122 0 : size = bus_max - res->start + 1;
3123 0 : ret = adjust_resource(res, res->start, size);
3124 0 : dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3125 : &old_res, ret ? "can not be" : "is", bus_max);
3126 :
3127 0 : if (!ret && !res->parent)
3128 0 : pci_bus_insert_busn_res(b, res->start, res->end);
3129 :
3130 : return ret;
3131 : }
3132 :
3133 0 : void pci_bus_release_busn_res(struct pci_bus *b)
3134 : {
3135 0 : struct resource *res = &b->busn_res;
3136 : int ret;
3137 :
3138 0 : if (!res->flags || !res->parent)
3139 : return;
3140 :
3141 0 : ret = release_resource(res);
3142 0 : dev_info(&b->dev, "busn_res: %pR %s released\n",
3143 : res, ret ? "can not be" : "is");
3144 : }
3145 :
3146 0 : int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3147 : {
3148 : struct resource_entry *window;
3149 0 : bool found = false;
3150 : struct pci_bus *b;
3151 : int max, bus, ret;
3152 :
3153 0 : if (!bridge)
3154 : return -EINVAL;
3155 :
3156 0 : resource_list_for_each_entry(window, &bridge->windows)
3157 0 : if (window->res->flags & IORESOURCE_BUS) {
3158 0 : bridge->busnr = window->res->start;
3159 0 : found = true;
3160 0 : break;
3161 : }
3162 :
3163 0 : ret = pci_register_host_bridge(bridge);
3164 0 : if (ret < 0)
3165 : return ret;
3166 :
3167 0 : b = bridge->bus;
3168 0 : bus = bridge->busnr;
3169 :
3170 0 : if (!found) {
3171 0 : dev_info(&b->dev,
3172 : "No busn resource found for root bus, will use [bus %02x-ff]\n",
3173 : bus);
3174 0 : pci_bus_insert_busn_res(b, bus, 255);
3175 : }
3176 :
3177 0 : max = pci_scan_child_bus(b);
3178 :
3179 0 : if (!found)
3180 0 : pci_bus_update_busn_res_end(b, max);
3181 :
3182 : return 0;
3183 : }
3184 : EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3185 :
3186 0 : struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3187 : struct pci_ops *ops, void *sysdata, struct list_head *resources)
3188 : {
3189 : struct resource_entry *window;
3190 0 : bool found = false;
3191 : struct pci_bus *b;
3192 : int max;
3193 :
3194 0 : resource_list_for_each_entry(window, resources)
3195 0 : if (window->res->flags & IORESOURCE_BUS) {
3196 : found = true;
3197 : break;
3198 : }
3199 :
3200 0 : b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3201 0 : if (!b)
3202 : return NULL;
3203 :
3204 0 : if (!found) {
3205 0 : dev_info(&b->dev,
3206 : "No busn resource found for root bus, will use [bus %02x-ff]\n",
3207 : bus);
3208 0 : pci_bus_insert_busn_res(b, bus, 255);
3209 : }
3210 :
3211 0 : max = pci_scan_child_bus(b);
3212 :
3213 0 : if (!found)
3214 0 : pci_bus_update_busn_res_end(b, max);
3215 :
3216 : return b;
3217 : }
3218 : EXPORT_SYMBOL(pci_scan_root_bus);
3219 :
3220 0 : struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3221 : void *sysdata)
3222 : {
3223 0 : LIST_HEAD(resources);
3224 : struct pci_bus *b;
3225 :
3226 0 : pci_add_resource(&resources, &ioport_resource);
3227 0 : pci_add_resource(&resources, &iomem_resource);
3228 0 : pci_add_resource(&resources, &busn_resource);
3229 0 : b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3230 0 : if (b) {
3231 : pci_scan_child_bus(b);
3232 : } else {
3233 0 : pci_free_resource_list(&resources);
3234 : }
3235 0 : return b;
3236 : }
3237 : EXPORT_SYMBOL(pci_scan_bus);
3238 :
3239 : /**
3240 : * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3241 : * @bridge: PCI bridge for the bus to scan
3242 : *
3243 : * Scan a PCI bus and child buses for new devices, add them,
3244 : * and enable them, resizing bridge mmio/io resource if necessary
3245 : * and possible. The caller must ensure the child devices are already
3246 : * removed for resizing to occur.
3247 : *
3248 : * Returns the max number of subordinate bus discovered.
3249 : */
3250 0 : unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3251 : {
3252 : unsigned int max;
3253 0 : struct pci_bus *bus = bridge->subordinate;
3254 :
3255 0 : max = pci_scan_child_bus(bus);
3256 :
3257 0 : pci_assign_unassigned_bridge_resources(bridge);
3258 :
3259 0 : pci_bus_add_devices(bus);
3260 :
3261 0 : return max;
3262 : }
3263 :
3264 : /**
3265 : * pci_rescan_bus - Scan a PCI bus for devices
3266 : * @bus: PCI bus to scan
3267 : *
3268 : * Scan a PCI bus and child buses for new devices, add them,
3269 : * and enable them.
3270 : *
3271 : * Returns the max number of subordinate bus discovered.
3272 : */
3273 0 : unsigned int pci_rescan_bus(struct pci_bus *bus)
3274 : {
3275 : unsigned int max;
3276 :
3277 0 : max = pci_scan_child_bus(bus);
3278 0 : pci_assign_unassigned_bus_resources(bus);
3279 0 : pci_bus_add_devices(bus);
3280 :
3281 0 : return max;
3282 : }
3283 : EXPORT_SYMBOL_GPL(pci_rescan_bus);
3284 :
3285 : /*
3286 : * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3287 : * routines should always be executed under this mutex.
3288 : */
3289 : static DEFINE_MUTEX(pci_rescan_remove_lock);
3290 :
3291 0 : void pci_lock_rescan_remove(void)
3292 : {
3293 0 : mutex_lock(&pci_rescan_remove_lock);
3294 0 : }
3295 : EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3296 :
3297 0 : void pci_unlock_rescan_remove(void)
3298 : {
3299 0 : mutex_unlock(&pci_rescan_remove_lock);
3300 0 : }
3301 : EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3302 :
3303 0 : static int __init pci_sort_bf_cmp(const struct device *d_a,
3304 : const struct device *d_b)
3305 : {
3306 0 : const struct pci_dev *a = to_pci_dev(d_a);
3307 0 : const struct pci_dev *b = to_pci_dev(d_b);
3308 :
3309 0 : if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3310 0 : else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3311 :
3312 0 : if (a->bus->number < b->bus->number) return -1;
3313 0 : else if (a->bus->number > b->bus->number) return 1;
3314 :
3315 0 : if (a->devfn < b->devfn) return -1;
3316 0 : else if (a->devfn > b->devfn) return 1;
3317 :
3318 0 : return 0;
3319 : }
3320 :
3321 0 : void __init pci_sort_breadthfirst(void)
3322 : {
3323 0 : bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3324 0 : }
3325 :
3326 0 : int pci_hp_add_bridge(struct pci_dev *dev)
3327 : {
3328 0 : struct pci_bus *parent = dev->bus;
3329 0 : int busnr, start = parent->busn_res.start;
3330 0 : unsigned int available_buses = 0;
3331 0 : int end = parent->busn_res.end;
3332 :
3333 0 : for (busnr = start; busnr <= end; busnr++) {
3334 0 : if (!pci_find_bus(pci_domain_nr(parent), busnr))
3335 : break;
3336 : }
3337 0 : if (busnr-- > end) {
3338 0 : pci_err(dev, "No bus number available for hot-added bridge\n");
3339 0 : return -1;
3340 : }
3341 :
3342 : /* Scan bridges that are already configured */
3343 0 : busnr = pci_scan_bridge(parent, dev, busnr, 0);
3344 :
3345 : /*
3346 : * Distribute the available bus numbers between hotplug-capable
3347 : * bridges to make extending the chain later possible.
3348 : */
3349 0 : available_buses = end - busnr;
3350 :
3351 : /* Scan bridges that need to be reconfigured */
3352 0 : pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3353 :
3354 0 : if (!dev->subordinate)
3355 : return -1;
3356 :
3357 0 : return 0;
3358 : }
3359 : EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
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