Line data Source code
1 : // SPDX-License-Identifier: GPL-2.0
2 : /*
3 : * This file contains work-arounds for many known PCI hardware bugs.
4 : * Devices present only on certain architectures (host bridges et cetera)
5 : * should be handled in arch-specific code.
6 : *
7 : * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 : *
9 : * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 : *
11 : * Init/reset quirks for USB host controllers should be in the USB quirks
12 : * file, where their drivers can use them.
13 : */
14 :
15 : #include <linux/types.h>
16 : #include <linux/kernel.h>
17 : #include <linux/export.h>
18 : #include <linux/pci.h>
19 : #include <linux/init.h>
20 : #include <linux/delay.h>
21 : #include <linux/acpi.h>
22 : #include <linux/dmi.h>
23 : #include <linux/ioport.h>
24 : #include <linux/sched.h>
25 : #include <linux/ktime.h>
26 : #include <linux/mm.h>
27 : #include <linux/nvme.h>
28 : #include <linux/platform_data/x86/apple.h>
29 : #include <linux/pm_runtime.h>
30 : #include <linux/suspend.h>
31 : #include <linux/switchtec.h>
32 : #include <asm/dma.h> /* isa_dma_bridge_buggy */
33 : #include "pci.h"
34 :
35 0 : static ktime_t fixup_debug_start(struct pci_dev *dev,
36 : void (*fn)(struct pci_dev *dev))
37 : {
38 0 : if (initcall_debug)
39 0 : pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
40 :
41 0 : return ktime_get();
42 : }
43 :
44 0 : static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
45 : void (*fn)(struct pci_dev *dev))
46 : {
47 : ktime_t delta, rettime;
48 : unsigned long long duration;
49 :
50 0 : rettime = ktime_get();
51 0 : delta = ktime_sub(rettime, calltime);
52 0 : duration = (unsigned long long) ktime_to_ns(delta) >> 10;
53 0 : if (initcall_debug || duration > 10000)
54 0 : pci_info(dev, "%pS took %lld usecs\n", fn, duration);
55 0 : }
56 :
57 0 : static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
58 : struct pci_fixup *end)
59 : {
60 : ktime_t calltime;
61 :
62 0 : for (; f < end; f++)
63 0 : if ((f->class == (u32) (dev->class >> f->class_shift) ||
64 0 : f->class == (u32) PCI_ANY_ID) &&
65 0 : (f->vendor == dev->vendor ||
66 0 : f->vendor == (u16) PCI_ANY_ID) &&
67 0 : (f->device == dev->device ||
68 : f->device == (u16) PCI_ANY_ID)) {
69 : void (*hook)(struct pci_dev *dev);
70 : #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
71 : hook = offset_to_ptr(&f->hook_offset);
72 : #else
73 0 : hook = f->hook;
74 : #endif
75 0 : calltime = fixup_debug_start(dev, hook);
76 0 : hook(dev);
77 0 : fixup_debug_report(dev, calltime, hook);
78 : }
79 0 : }
80 :
81 : extern struct pci_fixup __start_pci_fixups_early[];
82 : extern struct pci_fixup __end_pci_fixups_early[];
83 : extern struct pci_fixup __start_pci_fixups_header[];
84 : extern struct pci_fixup __end_pci_fixups_header[];
85 : extern struct pci_fixup __start_pci_fixups_final[];
86 : extern struct pci_fixup __end_pci_fixups_final[];
87 : extern struct pci_fixup __start_pci_fixups_enable[];
88 : extern struct pci_fixup __end_pci_fixups_enable[];
89 : extern struct pci_fixup __start_pci_fixups_resume[];
90 : extern struct pci_fixup __end_pci_fixups_resume[];
91 : extern struct pci_fixup __start_pci_fixups_resume_early[];
92 : extern struct pci_fixup __end_pci_fixups_resume_early[];
93 : extern struct pci_fixup __start_pci_fixups_suspend[];
94 : extern struct pci_fixup __end_pci_fixups_suspend[];
95 : extern struct pci_fixup __start_pci_fixups_suspend_late[];
96 : extern struct pci_fixup __end_pci_fixups_suspend_late[];
97 :
98 : static bool pci_apply_fixup_final_quirks;
99 :
100 0 : void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
101 : {
102 : struct pci_fixup *start, *end;
103 :
104 0 : switch (pass) {
105 : case pci_fixup_early:
106 : start = __start_pci_fixups_early;
107 : end = __end_pci_fixups_early;
108 : break;
109 :
110 : case pci_fixup_header:
111 0 : start = __start_pci_fixups_header;
112 0 : end = __end_pci_fixups_header;
113 0 : break;
114 :
115 : case pci_fixup_final:
116 0 : if (!pci_apply_fixup_final_quirks)
117 : return;
118 : start = __start_pci_fixups_final;
119 : end = __end_pci_fixups_final;
120 : break;
121 :
122 : case pci_fixup_enable:
123 0 : start = __start_pci_fixups_enable;
124 0 : end = __end_pci_fixups_enable;
125 0 : break;
126 :
127 : case pci_fixup_resume:
128 0 : start = __start_pci_fixups_resume;
129 0 : end = __end_pci_fixups_resume;
130 0 : break;
131 :
132 : case pci_fixup_resume_early:
133 0 : start = __start_pci_fixups_resume_early;
134 0 : end = __end_pci_fixups_resume_early;
135 0 : break;
136 :
137 : case pci_fixup_suspend:
138 0 : start = __start_pci_fixups_suspend;
139 0 : end = __end_pci_fixups_suspend;
140 0 : break;
141 :
142 : case pci_fixup_suspend_late:
143 0 : start = __start_pci_fixups_suspend_late;
144 0 : end = __end_pci_fixups_suspend_late;
145 0 : break;
146 :
147 : default:
148 : /* stupid compiler warning, you would think with an enum... */
149 : return;
150 : }
151 0 : pci_do_fixups(dev, start, end);
152 : }
153 : EXPORT_SYMBOL(pci_fixup_device);
154 :
155 1 : static int __init pci_apply_final_quirks(void)
156 : {
157 1 : struct pci_dev *dev = NULL;
158 1 : u8 cls = 0;
159 : u8 tmp;
160 :
161 1 : if (pci_cache_line_size)
162 0 : pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
163 :
164 1 : pci_apply_fixup_final_quirks = true;
165 2 : for_each_pci_dev(dev) {
166 0 : pci_fixup_device(pci_fixup_final, dev);
167 : /*
168 : * If arch hasn't set it explicitly yet, use the CLS
169 : * value shared by all PCI devices. If there's a
170 : * mismatch, fall back to the default value.
171 : */
172 0 : if (!pci_cache_line_size) {
173 0 : pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
174 0 : if (!cls)
175 0 : cls = tmp;
176 0 : if (!tmp || cls == tmp)
177 0 : continue;
178 :
179 0 : pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
180 : cls << 2, tmp << 2,
181 : pci_dfl_cache_line_size << 2);
182 0 : pci_cache_line_size = pci_dfl_cache_line_size;
183 : }
184 : }
185 :
186 1 : if (!pci_cache_line_size) {
187 1 : pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
188 : pci_dfl_cache_line_size << 2);
189 1 : pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
190 : }
191 :
192 1 : return 0;
193 : }
194 : fs_initcall_sync(pci_apply_final_quirks);
195 :
196 : /*
197 : * Decoding should be disabled for a PCI device during BAR sizing to avoid
198 : * conflict. But doing so may cause problems on host bridge and perhaps other
199 : * key system devices. For devices that need to have mmio decoding always-on,
200 : * we need to set the dev->mmio_always_on bit.
201 : */
202 0 : static void quirk_mmio_always_on(struct pci_dev *dev)
203 : {
204 0 : dev->mmio_always_on = 1;
205 0 : }
206 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
207 : PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
208 :
209 : /*
210 : * The Mellanox Tavor device gives false positive parity errors. Disable
211 : * parity error reporting.
212 : */
213 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity);
214 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity);
215 :
216 : /*
217 : * Deal with broken BIOSes that neglect to enable passive release,
218 : * which can cause problems in combination with the 82441FX/PPro MTRRs
219 : */
220 0 : static void quirk_passive_release(struct pci_dev *dev)
221 : {
222 0 : struct pci_dev *d = NULL;
223 : unsigned char dlc;
224 :
225 : /*
226 : * We have to make sure a particular bit is set in the PIIX3
227 : * ISA bridge, so we have to go out and find it.
228 : */
229 0 : while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
230 0 : pci_read_config_byte(d, 0x82, &dlc);
231 0 : if (!(dlc & 1<<1)) {
232 0 : pci_info(d, "PIIX3: Enabling Passive Release\n");
233 0 : dlc |= 1<<1;
234 0 : pci_write_config_byte(d, 0x82, dlc);
235 : }
236 : }
237 0 : }
238 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
239 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
240 :
241 : /*
242 : * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
243 : * workaround but VIA don't answer queries. If you happen to have good
244 : * contacts at VIA ask them for me please -- Alan
245 : *
246 : * This appears to be BIOS not version dependent. So presumably there is a
247 : * chipset level fix.
248 : */
249 0 : static void quirk_isa_dma_hangs(struct pci_dev *dev)
250 : {
251 0 : if (!isa_dma_bridge_buggy) {
252 0 : isa_dma_bridge_buggy = 1;
253 0 : pci_info(dev, "Activating ISA DMA hang workarounds\n");
254 : }
255 0 : }
256 : /*
257 : * It's not totally clear which chipsets are the problematic ones. We know
258 : * 82C586 and 82C596 variants are affected.
259 : */
260 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
261 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
262 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
263 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
264 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
265 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
266 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
267 :
268 : /*
269 : * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
270 : * for some HT machines to use C4 w/o hanging.
271 : */
272 0 : static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
273 : {
274 : u32 pmbase;
275 : u16 pm1a;
276 :
277 0 : pci_read_config_dword(dev, 0x40, &pmbase);
278 0 : pmbase = pmbase & 0xff80;
279 0 : pm1a = inw(pmbase);
280 :
281 0 : if (pm1a & 0x10) {
282 0 : pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
283 0 : outw(0x10, pmbase);
284 : }
285 0 : }
286 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
287 :
288 : /* Chipsets where PCI->PCI transfers vanish or hang */
289 0 : static void quirk_nopcipci(struct pci_dev *dev)
290 : {
291 0 : if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
292 0 : pci_info(dev, "Disabling direct PCI/PCI transfers\n");
293 0 : pci_pci_problems |= PCIPCI_FAIL;
294 : }
295 0 : }
296 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
297 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
298 :
299 0 : static void quirk_nopciamd(struct pci_dev *dev)
300 : {
301 : u8 rev;
302 0 : pci_read_config_byte(dev, 0x08, &rev);
303 0 : if (rev == 0x13) {
304 : /* Erratum 24 */
305 0 : pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
306 0 : pci_pci_problems |= PCIAGP_FAIL;
307 : }
308 0 : }
309 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
310 :
311 : /* Triton requires workarounds to be used by the drivers */
312 0 : static void quirk_triton(struct pci_dev *dev)
313 : {
314 0 : if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
315 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
316 0 : pci_pci_problems |= PCIPCI_TRITON;
317 : }
318 0 : }
319 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
320 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
321 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
322 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
323 :
324 : /*
325 : * VIA Apollo KT133 needs PCI latency patch
326 : * Made according to a Windows driver-based patch by George E. Breese;
327 : * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
328 : * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
329 : * which Mr Breese based his work.
330 : *
331 : * Updated based on further information from the site and also on
332 : * information provided by VIA
333 : */
334 0 : static void quirk_vialatency(struct pci_dev *dev)
335 : {
336 : struct pci_dev *p;
337 : u8 busarb;
338 :
339 : /*
340 : * Ok, we have a potential problem chipset here. Now see if we have
341 : * a buggy southbridge.
342 : */
343 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
344 0 : if (p != NULL) {
345 :
346 : /*
347 : * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
348 : * thanks Dan Hollis.
349 : * Check for buggy part revisions
350 : */
351 0 : if (p->revision < 0x40 || p->revision > 0x42)
352 : goto exit;
353 : } else {
354 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
355 0 : if (p == NULL) /* No problem parts */
356 : goto exit;
357 :
358 : /* Check for buggy part revisions */
359 0 : if (p->revision < 0x10 || p->revision > 0x12)
360 : goto exit;
361 : }
362 :
363 : /*
364 : * Ok we have the problem. Now set the PCI master grant to occur
365 : * every master grant. The apparent bug is that under high PCI load
366 : * (quite common in Linux of course) you can get data loss when the
367 : * CPU is held off the bus for 3 bus master requests. This happens
368 : * to include the IDE controllers....
369 : *
370 : * VIA only apply this fix when an SB Live! is present but under
371 : * both Linux and Windows this isn't enough, and we have seen
372 : * corruption without SB Live! but with things like 3 UDMA IDE
373 : * controllers. So we ignore that bit of the VIA recommendation..
374 : */
375 0 : pci_read_config_byte(dev, 0x76, &busarb);
376 :
377 : /*
378 : * Set bit 4 and bit 5 of byte 76 to 0x01
379 : * "Master priority rotation on every PCI master grant"
380 : */
381 0 : busarb &= ~(1<<5);
382 0 : busarb |= (1<<4);
383 0 : pci_write_config_byte(dev, 0x76, busarb);
384 0 : pci_info(dev, "Applying VIA southbridge workaround\n");
385 : exit:
386 0 : pci_dev_put(p);
387 0 : }
388 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
389 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
390 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
391 : /* Must restore this on a resume from RAM */
392 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
393 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
394 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
395 :
396 : /* VIA Apollo VP3 needs ETBF on BT848/878 */
397 0 : static void quirk_viaetbf(struct pci_dev *dev)
398 : {
399 0 : if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
400 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
401 0 : pci_pci_problems |= PCIPCI_VIAETBF;
402 : }
403 0 : }
404 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
405 :
406 0 : static void quirk_vsfx(struct pci_dev *dev)
407 : {
408 0 : if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
409 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
410 0 : pci_pci_problems |= PCIPCI_VSFX;
411 : }
412 0 : }
413 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
414 :
415 : /*
416 : * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
417 : * space. Latency must be set to 0xA and Triton workaround applied too.
418 : * [Info kindly provided by ALi]
419 : */
420 0 : static void quirk_alimagik(struct pci_dev *dev)
421 : {
422 0 : if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
423 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
424 0 : pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
425 : }
426 0 : }
427 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
428 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
429 :
430 : /* Natoma has some interesting boundary conditions with Zoran stuff at least */
431 0 : static void quirk_natoma(struct pci_dev *dev)
432 : {
433 0 : if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
434 0 : pci_info(dev, "Limiting direct PCI/PCI transfers\n");
435 0 : pci_pci_problems |= PCIPCI_NATOMA;
436 : }
437 0 : }
438 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
439 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
440 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
441 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
442 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
443 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
444 :
445 : /*
446 : * This chip can cause PCI parity errors if config register 0xA0 is read
447 : * while DMAs are occurring.
448 : */
449 0 : static void quirk_citrine(struct pci_dev *dev)
450 : {
451 0 : dev->cfg_size = 0xA0;
452 0 : }
453 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
454 :
455 : /*
456 : * This chip can cause bus lockups if config addresses above 0x600
457 : * are read or written.
458 : */
459 0 : static void quirk_nfp6000(struct pci_dev *dev)
460 : {
461 0 : dev->cfg_size = 0x600;
462 0 : }
463 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
464 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
465 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
466 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
467 :
468 : /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
469 0 : static void quirk_extend_bar_to_page(struct pci_dev *dev)
470 : {
471 : int i;
472 :
473 0 : for (i = 0; i < PCI_STD_NUM_BARS; i++) {
474 0 : struct resource *r = &dev->resource[i];
475 :
476 0 : if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
477 0 : r->end = PAGE_SIZE - 1;
478 0 : r->start = 0;
479 0 : r->flags |= IORESOURCE_UNSET;
480 0 : pci_info(dev, "expanded BAR %d to page size: %pR\n",
481 : i, r);
482 : }
483 : }
484 0 : }
485 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
486 :
487 : /*
488 : * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
489 : * If it's needed, re-allocate the region.
490 : */
491 0 : static void quirk_s3_64M(struct pci_dev *dev)
492 : {
493 0 : struct resource *r = &dev->resource[0];
494 :
495 0 : if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
496 0 : r->flags |= IORESOURCE_UNSET;
497 0 : r->start = 0;
498 0 : r->end = 0x3ffffff;
499 : }
500 0 : }
501 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
502 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
503 :
504 0 : static void quirk_io(struct pci_dev *dev, int pos, unsigned int size,
505 : const char *name)
506 : {
507 : u32 region;
508 : struct pci_bus_region bus_region;
509 0 : struct resource *res = dev->resource + pos;
510 :
511 0 : pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
512 :
513 0 : if (!region)
514 0 : return;
515 :
516 0 : res->name = pci_name(dev);
517 0 : res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
518 0 : res->flags |=
519 : (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
520 0 : region &= ~(size - 1);
521 :
522 : /* Convert from PCI bus to resource space */
523 0 : bus_region.start = region;
524 0 : bus_region.end = region + size - 1;
525 0 : pcibios_bus_to_resource(dev->bus, res, &bus_region);
526 :
527 0 : pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
528 : name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
529 : }
530 :
531 : /*
532 : * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
533 : * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
534 : * BAR0 should be 8 bytes; instead, it may be set to something like 8k
535 : * (which conflicts w/ BAR1's memory range).
536 : *
537 : * CS553x's ISA PCI BARs may also be read-only (ref:
538 : * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
539 : */
540 0 : static void quirk_cs5536_vsa(struct pci_dev *dev)
541 : {
542 : static char *name = "CS5536 ISA bridge";
543 :
544 0 : if (pci_resource_len(dev, 0) != 8) {
545 0 : quirk_io(dev, 0, 8, name); /* SMB */
546 0 : quirk_io(dev, 1, 256, name); /* GPIO */
547 0 : quirk_io(dev, 2, 64, name); /* MFGPT */
548 0 : pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
549 : name);
550 : }
551 0 : }
552 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
553 :
554 0 : static void quirk_io_region(struct pci_dev *dev, int port,
555 : unsigned int size, int nr, const char *name)
556 : {
557 : u16 region;
558 : struct pci_bus_region bus_region;
559 0 : struct resource *res = dev->resource + nr;
560 :
561 0 : pci_read_config_word(dev, port, ®ion);
562 0 : region &= ~(size - 1);
563 :
564 0 : if (!region)
565 0 : return;
566 :
567 0 : res->name = pci_name(dev);
568 0 : res->flags = IORESOURCE_IO;
569 :
570 : /* Convert from PCI bus to resource space */
571 0 : bus_region.start = region;
572 0 : bus_region.end = region + size - 1;
573 0 : pcibios_bus_to_resource(dev->bus, res, &bus_region);
574 :
575 0 : if (!pci_claim_resource(dev, nr))
576 0 : pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
577 : }
578 :
579 : /*
580 : * ATI Northbridge setups MCE the processor if you even read somewhere
581 : * between 0x3b0->0x3bb or read 0x3d3
582 : */
583 0 : static void quirk_ati_exploding_mce(struct pci_dev *dev)
584 : {
585 0 : pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
586 : /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
587 0 : request_region(0x3b0, 0x0C, "RadeonIGP");
588 0 : request_region(0x3d3, 0x01, "RadeonIGP");
589 0 : }
590 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
591 :
592 : /*
593 : * In the AMD NL platform, this device ([1022:7912]) has a class code of
594 : * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
595 : * claim it.
596 : *
597 : * But the dwc3 driver is a more specific driver for this device, and we'd
598 : * prefer to use it instead of xhci. To prevent xhci from claiming the
599 : * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
600 : * defines as "USB device (not host controller)". The dwc3 driver can then
601 : * claim it based on its Vendor and Device ID.
602 : */
603 0 : static void quirk_amd_nl_class(struct pci_dev *pdev)
604 : {
605 0 : u32 class = pdev->class;
606 :
607 : /* Use "USB Device (not host controller)" class */
608 0 : pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
609 0 : pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
610 : class, pdev->class);
611 0 : }
612 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
613 : quirk_amd_nl_class);
614 :
615 : /*
616 : * Synopsys USB 3.x host HAPS platform has a class code of
617 : * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
618 : * devices should use dwc3-haps driver. Change these devices' class code to
619 : * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
620 : * them.
621 : */
622 0 : static void quirk_synopsys_haps(struct pci_dev *pdev)
623 : {
624 0 : u32 class = pdev->class;
625 :
626 0 : switch (pdev->device) {
627 : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
628 : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
629 : case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
630 0 : pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
631 0 : pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
632 : class, pdev->class);
633 0 : break;
634 : }
635 0 : }
636 : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
637 : PCI_CLASS_SERIAL_USB_XHCI, 0,
638 : quirk_synopsys_haps);
639 :
640 : /*
641 : * Let's make the southbridge information explicit instead of having to
642 : * worry about people probing the ACPI areas, for example.. (Yes, it
643 : * happens, and if you read the wrong ACPI register it will put the machine
644 : * to sleep with no way of waking it up again. Bummer).
645 : *
646 : * ALI M7101: Two IO regions pointed to by words at
647 : * 0xE0 (64 bytes of ACPI registers)
648 : * 0xE2 (32 bytes of SMB registers)
649 : */
650 0 : static void quirk_ali7101_acpi(struct pci_dev *dev)
651 : {
652 0 : quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
653 0 : quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
654 0 : }
655 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
656 :
657 0 : static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
658 : {
659 : u32 devres;
660 : u32 mask, size, base;
661 :
662 0 : pci_read_config_dword(dev, port, &devres);
663 0 : if ((devres & enable) != enable)
664 0 : return;
665 0 : mask = (devres >> 16) & 15;
666 0 : base = devres & 0xffff;
667 0 : size = 16;
668 : for (;;) {
669 0 : unsigned int bit = size >> 1;
670 0 : if ((bit & mask) == bit)
671 : break;
672 : size = bit;
673 : }
674 : /*
675 : * For now we only print it out. Eventually we'll want to
676 : * reserve it (at least if it's in the 0x1000+ range), but
677 : * let's get enough confirmation reports first.
678 : */
679 0 : base &= -size;
680 0 : pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
681 : }
682 :
683 0 : static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
684 : {
685 : u32 devres;
686 : u32 mask, size, base;
687 :
688 0 : pci_read_config_dword(dev, port, &devres);
689 0 : if ((devres & enable) != enable)
690 0 : return;
691 0 : base = devres & 0xffff0000;
692 0 : mask = (devres & 0x3f) << 16;
693 0 : size = 128 << 16;
694 : for (;;) {
695 0 : unsigned int bit = size >> 1;
696 0 : if ((bit & mask) == bit)
697 : break;
698 : size = bit;
699 : }
700 :
701 : /*
702 : * For now we only print it out. Eventually we'll want to
703 : * reserve it, but let's get enough confirmation reports first.
704 : */
705 0 : base &= -size;
706 0 : pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
707 : }
708 :
709 : /*
710 : * PIIX4 ACPI: Two IO regions pointed to by longwords at
711 : * 0x40 (64 bytes of ACPI registers)
712 : * 0x90 (16 bytes of SMB registers)
713 : * and a few strange programmable PIIX4 device resources.
714 : */
715 0 : static void quirk_piix4_acpi(struct pci_dev *dev)
716 : {
717 : u32 res_a;
718 :
719 0 : quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
720 0 : quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
721 :
722 : /* Device resource A has enables for some of the other ones */
723 0 : pci_read_config_dword(dev, 0x5c, &res_a);
724 :
725 0 : piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
726 0 : piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
727 :
728 : /* Device resource D is just bitfields for static resources */
729 :
730 : /* Device 12 enabled? */
731 0 : if (res_a & (1 << 29)) {
732 0 : piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
733 0 : piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
734 : }
735 : /* Device 13 enabled? */
736 0 : if (res_a & (1 << 30)) {
737 0 : piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
738 0 : piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
739 : }
740 0 : piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
741 0 : piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
742 0 : }
743 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
744 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
745 :
746 : #define ICH_PMBASE 0x40
747 : #define ICH_ACPI_CNTL 0x44
748 : #define ICH4_ACPI_EN 0x10
749 : #define ICH6_ACPI_EN 0x80
750 : #define ICH4_GPIOBASE 0x58
751 : #define ICH4_GPIO_CNTL 0x5c
752 : #define ICH4_GPIO_EN 0x10
753 : #define ICH6_GPIOBASE 0x48
754 : #define ICH6_GPIO_CNTL 0x4c
755 : #define ICH6_GPIO_EN 0x10
756 :
757 : /*
758 : * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
759 : * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
760 : * 0x58 (64 bytes of GPIO I/O space)
761 : */
762 0 : static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
763 : {
764 : u8 enable;
765 :
766 : /*
767 : * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
768 : * with low legacy (and fixed) ports. We don't know the decoding
769 : * priority and can't tell whether the legacy device or the one created
770 : * here is really at that address. This happens on boards with broken
771 : * BIOSes.
772 : */
773 0 : pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
774 0 : if (enable & ICH4_ACPI_EN)
775 0 : quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
776 : "ICH4 ACPI/GPIO/TCO");
777 :
778 0 : pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
779 0 : if (enable & ICH4_GPIO_EN)
780 0 : quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
781 : "ICH4 GPIO");
782 0 : }
783 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
784 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
785 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
786 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
787 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
788 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
789 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
790 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
791 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
792 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
793 :
794 0 : static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
795 : {
796 : u8 enable;
797 :
798 0 : pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
799 0 : if (enable & ICH6_ACPI_EN)
800 0 : quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
801 : "ICH6 ACPI/GPIO/TCO");
802 :
803 0 : pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
804 0 : if (enable & ICH6_GPIO_EN)
805 0 : quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
806 : "ICH6 GPIO");
807 0 : }
808 :
809 0 : static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
810 : const char *name, int dynsize)
811 : {
812 : u32 val;
813 : u32 size, base;
814 :
815 0 : pci_read_config_dword(dev, reg, &val);
816 :
817 : /* Enabled? */
818 0 : if (!(val & 1))
819 0 : return;
820 0 : base = val & 0xfffc;
821 0 : if (dynsize) {
822 : /*
823 : * This is not correct. It is 16, 32 or 64 bytes depending on
824 : * register D31:F0:ADh bits 5:4.
825 : *
826 : * But this gets us at least _part_ of it.
827 : */
828 : size = 16;
829 : } else {
830 0 : size = 128;
831 : }
832 0 : base &= ~(size-1);
833 :
834 : /*
835 : * Just print it out for now. We should reserve it after more
836 : * debugging.
837 : */
838 0 : pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
839 : }
840 :
841 0 : static void quirk_ich6_lpc(struct pci_dev *dev)
842 : {
843 : /* Shared ACPI/GPIO decode with all ICH6+ */
844 0 : ich6_lpc_acpi_gpio(dev);
845 :
846 : /* ICH6-specific generic IO decode */
847 0 : ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
848 0 : ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
849 0 : }
850 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
851 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
852 :
853 0 : static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
854 : const char *name)
855 : {
856 : u32 val;
857 : u32 mask, base;
858 :
859 0 : pci_read_config_dword(dev, reg, &val);
860 :
861 : /* Enabled? */
862 0 : if (!(val & 1))
863 0 : return;
864 :
865 : /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
866 0 : base = val & 0xfffc;
867 0 : mask = (val >> 16) & 0xfc;
868 0 : mask |= 3;
869 :
870 : /*
871 : * Just print it out for now. We should reserve it after more
872 : * debugging.
873 : */
874 0 : pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
875 : }
876 :
877 : /* ICH7-10 has the same common LPC generic IO decode registers */
878 0 : static void quirk_ich7_lpc(struct pci_dev *dev)
879 : {
880 : /* We share the common ACPI/GPIO decode with ICH6 */
881 0 : ich6_lpc_acpi_gpio(dev);
882 :
883 : /* And have 4 ICH7+ generic decodes */
884 0 : ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
885 0 : ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
886 0 : ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
887 0 : ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
888 0 : }
889 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
890 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
891 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
892 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
893 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
894 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
895 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
896 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
897 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
898 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
899 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
900 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
901 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
902 :
903 : /*
904 : * VIA ACPI: One IO region pointed to by longword at
905 : * 0x48 or 0x20 (256 bytes of ACPI registers)
906 : */
907 0 : static void quirk_vt82c586_acpi(struct pci_dev *dev)
908 : {
909 0 : if (dev->revision & 0x10)
910 0 : quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
911 : "vt82c586 ACPI");
912 0 : }
913 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
914 :
915 : /*
916 : * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
917 : * 0x48 (256 bytes of ACPI registers)
918 : * 0x70 (128 bytes of hardware monitoring register)
919 : * 0x90 (16 bytes of SMB registers)
920 : */
921 0 : static void quirk_vt82c686_acpi(struct pci_dev *dev)
922 : {
923 0 : quirk_vt82c586_acpi(dev);
924 :
925 0 : quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
926 : "vt82c686 HW-mon");
927 :
928 0 : quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
929 0 : }
930 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
931 :
932 : /*
933 : * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
934 : * 0x88 (128 bytes of power management registers)
935 : * 0xd0 (16 bytes of SMB registers)
936 : */
937 0 : static void quirk_vt8235_acpi(struct pci_dev *dev)
938 : {
939 0 : quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
940 0 : quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
941 0 : }
942 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
943 :
944 : /*
945 : * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
946 : * back-to-back: Disable fast back-to-back on the secondary bus segment
947 : */
948 0 : static void quirk_xio2000a(struct pci_dev *dev)
949 : {
950 : struct pci_dev *pdev;
951 : u16 command;
952 :
953 0 : pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
954 0 : list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
955 0 : pci_read_config_word(pdev, PCI_COMMAND, &command);
956 0 : if (command & PCI_COMMAND_FAST_BACK)
957 0 : pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
958 : }
959 0 : }
960 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
961 : quirk_xio2000a);
962 :
963 : #ifdef CONFIG_X86_IO_APIC
964 :
965 : #include <asm/io_apic.h>
966 :
967 : /*
968 : * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
969 : * devices to the external APIC.
970 : *
971 : * TODO: When we have device-specific interrupt routers, this code will go
972 : * away from quirks.
973 : */
974 : static void quirk_via_ioapic(struct pci_dev *dev)
975 : {
976 : u8 tmp;
977 :
978 : if (nr_ioapics < 1)
979 : tmp = 0; /* nothing routed to external APIC */
980 : else
981 : tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
982 :
983 : pci_info(dev, "%s VIA external APIC routing\n",
984 : tmp ? "Enabling" : "Disabling");
985 :
986 : /* Offset 0x58: External APIC IRQ output control */
987 : pci_write_config_byte(dev, 0x58, tmp);
988 : }
989 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
990 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
991 :
992 : /*
993 : * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
994 : * This leads to doubled level interrupt rates.
995 : * Set this bit to get rid of cycle wastage.
996 : * Otherwise uncritical.
997 : */
998 : static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
999 : {
1000 : u8 misc_control2;
1001 : #define BYPASS_APIC_DEASSERT 8
1002 :
1003 : pci_read_config_byte(dev, 0x5B, &misc_control2);
1004 : if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1005 : pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1006 : pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1007 : }
1008 : }
1009 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1010 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1011 :
1012 : /*
1013 : * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1014 : * We check all revs >= B0 (yet not in the pre production!) as the bug
1015 : * is currently marked NoFix
1016 : *
1017 : * We have multiple reports of hangs with this chipset that went away with
1018 : * noapic specified. For the moment we assume it's the erratum. We may be wrong
1019 : * of course. However the advice is demonstrably good even if so.
1020 : */
1021 : static void quirk_amd_ioapic(struct pci_dev *dev)
1022 : {
1023 : if (dev->revision >= 0x02) {
1024 : pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1025 : pci_warn(dev, " : booting with the \"noapic\" option\n");
1026 : }
1027 : }
1028 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1029 : #endif /* CONFIG_X86_IO_APIC */
1030 :
1031 : #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1032 :
1033 : static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1034 : {
1035 : /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1036 : if (dev->subsystem_device == 0xa118)
1037 : dev->sriov->link = dev->devfn;
1038 : }
1039 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1040 : #endif
1041 :
1042 : /*
1043 : * Some settings of MMRBC can lead to data corruption so block changes.
1044 : * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1045 : */
1046 0 : static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1047 : {
1048 0 : if (dev->subordinate && dev->revision <= 0x12) {
1049 0 : pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1050 : dev->revision);
1051 0 : dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1052 : }
1053 0 : }
1054 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1055 :
1056 : /*
1057 : * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1058 : * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1059 : * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1060 : * of the ACPI SCI interrupt is only done for convenience.
1061 : * -jgarzik
1062 : */
1063 0 : static void quirk_via_acpi(struct pci_dev *d)
1064 : {
1065 : u8 irq;
1066 :
1067 : /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1068 0 : pci_read_config_byte(d, 0x42, &irq);
1069 0 : irq &= 0xf;
1070 0 : if (irq && (irq != 2))
1071 0 : d->irq = irq;
1072 0 : }
1073 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1074 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1075 :
1076 : /* VIA bridges which have VLink */
1077 : static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1078 :
1079 0 : static void quirk_via_bridge(struct pci_dev *dev)
1080 : {
1081 : /* See what bridge we have and find the device ranges */
1082 0 : switch (dev->device) {
1083 : case PCI_DEVICE_ID_VIA_82C686:
1084 : /*
1085 : * The VT82C686 is special; it attaches to PCI and can have
1086 : * any device number. All its subdevices are functions of
1087 : * that single device.
1088 : */
1089 0 : via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1090 0 : via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1091 0 : break;
1092 : case PCI_DEVICE_ID_VIA_8237:
1093 : case PCI_DEVICE_ID_VIA_8237A:
1094 0 : via_vlink_dev_lo = 15;
1095 0 : break;
1096 : case PCI_DEVICE_ID_VIA_8235:
1097 0 : via_vlink_dev_lo = 16;
1098 0 : break;
1099 : case PCI_DEVICE_ID_VIA_8231:
1100 : case PCI_DEVICE_ID_VIA_8233_0:
1101 : case PCI_DEVICE_ID_VIA_8233A:
1102 : case PCI_DEVICE_ID_VIA_8233C_0:
1103 0 : via_vlink_dev_lo = 17;
1104 0 : break;
1105 : }
1106 0 : }
1107 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1108 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1109 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1110 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1111 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1112 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1113 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1114 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1115 :
1116 : /*
1117 : * quirk_via_vlink - VIA VLink IRQ number update
1118 : * @dev: PCI device
1119 : *
1120 : * If the device we are dealing with is on a PIC IRQ we need to ensure that
1121 : * the IRQ line register which usually is not relevant for PCI cards, is
1122 : * actually written so that interrupts get sent to the right place.
1123 : *
1124 : * We only do this on systems where a VIA south bridge was detected, and
1125 : * only for VIA devices on the motherboard (see quirk_via_bridge above).
1126 : */
1127 0 : static void quirk_via_vlink(struct pci_dev *dev)
1128 : {
1129 : u8 irq, new_irq;
1130 :
1131 : /* Check if we have VLink at all */
1132 0 : if (via_vlink_dev_lo == -1)
1133 0 : return;
1134 :
1135 0 : new_irq = dev->irq;
1136 :
1137 : /* Don't quirk interrupts outside the legacy IRQ range */
1138 0 : if (!new_irq || new_irq > 15)
1139 : return;
1140 :
1141 : /* Internal device ? */
1142 0 : if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1143 0 : PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1144 : return;
1145 :
1146 : /*
1147 : * This is an internal VLink device on a PIC interrupt. The BIOS
1148 : * ought to have set this but may not have, so we redo it.
1149 : */
1150 0 : pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1151 0 : if (new_irq != irq) {
1152 0 : pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1153 : irq, new_irq);
1154 0 : udelay(15); /* unknown if delay really needed */
1155 0 : pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1156 : }
1157 : }
1158 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1159 :
1160 : /*
1161 : * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1162 : * of VT82C597 for backward compatibility. We need to switch it off to be
1163 : * able to recognize the real type of the chip.
1164 : */
1165 0 : static void quirk_vt82c598_id(struct pci_dev *dev)
1166 : {
1167 0 : pci_write_config_byte(dev, 0xfc, 0);
1168 0 : pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1169 0 : }
1170 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1171 :
1172 : /*
1173 : * CardBus controllers have a legacy base address that enables them to
1174 : * respond as i82365 pcmcia controllers. We don't want them to do this
1175 : * even if the Linux CardBus driver is not loaded, because the Linux i82365
1176 : * driver does not (and should not) handle CardBus.
1177 : */
1178 0 : static void quirk_cardbus_legacy(struct pci_dev *dev)
1179 : {
1180 0 : pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1181 0 : }
1182 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1183 : PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1184 : DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1185 : PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1186 :
1187 : /*
1188 : * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1189 : * what the designers were smoking but let's not inhale...
1190 : *
1191 : * To be fair to AMD, it follows the spec by default, it's BIOS people who
1192 : * turn it off!
1193 : */
1194 0 : static void quirk_amd_ordering(struct pci_dev *dev)
1195 : {
1196 : u32 pcic;
1197 0 : pci_read_config_dword(dev, 0x4C, &pcic);
1198 0 : if ((pcic & 6) != 6) {
1199 0 : pcic |= 6;
1200 0 : pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1201 0 : pci_write_config_dword(dev, 0x4C, pcic);
1202 0 : pci_read_config_dword(dev, 0x84, &pcic);
1203 0 : pcic |= (1 << 23); /* Required in this mode */
1204 0 : pci_write_config_dword(dev, 0x84, pcic);
1205 : }
1206 0 : }
1207 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1208 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1209 :
1210 : /*
1211 : * DreamWorks-provided workaround for Dunord I-3000 problem
1212 : *
1213 : * This card decodes and responds to addresses not apparently assigned to
1214 : * it. We force a larger allocation to ensure that nothing gets put too
1215 : * close to it.
1216 : */
1217 0 : static void quirk_dunord(struct pci_dev *dev)
1218 : {
1219 0 : struct resource *r = &dev->resource[1];
1220 :
1221 0 : r->flags |= IORESOURCE_UNSET;
1222 0 : r->start = 0;
1223 0 : r->end = 0xffffff;
1224 0 : }
1225 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1226 :
1227 : /*
1228 : * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1229 : * decoding (transparent), and does indicate this in the ProgIf.
1230 : * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1231 : */
1232 0 : static void quirk_transparent_bridge(struct pci_dev *dev)
1233 : {
1234 0 : dev->transparent = 1;
1235 0 : }
1236 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1237 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1238 :
1239 : /*
1240 : * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1241 : * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1242 : * found at http://www.national.com/analog for info on what these bits do.
1243 : * <christer@weinigel.se>
1244 : */
1245 0 : static void quirk_mediagx_master(struct pci_dev *dev)
1246 : {
1247 : u8 reg;
1248 :
1249 0 : pci_read_config_byte(dev, 0x41, ®);
1250 0 : if (reg & 2) {
1251 0 : reg &= ~2;
1252 0 : pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1253 : reg);
1254 0 : pci_write_config_byte(dev, 0x41, reg);
1255 : }
1256 0 : }
1257 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1258 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1259 :
1260 : /*
1261 : * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1262 : * in the odd case it is not the results are corruption hence the presence
1263 : * of a Linux check.
1264 : */
1265 0 : static void quirk_disable_pxb(struct pci_dev *pdev)
1266 : {
1267 : u16 config;
1268 :
1269 0 : if (pdev->revision != 0x04) /* Only C0 requires this */
1270 0 : return;
1271 0 : pci_read_config_word(pdev, 0x40, &config);
1272 0 : if (config & (1<<6)) {
1273 0 : config &= ~(1<<6);
1274 0 : pci_write_config_word(pdev, 0x40, config);
1275 0 : pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1276 : }
1277 : }
1278 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1279 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1280 :
1281 0 : static void quirk_amd_ide_mode(struct pci_dev *pdev)
1282 : {
1283 : /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1284 : u8 tmp;
1285 :
1286 0 : pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1287 0 : if (tmp == 0x01) {
1288 0 : pci_read_config_byte(pdev, 0x40, &tmp);
1289 0 : pci_write_config_byte(pdev, 0x40, tmp|1);
1290 0 : pci_write_config_byte(pdev, 0x9, 1);
1291 0 : pci_write_config_byte(pdev, 0xa, 6);
1292 0 : pci_write_config_byte(pdev, 0x40, tmp);
1293 :
1294 0 : pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1295 0 : pci_info(pdev, "set SATA to AHCI mode\n");
1296 : }
1297 0 : }
1298 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1299 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1300 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1301 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1302 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1303 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1304 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1305 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1306 :
1307 : /* Serverworks CSB5 IDE does not fully support native mode */
1308 0 : static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1309 : {
1310 : u8 prog;
1311 0 : pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1312 0 : if (prog & 5) {
1313 0 : prog &= ~5;
1314 0 : pdev->class &= ~5;
1315 0 : pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1316 : /* PCI layer will sort out resources */
1317 : }
1318 0 : }
1319 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1320 :
1321 : /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1322 0 : static void quirk_ide_samemode(struct pci_dev *pdev)
1323 : {
1324 : u8 prog;
1325 :
1326 0 : pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1327 :
1328 0 : if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1329 0 : pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1330 0 : prog &= ~5;
1331 0 : pdev->class &= ~5;
1332 0 : pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1333 : }
1334 0 : }
1335 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1336 :
1337 : /* Some ATA devices break if put into D3 */
1338 0 : static void quirk_no_ata_d3(struct pci_dev *pdev)
1339 : {
1340 0 : pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1341 0 : }
1342 : /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1343 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1344 : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1345 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1346 : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1347 : /* ALi loses some register settings that we cannot then restore */
1348 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1349 : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1350 : /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1351 : occur when mode detecting */
1352 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1353 : PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1354 :
1355 : /*
1356 : * This was originally an Alpha-specific thing, but it really fits here.
1357 : * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1358 : */
1359 0 : static void quirk_eisa_bridge(struct pci_dev *dev)
1360 : {
1361 0 : dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1362 0 : }
1363 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1364 :
1365 : /*
1366 : * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1367 : * is not activated. The myth is that Asus said that they do not want the
1368 : * users to be irritated by just another PCI Device in the Win98 device
1369 : * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1370 : * package 2.7.0 for details)
1371 : *
1372 : * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1373 : * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1374 : * becomes necessary to do this tweak in two steps -- the chosen trigger
1375 : * is either the Host bridge (preferred) or on-board VGA controller.
1376 : *
1377 : * Note that we used to unhide the SMBus that way on Toshiba laptops
1378 : * (Satellite A40 and Tecra M2) but then found that the thermal management
1379 : * was done by SMM code, which could cause unsynchronized concurrent
1380 : * accesses to the SMBus registers, with potentially bad effects. Thus you
1381 : * should be very careful when adding new entries: if SMM is accessing the
1382 : * Intel SMBus, this is a very good reason to leave it hidden.
1383 : *
1384 : * Likewise, many recent laptops use ACPI for thermal management. If the
1385 : * ACPI DSDT code accesses the SMBus, then Linux should not access it
1386 : * natively, and keeping the SMBus hidden is the right thing to do. If you
1387 : * are about to add an entry in the table below, please first disassemble
1388 : * the DSDT and double-check that there is no code accessing the SMBus.
1389 : */
1390 : static int asus_hides_smbus;
1391 :
1392 0 : static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1393 : {
1394 0 : if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1395 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1396 0 : switch (dev->subsystem_device) {
1397 : case 0x8025: /* P4B-LX */
1398 : case 0x8070: /* P4B */
1399 : case 0x8088: /* P4B533 */
1400 : case 0x1626: /* L3C notebook */
1401 0 : asus_hides_smbus = 1;
1402 : }
1403 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1404 0 : switch (dev->subsystem_device) {
1405 : case 0x80b1: /* P4GE-V */
1406 : case 0x80b2: /* P4PE */
1407 : case 0x8093: /* P4B533-V */
1408 0 : asus_hides_smbus = 1;
1409 : }
1410 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1411 0 : switch (dev->subsystem_device) {
1412 : case 0x8030: /* P4T533 */
1413 0 : asus_hides_smbus = 1;
1414 : }
1415 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1416 0 : switch (dev->subsystem_device) {
1417 : case 0x8070: /* P4G8X Deluxe */
1418 0 : asus_hides_smbus = 1;
1419 : }
1420 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1421 0 : switch (dev->subsystem_device) {
1422 : case 0x80c9: /* PU-DLS */
1423 0 : asus_hides_smbus = 1;
1424 : }
1425 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1426 0 : switch (dev->subsystem_device) {
1427 : case 0x1751: /* M2N notebook */
1428 : case 0x1821: /* M5N notebook */
1429 : case 0x1897: /* A6L notebook */
1430 0 : asus_hides_smbus = 1;
1431 : }
1432 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1433 0 : switch (dev->subsystem_device) {
1434 : case 0x184b: /* W1N notebook */
1435 : case 0x186a: /* M6Ne notebook */
1436 0 : asus_hides_smbus = 1;
1437 : }
1438 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1439 0 : switch (dev->subsystem_device) {
1440 : case 0x80f2: /* P4P800-X */
1441 0 : asus_hides_smbus = 1;
1442 : }
1443 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1444 0 : switch (dev->subsystem_device) {
1445 : case 0x1882: /* M6V notebook */
1446 : case 0x1977: /* A6VA notebook */
1447 0 : asus_hides_smbus = 1;
1448 : }
1449 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1450 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1451 0 : switch (dev->subsystem_device) {
1452 : case 0x088C: /* HP Compaq nc8000 */
1453 : case 0x0890: /* HP Compaq nc6000 */
1454 0 : asus_hides_smbus = 1;
1455 : }
1456 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1457 0 : switch (dev->subsystem_device) {
1458 : case 0x12bc: /* HP D330L */
1459 : case 0x12bd: /* HP D530 */
1460 : case 0x006a: /* HP Compaq nx9500 */
1461 0 : asus_hides_smbus = 1;
1462 : }
1463 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1464 0 : switch (dev->subsystem_device) {
1465 : case 0x12bf: /* HP xw4100 */
1466 0 : asus_hides_smbus = 1;
1467 : }
1468 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1469 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1470 0 : switch (dev->subsystem_device) {
1471 : case 0xC00C: /* Samsung P35 notebook */
1472 0 : asus_hides_smbus = 1;
1473 : }
1474 0 : } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1475 0 : if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1476 0 : switch (dev->subsystem_device) {
1477 : case 0x0058: /* Compaq Evo N620c */
1478 0 : asus_hides_smbus = 1;
1479 : }
1480 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1481 0 : switch (dev->subsystem_device) {
1482 : case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1483 : /* Motherboard doesn't have Host bridge
1484 : * subvendor/subdevice IDs, therefore checking
1485 : * its on-board VGA controller */
1486 0 : asus_hides_smbus = 1;
1487 : }
1488 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1489 0 : switch (dev->subsystem_device) {
1490 : case 0x00b8: /* Compaq Evo D510 CMT */
1491 : case 0x00b9: /* Compaq Evo D510 SFF */
1492 : case 0x00ba: /* Compaq Evo D510 USDT */
1493 : /* Motherboard doesn't have Host bridge
1494 : * subvendor/subdevice IDs and on-board VGA
1495 : * controller is disabled if an AGP card is
1496 : * inserted, therefore checking USB UHCI
1497 : * Controller #1 */
1498 0 : asus_hides_smbus = 1;
1499 : }
1500 0 : else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1501 0 : switch (dev->subsystem_device) {
1502 : case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1503 : /* Motherboard doesn't have host bridge
1504 : * subvendor/subdevice IDs, therefore checking
1505 : * its on-board VGA controller */
1506 0 : asus_hides_smbus = 1;
1507 : }
1508 : }
1509 0 : }
1510 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1511 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1512 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1513 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1514 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1515 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1516 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1517 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1518 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1519 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1520 :
1521 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1522 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1523 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1524 :
1525 0 : static void asus_hides_smbus_lpc(struct pci_dev *dev)
1526 : {
1527 : u16 val;
1528 :
1529 0 : if (likely(!asus_hides_smbus))
1530 0 : return;
1531 :
1532 0 : pci_read_config_word(dev, 0xF2, &val);
1533 0 : if (val & 0x8) {
1534 0 : pci_write_config_word(dev, 0xF2, val & (~0x8));
1535 0 : pci_read_config_word(dev, 0xF2, &val);
1536 0 : if (val & 0x8)
1537 0 : pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1538 : val);
1539 : else
1540 0 : pci_info(dev, "Enabled i801 SMBus device\n");
1541 : }
1542 : }
1543 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1544 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1545 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1546 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1547 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1548 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1549 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1550 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1551 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1552 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1553 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1554 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1555 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1556 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1557 :
1558 : /* It appears we just have one such device. If not, we have a warning */
1559 : static void __iomem *asus_rcba_base;
1560 0 : static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1561 : {
1562 : u32 rcba;
1563 :
1564 0 : if (likely(!asus_hides_smbus))
1565 0 : return;
1566 0 : WARN_ON(asus_rcba_base);
1567 :
1568 0 : pci_read_config_dword(dev, 0xF0, &rcba);
1569 : /* use bits 31:14, 16 kB aligned */
1570 0 : asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1571 : if (asus_rcba_base == NULL)
1572 : return;
1573 : }
1574 :
1575 0 : static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1576 : {
1577 : u32 val;
1578 :
1579 0 : if (likely(!asus_hides_smbus || !asus_rcba_base))
1580 : return;
1581 :
1582 : /* read the Function Disable register, dword mode only */
1583 0 : val = readl(asus_rcba_base + 0x3418);
1584 :
1585 : /* enable the SMBus device */
1586 0 : writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1587 : }
1588 :
1589 0 : static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1590 : {
1591 0 : if (likely(!asus_hides_smbus || !asus_rcba_base))
1592 : return;
1593 :
1594 0 : iounmap(asus_rcba_base);
1595 0 : asus_rcba_base = NULL;
1596 0 : pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1597 : }
1598 :
1599 0 : static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1600 : {
1601 0 : asus_hides_smbus_lpc_ich6_suspend(dev);
1602 0 : asus_hides_smbus_lpc_ich6_resume_early(dev);
1603 0 : asus_hides_smbus_lpc_ich6_resume(dev);
1604 0 : }
1605 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1606 : DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1607 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1608 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1609 :
1610 : /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1611 0 : static void quirk_sis_96x_smbus(struct pci_dev *dev)
1612 : {
1613 0 : u8 val = 0;
1614 0 : pci_read_config_byte(dev, 0x77, &val);
1615 0 : if (val & 0x10) {
1616 0 : pci_info(dev, "Enabling SiS 96x SMBus\n");
1617 0 : pci_write_config_byte(dev, 0x77, val & ~0x10);
1618 : }
1619 0 : }
1620 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1621 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1622 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1623 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1624 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1625 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1626 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1627 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1628 :
1629 : /*
1630 : * ... This is further complicated by the fact that some SiS96x south
1631 : * bridges pretend to be 85C503/5513 instead. In that case see if we
1632 : * spotted a compatible north bridge to make sure.
1633 : * (pci_find_device() doesn't work yet)
1634 : *
1635 : * We can also enable the sis96x bit in the discovery register..
1636 : */
1637 : #define SIS_DETECT_REGISTER 0x40
1638 :
1639 0 : static void quirk_sis_503(struct pci_dev *dev)
1640 : {
1641 : u8 reg;
1642 : u16 devid;
1643 :
1644 0 : pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1645 0 : pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1646 0 : pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1647 0 : if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1648 0 : pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1649 0 : return;
1650 : }
1651 :
1652 : /*
1653 : * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1654 : * it has already been processed. (Depends on link order, which is
1655 : * apparently not guaranteed)
1656 : */
1657 0 : dev->device = devid;
1658 0 : quirk_sis_96x_smbus(dev);
1659 : }
1660 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1661 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1662 :
1663 : /*
1664 : * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1665 : * and MC97 modem controller are disabled when a second PCI soundcard is
1666 : * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1667 : * -- bjd
1668 : */
1669 0 : static void asus_hides_ac97_lpc(struct pci_dev *dev)
1670 : {
1671 : u8 val;
1672 0 : int asus_hides_ac97 = 0;
1673 :
1674 0 : if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1675 0 : if (dev->device == PCI_DEVICE_ID_VIA_8237)
1676 0 : asus_hides_ac97 = 1;
1677 : }
1678 :
1679 0 : if (!asus_hides_ac97)
1680 0 : return;
1681 :
1682 0 : pci_read_config_byte(dev, 0x50, &val);
1683 0 : if (val & 0xc0) {
1684 0 : pci_write_config_byte(dev, 0x50, val & (~0xc0));
1685 0 : pci_read_config_byte(dev, 0x50, &val);
1686 0 : if (val & 0xc0)
1687 0 : pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1688 : val);
1689 : else
1690 0 : pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1691 : }
1692 : }
1693 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1694 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1695 :
1696 : #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1697 :
1698 : /*
1699 : * If we are using libata we can drive this chip properly but must do this
1700 : * early on to make the additional device appear during the PCI scanning.
1701 : */
1702 : static void quirk_jmicron_ata(struct pci_dev *pdev)
1703 : {
1704 : u32 conf1, conf5, class;
1705 : u8 hdr;
1706 :
1707 : /* Only poke fn 0 */
1708 : if (PCI_FUNC(pdev->devfn))
1709 : return;
1710 :
1711 : pci_read_config_dword(pdev, 0x40, &conf1);
1712 : pci_read_config_dword(pdev, 0x80, &conf5);
1713 :
1714 : conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1715 : conf5 &= ~(1 << 24); /* Clear bit 24 */
1716 :
1717 : switch (pdev->device) {
1718 : case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1719 : case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1720 : case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1721 : /* The controller should be in single function ahci mode */
1722 : conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1723 : break;
1724 :
1725 : case PCI_DEVICE_ID_JMICRON_JMB365:
1726 : case PCI_DEVICE_ID_JMICRON_JMB366:
1727 : /* Redirect IDE second PATA port to the right spot */
1728 : conf5 |= (1 << 24);
1729 : fallthrough;
1730 : case PCI_DEVICE_ID_JMICRON_JMB361:
1731 : case PCI_DEVICE_ID_JMICRON_JMB363:
1732 : case PCI_DEVICE_ID_JMICRON_JMB369:
1733 : /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1734 : /* Set the class codes correctly and then direct IDE 0 */
1735 : conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1736 : break;
1737 :
1738 : case PCI_DEVICE_ID_JMICRON_JMB368:
1739 : /* The controller should be in single function IDE mode */
1740 : conf1 |= 0x00C00000; /* Set 22, 23 */
1741 : break;
1742 : }
1743 :
1744 : pci_write_config_dword(pdev, 0x40, conf1);
1745 : pci_write_config_dword(pdev, 0x80, conf5);
1746 :
1747 : /* Update pdev accordingly */
1748 : pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1749 : pdev->hdr_type = hdr & 0x7f;
1750 : pdev->multifunction = !!(hdr & 0x80);
1751 :
1752 : pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1753 : pdev->class = class >> 8;
1754 : }
1755 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1756 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1757 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1758 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1759 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1760 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1761 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1762 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1763 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1764 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1765 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1766 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1767 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1768 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1769 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1770 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1771 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1772 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1773 :
1774 : #endif
1775 :
1776 0 : static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1777 : {
1778 0 : if (dev->multifunction) {
1779 0 : device_disable_async_suspend(&dev->dev);
1780 0 : pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1781 : }
1782 0 : }
1783 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1784 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1785 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1786 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1787 :
1788 : #ifdef CONFIG_X86_IO_APIC
1789 : static void quirk_alder_ioapic(struct pci_dev *pdev)
1790 : {
1791 : int i;
1792 :
1793 : if ((pdev->class >> 8) != 0xff00)
1794 : return;
1795 :
1796 : /*
1797 : * The first BAR is the location of the IO-APIC... we must
1798 : * not touch this (and it's already covered by the fixmap), so
1799 : * forcibly insert it into the resource tree.
1800 : */
1801 : if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1802 : insert_resource(&iomem_resource, &pdev->resource[0]);
1803 :
1804 : /*
1805 : * The next five BARs all seem to be rubbish, so just clean
1806 : * them out.
1807 : */
1808 : for (i = 1; i < PCI_STD_NUM_BARS; i++)
1809 : memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1810 : }
1811 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1812 : #endif
1813 :
1814 0 : static void quirk_no_msi(struct pci_dev *dev)
1815 : {
1816 0 : pci_info(dev, "avoiding MSI to work around a hardware defect\n");
1817 0 : dev->no_msi = 1;
1818 0 : }
1819 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1820 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1821 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1822 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1823 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1824 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1825 :
1826 0 : static void quirk_pcie_mch(struct pci_dev *pdev)
1827 : {
1828 0 : pdev->no_msi = 1;
1829 0 : }
1830 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1831 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1832 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1833 :
1834 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1835 :
1836 : /*
1837 : * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
1838 : * actually on the AMBA bus. These fake PCI devices can support SVA via
1839 : * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1840 : *
1841 : * Normally stalling must not be enabled for PCI devices, since it would
1842 : * break the PCI requirement for free-flowing writes and may lead to
1843 : * deadlock. We expect PCI devices to support ATS and PRI if they want to
1844 : * be fault-tolerant, so there's no ACPI binding to describe anything else,
1845 : * even when a "PCI" device turns out to be a regular old SoC device
1846 : * dressed up as a RCiEP and normal rules don't apply.
1847 : */
1848 0 : static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
1849 : {
1850 0 : struct property_entry properties[] = {
1851 : PROPERTY_ENTRY_BOOL("dma-can-stall"),
1852 : {},
1853 : };
1854 :
1855 0 : if (pdev->revision != 0x21 && pdev->revision != 0x30)
1856 0 : return;
1857 :
1858 0 : pdev->pasid_no_tlp = 1;
1859 :
1860 : /*
1861 : * Set the dma-can-stall property on ACPI platforms. Device tree
1862 : * can set it directly.
1863 : */
1864 0 : if (!pdev->dev.of_node &&
1865 0 : device_create_managed_software_node(&pdev->dev, properties, NULL))
1866 0 : pci_warn(pdev, "could not add stall property");
1867 : }
1868 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1869 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1870 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1871 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1872 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1873 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
1874 :
1875 : /*
1876 : * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1877 : * together on certain PXH-based systems.
1878 : */
1879 0 : static void quirk_pcie_pxh(struct pci_dev *dev)
1880 : {
1881 0 : dev->no_msi = 1;
1882 0 : pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1883 0 : }
1884 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1885 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1886 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1887 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1888 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1889 :
1890 : /*
1891 : * Some Intel PCI Express chipsets have trouble with downstream device
1892 : * power management.
1893 : */
1894 0 : static void quirk_intel_pcie_pm(struct pci_dev *dev)
1895 : {
1896 0 : pci_pm_d3hot_delay = 120;
1897 0 : dev->no_d1d2 = 1;
1898 0 : }
1899 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1900 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1901 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1902 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1903 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1904 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1905 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1906 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1907 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1908 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1909 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1910 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1911 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1912 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1913 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1914 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1915 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1916 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1917 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1918 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1919 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1920 :
1921 : static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1922 : {
1923 0 : if (dev->d3hot_delay >= delay)
1924 : return;
1925 :
1926 0 : dev->d3hot_delay = delay;
1927 0 : pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1928 : dev->d3hot_delay);
1929 : }
1930 :
1931 0 : static void quirk_radeon_pm(struct pci_dev *dev)
1932 : {
1933 0 : if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1934 : dev->subsystem_device == 0x00e2)
1935 : quirk_d3hot_delay(dev, 20);
1936 0 : }
1937 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1938 :
1939 : /*
1940 : * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1941 : * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1942 : *
1943 : * The kernel attempts to transition these devices to D3cold, but that seems
1944 : * to be ineffective on the platforms in question; the PCI device appears to
1945 : * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1946 : * extended delay in order to succeed.
1947 : */
1948 0 : static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1949 : {
1950 0 : quirk_d3hot_delay(dev, 20);
1951 0 : }
1952 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1953 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1954 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
1955 :
1956 : #ifdef CONFIG_X86_IO_APIC
1957 : static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1958 : {
1959 : noioapicreroute = 1;
1960 : pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1961 :
1962 : return 0;
1963 : }
1964 :
1965 : static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1966 : /*
1967 : * Systems to exclude from boot interrupt reroute quirks
1968 : */
1969 : {
1970 : .callback = dmi_disable_ioapicreroute,
1971 : .ident = "ASUSTek Computer INC. M2N-LR",
1972 : .matches = {
1973 : DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1974 : DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1975 : },
1976 : },
1977 : {}
1978 : };
1979 :
1980 : /*
1981 : * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1982 : * remap the original interrupt in the Linux kernel to the boot interrupt, so
1983 : * that a PCI device's interrupt handler is installed on the boot interrupt
1984 : * line instead.
1985 : */
1986 : static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1987 : {
1988 : dmi_check_system(boot_interrupt_dmi_table);
1989 : if (noioapicquirk || noioapicreroute)
1990 : return;
1991 :
1992 : dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1993 : pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1994 : dev->vendor, dev->device);
1995 : }
1996 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1997 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1998 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1999 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2000 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2001 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2002 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2003 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2004 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2005 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2006 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2007 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2008 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2009 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2010 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2011 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2012 :
2013 : /*
2014 : * On some chipsets we can disable the generation of legacy INTx boot
2015 : * interrupts.
2016 : */
2017 :
2018 : /*
2019 : * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2020 : * 300641-004US, section 5.7.3.
2021 : *
2022 : * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2023 : * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2024 : * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2025 : * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2026 : * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2027 : * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2028 : * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2029 : * Core IO on Xeon D-1500, see Intel order no 332051-001.
2030 : * Core IO on Xeon Scalable, see Intel order no 610950.
2031 : */
2032 : #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2033 : #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
2034 :
2035 : #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2036 : #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
2037 :
2038 : static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
2039 : {
2040 : u16 pci_config_word;
2041 : u32 pci_config_dword;
2042 :
2043 : if (noioapicquirk)
2044 : return;
2045 :
2046 : switch (dev->device) {
2047 : case PCI_DEVICE_ID_INTEL_ESB_10:
2048 : pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2049 : &pci_config_word);
2050 : pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2051 : pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2052 : pci_config_word);
2053 : break;
2054 : case 0x3c28: /* Xeon E5 1600/2600/4600 */
2055 : case 0x0e28: /* Xeon E5/E7 V2 */
2056 : case 0x2f28: /* Xeon E5/E7 V3,V4 */
2057 : case 0x6f28: /* Xeon D-1500 */
2058 : case 0x2034: /* Xeon Scalable Family */
2059 : pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2060 : &pci_config_dword);
2061 : pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2062 : pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2063 : pci_config_dword);
2064 : break;
2065 : default:
2066 : return;
2067 : }
2068 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2069 : dev->vendor, dev->device);
2070 : }
2071 : /*
2072 : * Device 29 Func 5 Device IDs of IO-APIC
2073 : * containing ABAR—APIC1 Alternate Base Address Register
2074 : */
2075 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2076 : quirk_disable_intel_boot_interrupt);
2077 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2078 : quirk_disable_intel_boot_interrupt);
2079 :
2080 : /*
2081 : * Device 5 Func 0 Device IDs of Core IO modules/hubs
2082 : * containing Coherent Interface Protocol Interrupt Control
2083 : *
2084 : * Device IDs obtained from volume 2 datasheets of commented
2085 : * families above.
2086 : */
2087 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2088 : quirk_disable_intel_boot_interrupt);
2089 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2090 : quirk_disable_intel_boot_interrupt);
2091 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2092 : quirk_disable_intel_boot_interrupt);
2093 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2094 : quirk_disable_intel_boot_interrupt);
2095 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2096 : quirk_disable_intel_boot_interrupt);
2097 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2098 : quirk_disable_intel_boot_interrupt);
2099 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2100 : quirk_disable_intel_boot_interrupt);
2101 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2102 : quirk_disable_intel_boot_interrupt);
2103 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2104 : quirk_disable_intel_boot_interrupt);
2105 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2106 : quirk_disable_intel_boot_interrupt);
2107 :
2108 : /* Disable boot interrupts on HT-1000 */
2109 : #define BC_HT1000_FEATURE_REG 0x64
2110 : #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2111 : #define BC_HT1000_MAP_IDX 0xC00
2112 : #define BC_HT1000_MAP_DATA 0xC01
2113 :
2114 : static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2115 : {
2116 : u32 pci_config_dword;
2117 : u8 irq;
2118 :
2119 : if (noioapicquirk)
2120 : return;
2121 :
2122 : pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2123 : pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2124 : BC_HT1000_PIC_REGS_ENABLE);
2125 :
2126 : for (irq = 0x10; irq < 0x10 + 32; irq++) {
2127 : outb(irq, BC_HT1000_MAP_IDX);
2128 : outb(0x00, BC_HT1000_MAP_DATA);
2129 : }
2130 :
2131 : pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2132 :
2133 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2134 : dev->vendor, dev->device);
2135 : }
2136 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2137 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2138 :
2139 : /* Disable boot interrupts on AMD and ATI chipsets */
2140 :
2141 : /*
2142 : * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2143 : * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2144 : * (due to an erratum).
2145 : */
2146 : #define AMD_813X_MISC 0x40
2147 : #define AMD_813X_NOIOAMODE (1<<0)
2148 : #define AMD_813X_REV_B1 0x12
2149 : #define AMD_813X_REV_B2 0x13
2150 :
2151 : static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2152 : {
2153 : u32 pci_config_dword;
2154 :
2155 : if (noioapicquirk)
2156 : return;
2157 : if ((dev->revision == AMD_813X_REV_B1) ||
2158 : (dev->revision == AMD_813X_REV_B2))
2159 : return;
2160 :
2161 : pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2162 : pci_config_dword &= ~AMD_813X_NOIOAMODE;
2163 : pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2164 :
2165 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2166 : dev->vendor, dev->device);
2167 : }
2168 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2169 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2170 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2171 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2172 :
2173 : #define AMD_8111_PCI_IRQ_ROUTING 0x56
2174 :
2175 : static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2176 : {
2177 : u16 pci_config_word;
2178 :
2179 : if (noioapicquirk)
2180 : return;
2181 :
2182 : pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2183 : if (!pci_config_word) {
2184 : pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2185 : dev->vendor, dev->device);
2186 : return;
2187 : }
2188 : pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2189 : pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2190 : dev->vendor, dev->device);
2191 : }
2192 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2193 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2194 : #endif /* CONFIG_X86_IO_APIC */
2195 :
2196 : /*
2197 : * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2198 : * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2199 : * Re-allocate the region if needed...
2200 : */
2201 0 : static void quirk_tc86c001_ide(struct pci_dev *dev)
2202 : {
2203 0 : struct resource *r = &dev->resource[0];
2204 :
2205 0 : if (r->start & 0x8) {
2206 0 : r->flags |= IORESOURCE_UNSET;
2207 0 : r->start = 0;
2208 0 : r->end = 0xf;
2209 : }
2210 0 : }
2211 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2212 : PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2213 : quirk_tc86c001_ide);
2214 :
2215 : /*
2216 : * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2217 : * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2218 : * being read correctly if bit 7 of the base address is set.
2219 : * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2220 : * Re-allocate the regions to a 256-byte boundary if necessary.
2221 : */
2222 0 : static void quirk_plx_pci9050(struct pci_dev *dev)
2223 : {
2224 : unsigned int bar;
2225 :
2226 : /* Fixed in revision 2 (PCI 9052). */
2227 0 : if (dev->revision >= 2)
2228 : return;
2229 0 : for (bar = 0; bar <= 1; bar++)
2230 0 : if (pci_resource_len(dev, bar) == 0x80 &&
2231 0 : (pci_resource_start(dev, bar) & 0x80)) {
2232 0 : struct resource *r = &dev->resource[bar];
2233 0 : pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2234 : bar);
2235 0 : r->flags |= IORESOURCE_UNSET;
2236 0 : r->start = 0;
2237 0 : r->end = 0xff;
2238 : }
2239 : }
2240 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2241 : quirk_plx_pci9050);
2242 : /*
2243 : * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2244 : * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2245 : * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2246 : * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2247 : *
2248 : * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2249 : * driver.
2250 : */
2251 : DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2252 : DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2253 :
2254 0 : static void quirk_netmos(struct pci_dev *dev)
2255 : {
2256 0 : unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2257 0 : unsigned int num_serial = dev->subsystem_device & 0xf;
2258 :
2259 : /*
2260 : * These Netmos parts are multiport serial devices with optional
2261 : * parallel ports. Even when parallel ports are present, they
2262 : * are identified as class SERIAL, which means the serial driver
2263 : * will claim them. To prevent this, mark them as class OTHER.
2264 : * These combo devices should be claimed by parport_serial.
2265 : *
2266 : * The subdevice ID is of the form 0x00PS, where <P> is the number
2267 : * of parallel ports and <S> is the number of serial ports.
2268 : */
2269 0 : switch (dev->device) {
2270 : case PCI_DEVICE_ID_NETMOS_9835:
2271 : /* Well, this rule doesn't hold for the following 9835 device */
2272 0 : if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2273 : dev->subsystem_device == 0x0299)
2274 : return;
2275 : fallthrough;
2276 : case PCI_DEVICE_ID_NETMOS_9735:
2277 : case PCI_DEVICE_ID_NETMOS_9745:
2278 : case PCI_DEVICE_ID_NETMOS_9845:
2279 : case PCI_DEVICE_ID_NETMOS_9855:
2280 0 : if (num_parallel) {
2281 0 : pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2282 : dev->device, num_parallel, num_serial);
2283 0 : dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2284 0 : (dev->class & 0xff);
2285 : }
2286 : }
2287 : }
2288 : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2289 : PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2290 :
2291 0 : static void quirk_e100_interrupt(struct pci_dev *dev)
2292 : {
2293 : u16 command, pmcsr;
2294 : u8 __iomem *csr;
2295 : u8 cmd_hi;
2296 :
2297 0 : switch (dev->device) {
2298 : /* PCI IDs taken from drivers/net/e100.c */
2299 : case 0x1029:
2300 : case 0x1030 ... 0x1034:
2301 : case 0x1038 ... 0x103E:
2302 : case 0x1050 ... 0x1057:
2303 : case 0x1059:
2304 : case 0x1064 ... 0x106B:
2305 : case 0x1091 ... 0x1095:
2306 : case 0x1209:
2307 : case 0x1229:
2308 : case 0x2449:
2309 : case 0x2459:
2310 : case 0x245D:
2311 : case 0x27DC:
2312 : break;
2313 : default:
2314 0 : return;
2315 : }
2316 :
2317 : /*
2318 : * Some firmware hands off the e100 with interrupts enabled,
2319 : * which can cause a flood of interrupts if packets are
2320 : * received before the driver attaches to the device. So
2321 : * disable all e100 interrupts here. The driver will
2322 : * re-enable them when it's ready.
2323 : */
2324 0 : pci_read_config_word(dev, PCI_COMMAND, &command);
2325 :
2326 0 : if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2327 : return;
2328 :
2329 : /*
2330 : * Check that the device is in the D0 power state. If it's not,
2331 : * there is no point to look any further.
2332 : */
2333 0 : if (dev->pm_cap) {
2334 0 : pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2335 0 : if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2336 : return;
2337 : }
2338 :
2339 : /* Convert from PCI bus to resource space. */
2340 0 : csr = ioremap(pci_resource_start(dev, 0), 8);
2341 0 : if (!csr) {
2342 0 : pci_warn(dev, "Can't map e100 registers\n");
2343 0 : return;
2344 : }
2345 :
2346 0 : cmd_hi = readb(csr + 3);
2347 0 : if (cmd_hi == 0) {
2348 0 : pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2349 0 : writeb(1, csr + 3);
2350 : }
2351 :
2352 0 : iounmap(csr);
2353 : }
2354 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2355 : PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2356 :
2357 : /*
2358 : * The 82575 and 82598 may experience data corruption issues when transitioning
2359 : * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2360 : */
2361 0 : static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2362 : {
2363 0 : pci_info(dev, "Disabling L0s\n");
2364 0 : pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2365 0 : }
2366 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2367 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2368 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2369 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2370 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2371 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2372 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2373 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2374 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2375 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2376 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2377 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2378 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2379 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2380 :
2381 0 : static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2382 : {
2383 0 : pci_info(dev, "Disabling ASPM L0s/L1\n");
2384 0 : pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2385 0 : }
2386 :
2387 : /*
2388 : * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2389 : * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2390 : * disable both L0s and L1 for now to be safe.
2391 : */
2392 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2393 :
2394 : /*
2395 : * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2396 : * Link bit cleared after starting the link retrain process to allow this
2397 : * process to finish.
2398 : *
2399 : * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2400 : * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2401 : */
2402 0 : static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2403 : {
2404 0 : dev->clear_retrain_link = 1;
2405 0 : pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2406 0 : }
2407 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2408 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2409 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2410 :
2411 0 : static void fixup_rev1_53c810(struct pci_dev *dev)
2412 : {
2413 0 : u32 class = dev->class;
2414 :
2415 : /*
2416 : * rev 1 ncr53c810 chips don't set the class at all which means
2417 : * they don't get their resources remapped. Fix that here.
2418 : */
2419 0 : if (class)
2420 : return;
2421 :
2422 0 : dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2423 0 : pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2424 : class, dev->class);
2425 : }
2426 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2427 :
2428 : /* Enable 1k I/O space granularity on the Intel P64H2 */
2429 0 : static void quirk_p64h2_1k_io(struct pci_dev *dev)
2430 : {
2431 : u16 en1k;
2432 :
2433 0 : pci_read_config_word(dev, 0x40, &en1k);
2434 :
2435 0 : if (en1k & 0x200) {
2436 0 : pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2437 0 : dev->io_window_1k = 1;
2438 : }
2439 0 : }
2440 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2441 :
2442 : /*
2443 : * Under some circumstances, AER is not linked with extended capabilities.
2444 : * Force it to be linked by setting the corresponding control bit in the
2445 : * config space.
2446 : */
2447 0 : static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2448 : {
2449 : uint8_t b;
2450 :
2451 0 : if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2452 0 : if (!(b & 0x20)) {
2453 0 : pci_write_config_byte(dev, 0xf41, b | 0x20);
2454 0 : pci_info(dev, "Linking AER extended capability\n");
2455 : }
2456 : }
2457 0 : }
2458 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2459 : quirk_nvidia_ck804_pcie_aer_ext_cap);
2460 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2461 : quirk_nvidia_ck804_pcie_aer_ext_cap);
2462 :
2463 0 : static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2464 : {
2465 : /*
2466 : * Disable PCI Bus Parking and PCI Master read caching on CX700
2467 : * which causes unspecified timing errors with a VT6212L on the PCI
2468 : * bus leading to USB2.0 packet loss.
2469 : *
2470 : * This quirk is only enabled if a second (on the external PCI bus)
2471 : * VT6212L is found -- the CX700 core itself also contains a USB
2472 : * host controller with the same PCI ID as the VT6212L.
2473 : */
2474 :
2475 : /* Count VT6212L instances */
2476 0 : struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2477 : PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2478 : uint8_t b;
2479 :
2480 : /*
2481 : * p should contain the first (internal) VT6212L -- see if we have
2482 : * an external one by searching again.
2483 : */
2484 0 : p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2485 0 : if (!p)
2486 0 : return;
2487 0 : pci_dev_put(p);
2488 :
2489 0 : if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2490 0 : if (b & 0x40) {
2491 : /* Turn off PCI Bus Parking */
2492 0 : pci_write_config_byte(dev, 0x76, b ^ 0x40);
2493 :
2494 0 : pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2495 : }
2496 : }
2497 :
2498 0 : if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2499 0 : if (b != 0) {
2500 : /* Turn off PCI Master read caching */
2501 0 : pci_write_config_byte(dev, 0x72, 0x0);
2502 :
2503 : /* Set PCI Master Bus time-out to "1x16 PCLK" */
2504 0 : pci_write_config_byte(dev, 0x75, 0x1);
2505 :
2506 : /* Disable "Read FIFO Timer" */
2507 0 : pci_write_config_byte(dev, 0x77, 0x0);
2508 :
2509 0 : pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2510 : }
2511 : }
2512 : }
2513 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2514 :
2515 0 : static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2516 : {
2517 : u32 rev;
2518 :
2519 0 : pci_read_config_dword(dev, 0xf4, &rev);
2520 :
2521 : /* Only CAP the MRRS if the device is a 5719 A0 */
2522 0 : if (rev == 0x05719000) {
2523 0 : int readrq = pcie_get_readrq(dev);
2524 0 : if (readrq > 2048)
2525 0 : pcie_set_readrq(dev, 2048);
2526 : }
2527 0 : }
2528 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2529 : PCI_DEVICE_ID_TIGON3_5719,
2530 : quirk_brcm_5719_limit_mrrs);
2531 :
2532 : /*
2533 : * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2534 : * hide device 6 which configures the overflow device access containing the
2535 : * DRBs - this is where we expose device 6.
2536 : * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2537 : */
2538 0 : static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2539 : {
2540 : u8 reg;
2541 :
2542 0 : if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2543 0 : pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2544 0 : pci_write_config_byte(dev, 0xF4, reg | 0x02);
2545 : }
2546 0 : }
2547 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2548 : quirk_unhide_mch_dev6);
2549 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2550 : quirk_unhide_mch_dev6);
2551 :
2552 : #ifdef CONFIG_PCI_MSI
2553 : /*
2554 : * Some chipsets do not support MSI. We cannot easily rely on setting
2555 : * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2556 : * other buses controlled by the chipset even if Linux is not aware of it.
2557 : * Instead of setting the flag on all buses in the machine, simply disable
2558 : * MSI globally.
2559 : */
2560 0 : static void quirk_disable_all_msi(struct pci_dev *dev)
2561 : {
2562 0 : pci_no_msi();
2563 0 : pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2564 0 : }
2565 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2566 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2567 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2568 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2569 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2570 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2571 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2572 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2573 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2574 :
2575 : /* Disable MSI on chipsets that are known to not support it */
2576 0 : static void quirk_disable_msi(struct pci_dev *dev)
2577 : {
2578 0 : if (dev->subordinate) {
2579 0 : pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2580 0 : dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2581 : }
2582 0 : }
2583 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2584 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2585 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2586 :
2587 : /*
2588 : * The APC bridge device in AMD 780 family northbridges has some random
2589 : * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2590 : * we use the possible vendor/device IDs of the host bridge for the
2591 : * declared quirk, and search for the APC bridge by slot number.
2592 : */
2593 0 : static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2594 : {
2595 : struct pci_dev *apc_bridge;
2596 :
2597 0 : apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2598 0 : if (apc_bridge) {
2599 0 : if (apc_bridge->device == 0x9602)
2600 : quirk_disable_msi(apc_bridge);
2601 0 : pci_dev_put(apc_bridge);
2602 : }
2603 0 : }
2604 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2605 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2606 :
2607 : /*
2608 : * Go through the list of HyperTransport capabilities and return 1 if a HT
2609 : * MSI capability is found and enabled.
2610 : */
2611 0 : static int msi_ht_cap_enabled(struct pci_dev *dev)
2612 : {
2613 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2614 :
2615 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2616 0 : while (pos && ttl--) {
2617 : u8 flags;
2618 :
2619 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2620 : &flags) == 0) {
2621 0 : pci_info(dev, "Found %s HT MSI Mapping\n",
2622 : flags & HT_MSI_FLAGS_ENABLE ?
2623 : "enabled" : "disabled");
2624 0 : return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2625 : }
2626 :
2627 0 : pos = pci_find_next_ht_capability(dev, pos,
2628 : HT_CAPTYPE_MSI_MAPPING);
2629 : }
2630 : return 0;
2631 : }
2632 :
2633 : /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2634 0 : static void quirk_msi_ht_cap(struct pci_dev *dev)
2635 : {
2636 0 : if (!msi_ht_cap_enabled(dev))
2637 : quirk_disable_msi(dev);
2638 0 : }
2639 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2640 : quirk_msi_ht_cap);
2641 :
2642 : /*
2643 : * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2644 : * if the MSI capability is set in any of these mappings.
2645 : */
2646 0 : static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2647 : {
2648 : struct pci_dev *pdev;
2649 :
2650 : /*
2651 : * Check HT MSI cap on this chipset and the root one. A single one
2652 : * having MSI is enough to be sure that MSI is supported.
2653 : */
2654 0 : pdev = pci_get_slot(dev->bus, 0);
2655 0 : if (!pdev)
2656 : return;
2657 0 : if (!msi_ht_cap_enabled(pdev))
2658 0 : quirk_msi_ht_cap(dev);
2659 0 : pci_dev_put(pdev);
2660 : }
2661 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2662 : quirk_nvidia_ck804_msi_ht_cap);
2663 :
2664 : /* Force enable MSI mapping capability on HT bridges */
2665 0 : static void ht_enable_msi_mapping(struct pci_dev *dev)
2666 : {
2667 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2668 :
2669 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2670 0 : while (pos && ttl--) {
2671 : u8 flags;
2672 :
2673 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2674 : &flags) == 0) {
2675 0 : pci_info(dev, "Enabling HT MSI Mapping\n");
2676 :
2677 0 : pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2678 : flags | HT_MSI_FLAGS_ENABLE);
2679 : }
2680 0 : pos = pci_find_next_ht_capability(dev, pos,
2681 : HT_CAPTYPE_MSI_MAPPING);
2682 : }
2683 0 : }
2684 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2685 : PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2686 : ht_enable_msi_mapping);
2687 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2688 : ht_enable_msi_mapping);
2689 :
2690 : /*
2691 : * The P5N32-SLI motherboards from Asus have a problem with MSI
2692 : * for the MCP55 NIC. It is not yet determined whether the MSI problem
2693 : * also affects other devices. As for now, turn off MSI for this device.
2694 : */
2695 0 : static void nvenet_msi_disable(struct pci_dev *dev)
2696 : {
2697 0 : const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2698 :
2699 : if (board_name &&
2700 : (strstr(board_name, "P5N32-SLI PREMIUM") ||
2701 : strstr(board_name, "P5N32-E SLI"))) {
2702 : pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2703 : dev->no_msi = 1;
2704 : }
2705 0 : }
2706 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2707 : PCI_DEVICE_ID_NVIDIA_NVENET_15,
2708 : nvenet_msi_disable);
2709 :
2710 : /*
2711 : * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2712 : * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2713 : * generate MSI interrupts for PME and AER events instead only INTx interrupts
2714 : * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2715 : * for other events, since PCIe specification doesn't support using a mix of
2716 : * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2717 : * service drivers registering their respective ISRs for MSIs.
2718 : */
2719 0 : static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2720 : {
2721 0 : dev->no_msi = 1;
2722 0 : }
2723 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2724 : PCI_CLASS_BRIDGE_PCI, 8,
2725 : pci_quirk_nvidia_tegra_disable_rp_msi);
2726 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2727 : PCI_CLASS_BRIDGE_PCI, 8,
2728 : pci_quirk_nvidia_tegra_disable_rp_msi);
2729 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2730 : PCI_CLASS_BRIDGE_PCI, 8,
2731 : pci_quirk_nvidia_tegra_disable_rp_msi);
2732 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2733 : PCI_CLASS_BRIDGE_PCI, 8,
2734 : pci_quirk_nvidia_tegra_disable_rp_msi);
2735 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2736 : PCI_CLASS_BRIDGE_PCI, 8,
2737 : pci_quirk_nvidia_tegra_disable_rp_msi);
2738 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2739 : PCI_CLASS_BRIDGE_PCI, 8,
2740 : pci_quirk_nvidia_tegra_disable_rp_msi);
2741 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2742 : PCI_CLASS_BRIDGE_PCI, 8,
2743 : pci_quirk_nvidia_tegra_disable_rp_msi);
2744 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2745 : PCI_CLASS_BRIDGE_PCI, 8,
2746 : pci_quirk_nvidia_tegra_disable_rp_msi);
2747 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2748 : PCI_CLASS_BRIDGE_PCI, 8,
2749 : pci_quirk_nvidia_tegra_disable_rp_msi);
2750 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2751 : PCI_CLASS_BRIDGE_PCI, 8,
2752 : pci_quirk_nvidia_tegra_disable_rp_msi);
2753 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2754 : PCI_CLASS_BRIDGE_PCI, 8,
2755 : pci_quirk_nvidia_tegra_disable_rp_msi);
2756 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2757 : PCI_CLASS_BRIDGE_PCI, 8,
2758 : pci_quirk_nvidia_tegra_disable_rp_msi);
2759 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2760 : PCI_CLASS_BRIDGE_PCI, 8,
2761 : pci_quirk_nvidia_tegra_disable_rp_msi);
2762 :
2763 : /*
2764 : * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2765 : * config register. This register controls the routing of legacy
2766 : * interrupts from devices that route through the MCP55. If this register
2767 : * is misprogrammed, interrupts are only sent to the BSP, unlike
2768 : * conventional systems where the IRQ is broadcast to all online CPUs. Not
2769 : * having this register set properly prevents kdump from booting up
2770 : * properly, so let's make sure that we have it set correctly.
2771 : * Note that this is an undocumented register.
2772 : */
2773 0 : static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2774 : {
2775 : u32 cfg;
2776 :
2777 0 : if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2778 0 : return;
2779 :
2780 0 : pci_read_config_dword(dev, 0x74, &cfg);
2781 :
2782 0 : if (cfg & ((1 << 2) | (1 << 15))) {
2783 0 : pr_info("Rewriting IRQ routing register on MCP55\n");
2784 0 : cfg &= ~((1 << 2) | (1 << 15));
2785 0 : pci_write_config_dword(dev, 0x74, cfg);
2786 : }
2787 : }
2788 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2789 : PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2790 : nvbridge_check_legacy_irq_routing);
2791 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2792 : PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2793 : nvbridge_check_legacy_irq_routing);
2794 :
2795 0 : static int ht_check_msi_mapping(struct pci_dev *dev)
2796 : {
2797 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2798 0 : int found = 0;
2799 :
2800 : /* Check if there is HT MSI cap or enabled on this device */
2801 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2802 0 : while (pos && ttl--) {
2803 : u8 flags;
2804 :
2805 0 : if (found < 1)
2806 0 : found = 1;
2807 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2808 : &flags) == 0) {
2809 0 : if (flags & HT_MSI_FLAGS_ENABLE) {
2810 0 : if (found < 2) {
2811 0 : found = 2;
2812 0 : break;
2813 : }
2814 : }
2815 : }
2816 0 : pos = pci_find_next_ht_capability(dev, pos,
2817 : HT_CAPTYPE_MSI_MAPPING);
2818 : }
2819 :
2820 0 : return found;
2821 : }
2822 :
2823 0 : static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2824 : {
2825 : struct pci_dev *dev;
2826 : int pos;
2827 : int i, dev_no;
2828 0 : int found = 0;
2829 :
2830 0 : dev_no = host_bridge->devfn >> 3;
2831 0 : for (i = dev_no + 1; i < 0x20; i++) {
2832 0 : dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2833 0 : if (!dev)
2834 0 : continue;
2835 :
2836 : /* found next host bridge? */
2837 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2838 0 : if (pos != 0) {
2839 0 : pci_dev_put(dev);
2840 : break;
2841 : }
2842 :
2843 0 : if (ht_check_msi_mapping(dev)) {
2844 0 : found = 1;
2845 0 : pci_dev_put(dev);
2846 : break;
2847 : }
2848 0 : pci_dev_put(dev);
2849 : }
2850 :
2851 0 : return found;
2852 : }
2853 :
2854 : #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2855 : #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2856 :
2857 0 : static int is_end_of_ht_chain(struct pci_dev *dev)
2858 : {
2859 : int pos, ctrl_off;
2860 0 : int end = 0;
2861 : u16 flags, ctrl;
2862 :
2863 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2864 :
2865 0 : if (!pos)
2866 : goto out;
2867 :
2868 0 : pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2869 :
2870 0 : ctrl_off = ((flags >> 10) & 1) ?
2871 0 : PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2872 0 : pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2873 :
2874 0 : if (ctrl & (1 << 6))
2875 0 : end = 1;
2876 :
2877 : out:
2878 0 : return end;
2879 : }
2880 :
2881 0 : static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2882 : {
2883 : struct pci_dev *host_bridge;
2884 : int pos;
2885 : int i, dev_no;
2886 0 : int found = 0;
2887 :
2888 0 : dev_no = dev->devfn >> 3;
2889 0 : for (i = dev_no; i >= 0; i--) {
2890 0 : host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2891 0 : if (!host_bridge)
2892 0 : continue;
2893 :
2894 0 : pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2895 0 : if (pos != 0) {
2896 : found = 1;
2897 : break;
2898 : }
2899 0 : pci_dev_put(host_bridge);
2900 : }
2901 :
2902 0 : if (!found)
2903 : return;
2904 :
2905 : /* don't enable end_device/host_bridge with leaf directly here */
2906 0 : if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2907 0 : host_bridge_with_leaf(host_bridge))
2908 : goto out;
2909 :
2910 : /* root did that ! */
2911 0 : if (msi_ht_cap_enabled(host_bridge))
2912 : goto out;
2913 :
2914 0 : ht_enable_msi_mapping(dev);
2915 :
2916 : out:
2917 0 : pci_dev_put(host_bridge);
2918 : }
2919 :
2920 0 : static void ht_disable_msi_mapping(struct pci_dev *dev)
2921 : {
2922 0 : int pos, ttl = PCI_FIND_CAP_TTL;
2923 :
2924 0 : pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2925 0 : while (pos && ttl--) {
2926 : u8 flags;
2927 :
2928 0 : if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2929 : &flags) == 0) {
2930 0 : pci_info(dev, "Disabling HT MSI Mapping\n");
2931 :
2932 0 : pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2933 0 : flags & ~HT_MSI_FLAGS_ENABLE);
2934 : }
2935 0 : pos = pci_find_next_ht_capability(dev, pos,
2936 : HT_CAPTYPE_MSI_MAPPING);
2937 : }
2938 0 : }
2939 :
2940 0 : static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2941 : {
2942 : struct pci_dev *host_bridge;
2943 : int pos;
2944 : int found;
2945 :
2946 0 : if (!pci_msi_enabled())
2947 : return;
2948 :
2949 : /* check if there is HT MSI cap or enabled on this device */
2950 0 : found = ht_check_msi_mapping(dev);
2951 :
2952 : /* no HT MSI CAP */
2953 0 : if (found == 0)
2954 : return;
2955 :
2956 : /*
2957 : * HT MSI mapping should be disabled on devices that are below
2958 : * a non-Hypertransport host bridge. Locate the host bridge...
2959 : */
2960 0 : host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2961 : PCI_DEVFN(0, 0));
2962 0 : if (host_bridge == NULL) {
2963 0 : pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2964 0 : return;
2965 : }
2966 :
2967 0 : pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2968 0 : if (pos != 0) {
2969 : /* Host bridge is to HT */
2970 0 : if (found == 1) {
2971 : /* it is not enabled, try to enable it */
2972 0 : if (all)
2973 0 : ht_enable_msi_mapping(dev);
2974 : else
2975 0 : nv_ht_enable_msi_mapping(dev);
2976 : }
2977 : goto out;
2978 : }
2979 :
2980 : /* HT MSI is not enabled */
2981 0 : if (found == 1)
2982 : goto out;
2983 :
2984 : /* Host bridge is not to HT, disable HT MSI mapping on this device */
2985 0 : ht_disable_msi_mapping(dev);
2986 :
2987 : out:
2988 0 : pci_dev_put(host_bridge);
2989 : }
2990 :
2991 0 : static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2992 : {
2993 0 : return __nv_msi_ht_cap_quirk(dev, 1);
2994 : }
2995 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2996 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2997 :
2998 0 : static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2999 : {
3000 0 : return __nv_msi_ht_cap_quirk(dev, 0);
3001 : }
3002 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3003 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3004 :
3005 0 : static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
3006 : {
3007 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3008 0 : }
3009 :
3010 0 : static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
3011 : {
3012 : struct pci_dev *p;
3013 :
3014 : /*
3015 : * SB700 MSI issue will be fixed at HW level from revision A21;
3016 : * we need check PCI REVISION ID of SMBus controller to get SB700
3017 : * revision.
3018 : */
3019 0 : p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3020 : NULL);
3021 0 : if (!p)
3022 : return;
3023 :
3024 0 : if ((p->revision < 0x3B) && (p->revision >= 0x30))
3025 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3026 0 : pci_dev_put(p);
3027 : }
3028 :
3029 0 : static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
3030 : {
3031 : /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
3032 0 : if (dev->revision < 0x18) {
3033 0 : pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
3034 0 : dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3035 : }
3036 0 : }
3037 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3038 : PCI_DEVICE_ID_TIGON3_5780,
3039 : quirk_msi_intx_disable_bug);
3040 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3041 : PCI_DEVICE_ID_TIGON3_5780S,
3042 : quirk_msi_intx_disable_bug);
3043 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3044 : PCI_DEVICE_ID_TIGON3_5714,
3045 : quirk_msi_intx_disable_bug);
3046 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3047 : PCI_DEVICE_ID_TIGON3_5714S,
3048 : quirk_msi_intx_disable_bug);
3049 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3050 : PCI_DEVICE_ID_TIGON3_5715,
3051 : quirk_msi_intx_disable_bug);
3052 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3053 : PCI_DEVICE_ID_TIGON3_5715S,
3054 : quirk_msi_intx_disable_bug);
3055 :
3056 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3057 : quirk_msi_intx_disable_ati_bug);
3058 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3059 : quirk_msi_intx_disable_ati_bug);
3060 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3061 : quirk_msi_intx_disable_ati_bug);
3062 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3063 : quirk_msi_intx_disable_ati_bug);
3064 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3065 : quirk_msi_intx_disable_ati_bug);
3066 :
3067 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3068 : quirk_msi_intx_disable_bug);
3069 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3070 : quirk_msi_intx_disable_bug);
3071 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3072 : quirk_msi_intx_disable_bug);
3073 :
3074 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3075 : quirk_msi_intx_disable_bug);
3076 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3077 : quirk_msi_intx_disable_bug);
3078 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3079 : quirk_msi_intx_disable_bug);
3080 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3081 : quirk_msi_intx_disable_bug);
3082 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3083 : quirk_msi_intx_disable_bug);
3084 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3085 : quirk_msi_intx_disable_bug);
3086 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3087 : quirk_msi_intx_disable_qca_bug);
3088 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3089 : quirk_msi_intx_disable_qca_bug);
3090 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3091 : quirk_msi_intx_disable_qca_bug);
3092 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3093 : quirk_msi_intx_disable_qca_bug);
3094 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3095 : quirk_msi_intx_disable_qca_bug);
3096 :
3097 : /*
3098 : * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3099 : * should be disabled on platforms where the device (mistakenly) advertises it.
3100 : *
3101 : * Notice that this quirk also disables MSI (which may work, but hasn't been
3102 : * tested), since currently there is no standard way to disable only MSI-X.
3103 : *
3104 : * The 0031 device id is reused for other non Root Port device types,
3105 : * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3106 : */
3107 0 : static void quirk_al_msi_disable(struct pci_dev *dev)
3108 : {
3109 0 : dev->no_msi = 1;
3110 0 : pci_warn(dev, "Disabling MSI/MSI-X\n");
3111 0 : }
3112 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3113 : PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3114 : #endif /* CONFIG_PCI_MSI */
3115 :
3116 : /*
3117 : * Allow manual resource allocation for PCI hotplug bridges via
3118 : * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3119 : * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3120 : * allocate resources when hotplug device is inserted and PCI bus is
3121 : * rescanned.
3122 : */
3123 0 : static void quirk_hotplug_bridge(struct pci_dev *dev)
3124 : {
3125 0 : dev->is_hotplug_bridge = 1;
3126 0 : }
3127 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3128 :
3129 : /*
3130 : * This is a quirk for the Ricoh MMC controller found as a part of some
3131 : * multifunction chips.
3132 : *
3133 : * This is very similar and based on the ricoh_mmc driver written by
3134 : * Philip Langdale. Thank you for these magic sequences.
3135 : *
3136 : * These chips implement the four main memory card controllers (SD, MMC,
3137 : * MS, xD) and one or both of CardBus or FireWire.
3138 : *
3139 : * It happens that they implement SD and MMC support as separate
3140 : * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3141 : * cards but the chip detects MMC cards in hardware and directs them to the
3142 : * MMC controller - so the SDHCI driver never sees them.
3143 : *
3144 : * To get around this, we must disable the useless MMC controller. At that
3145 : * point, the SDHCI controller will start seeing them. It seems to be the
3146 : * case that the relevant PCI registers to deactivate the MMC controller
3147 : * live on PCI function 0, which might be the CardBus controller or the
3148 : * FireWire controller, depending on the particular chip in question
3149 : *
3150 : * This has to be done early, because as soon as we disable the MMC controller
3151 : * other PCI functions shift up one level, e.g. function #2 becomes function
3152 : * #1, and this will confuse the PCI core.
3153 : */
3154 : #ifdef CONFIG_MMC_RICOH_MMC
3155 : static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3156 : {
3157 : u8 write_enable;
3158 : u8 write_target;
3159 : u8 disable;
3160 :
3161 : /*
3162 : * Disable via CardBus interface
3163 : *
3164 : * This must be done via function #0
3165 : */
3166 : if (PCI_FUNC(dev->devfn))
3167 : return;
3168 :
3169 : pci_read_config_byte(dev, 0xB7, &disable);
3170 : if (disable & 0x02)
3171 : return;
3172 :
3173 : pci_read_config_byte(dev, 0x8E, &write_enable);
3174 : pci_write_config_byte(dev, 0x8E, 0xAA);
3175 : pci_read_config_byte(dev, 0x8D, &write_target);
3176 : pci_write_config_byte(dev, 0x8D, 0xB7);
3177 : pci_write_config_byte(dev, 0xB7, disable | 0x02);
3178 : pci_write_config_byte(dev, 0x8E, write_enable);
3179 : pci_write_config_byte(dev, 0x8D, write_target);
3180 :
3181 : pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3182 : pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3183 : }
3184 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3185 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3186 :
3187 : static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3188 : {
3189 : u8 write_enable;
3190 : u8 disable;
3191 :
3192 : /*
3193 : * Disable via FireWire interface
3194 : *
3195 : * This must be done via function #0
3196 : */
3197 : if (PCI_FUNC(dev->devfn))
3198 : return;
3199 : /*
3200 : * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3201 : * certain types of SD/MMC cards. Lowering the SD base clock
3202 : * frequency from 200Mhz to 50Mhz fixes this issue.
3203 : *
3204 : * 0x150 - SD2.0 mode enable for changing base clock
3205 : * frequency to 50Mhz
3206 : * 0xe1 - Base clock frequency
3207 : * 0x32 - 50Mhz new clock frequency
3208 : * 0xf9 - Key register for 0x150
3209 : * 0xfc - key register for 0xe1
3210 : */
3211 : if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3212 : dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3213 : pci_write_config_byte(dev, 0xf9, 0xfc);
3214 : pci_write_config_byte(dev, 0x150, 0x10);
3215 : pci_write_config_byte(dev, 0xf9, 0x00);
3216 : pci_write_config_byte(dev, 0xfc, 0x01);
3217 : pci_write_config_byte(dev, 0xe1, 0x32);
3218 : pci_write_config_byte(dev, 0xfc, 0x00);
3219 :
3220 : pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3221 : }
3222 :
3223 : pci_read_config_byte(dev, 0xCB, &disable);
3224 :
3225 : if (disable & 0x02)
3226 : return;
3227 :
3228 : pci_read_config_byte(dev, 0xCA, &write_enable);
3229 : pci_write_config_byte(dev, 0xCA, 0x57);
3230 : pci_write_config_byte(dev, 0xCB, disable | 0x02);
3231 : pci_write_config_byte(dev, 0xCA, write_enable);
3232 :
3233 : pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3234 : pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3235 :
3236 : }
3237 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3238 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3239 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3240 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3241 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3242 : DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3243 : #endif /*CONFIG_MMC_RICOH_MMC*/
3244 :
3245 : #ifdef CONFIG_DMAR_TABLE
3246 : #define VTUNCERRMSK_REG 0x1ac
3247 : #define VTD_MSK_SPEC_ERRORS (1 << 31)
3248 : /*
3249 : * This is a quirk for masking VT-d spec-defined errors to platform error
3250 : * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3251 : * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3252 : * on the RAS config settings of the platform) when a VT-d fault happens.
3253 : * The resulting SMI caused the system to hang.
3254 : *
3255 : * VT-d spec-related errors are already handled by the VT-d OS code, so no
3256 : * need to report the same error through other channels.
3257 : */
3258 : static void vtd_mask_spec_errors(struct pci_dev *dev)
3259 : {
3260 : u32 word;
3261 :
3262 : pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3263 : pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3264 : }
3265 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3266 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3267 : #endif
3268 :
3269 0 : static void fixup_ti816x_class(struct pci_dev *dev)
3270 : {
3271 0 : u32 class = dev->class;
3272 :
3273 : /* TI 816x devices do not have class code set when in PCIe boot mode */
3274 0 : dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3275 0 : pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3276 : class, dev->class);
3277 0 : }
3278 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3279 : PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3280 :
3281 : /*
3282 : * Some PCIe devices do not work reliably with the claimed maximum
3283 : * payload size supported.
3284 : */
3285 0 : static void fixup_mpss_256(struct pci_dev *dev)
3286 : {
3287 0 : dev->pcie_mpss = 1; /* 256 bytes */
3288 0 : }
3289 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3290 : PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3291 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3292 : PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3293 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3294 : PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3295 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3296 :
3297 : /*
3298 : * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3299 : * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3300 : * Since there is no way of knowing what the PCIe MPS on each fabric will be
3301 : * until all of the devices are discovered and buses walked, read completion
3302 : * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3303 : * it is possible to hotplug a device with MPS of 256B.
3304 : */
3305 0 : static void quirk_intel_mc_errata(struct pci_dev *dev)
3306 : {
3307 : int err;
3308 : u16 rcc;
3309 :
3310 0 : if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3311 : pcie_bus_config == PCIE_BUS_DEFAULT)
3312 0 : return;
3313 :
3314 : /*
3315 : * Intel erratum specifies bits to change but does not say what
3316 : * they are. Keeping them magical until such time as the registers
3317 : * and values can be explained.
3318 : */
3319 0 : err = pci_read_config_word(dev, 0x48, &rcc);
3320 0 : if (err) {
3321 0 : pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3322 0 : return;
3323 : }
3324 :
3325 0 : if (!(rcc & (1 << 10)))
3326 : return;
3327 :
3328 0 : rcc &= ~(1 << 10);
3329 :
3330 0 : err = pci_write_config_word(dev, 0x48, rcc);
3331 0 : if (err) {
3332 0 : pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3333 0 : return;
3334 : }
3335 :
3336 0 : pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3337 : }
3338 : /* Intel 5000 series memory controllers and ports 2-7 */
3339 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3340 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3341 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3342 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3343 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3344 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3345 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3346 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3347 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3348 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3349 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3350 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3351 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3352 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3353 : /* Intel 5100 series memory controllers and ports 2-7 */
3354 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3355 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3356 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3357 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3358 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3359 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3360 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3361 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3362 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3363 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3364 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3365 :
3366 : /*
3367 : * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3368 : * To work around this, query the size it should be configured to by the
3369 : * device and modify the resource end to correspond to this new size.
3370 : */
3371 0 : static void quirk_intel_ntb(struct pci_dev *dev)
3372 : {
3373 : int rc;
3374 : u8 val;
3375 :
3376 0 : rc = pci_read_config_byte(dev, 0x00D0, &val);
3377 0 : if (rc)
3378 0 : return;
3379 :
3380 0 : dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3381 :
3382 0 : rc = pci_read_config_byte(dev, 0x00D1, &val);
3383 0 : if (rc)
3384 : return;
3385 :
3386 0 : dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3387 : }
3388 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3389 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3390 :
3391 : /*
3392 : * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3393 : * though no one is handling them (e.g., if the i915 driver is never
3394 : * loaded). Additionally the interrupt destination is not set up properly
3395 : * and the interrupt ends up -somewhere-.
3396 : *
3397 : * These spurious interrupts are "sticky" and the kernel disables the
3398 : * (shared) interrupt line after 100,000+ generated interrupts.
3399 : *
3400 : * Fix it by disabling the still enabled interrupts. This resolves crashes
3401 : * often seen on monitor unplug.
3402 : */
3403 : #define I915_DEIER_REG 0x4400c
3404 0 : static void disable_igfx_irq(struct pci_dev *dev)
3405 : {
3406 0 : void __iomem *regs = pci_iomap(dev, 0, 0);
3407 0 : if (regs == NULL) {
3408 0 : pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3409 0 : return;
3410 : }
3411 :
3412 : /* Check if any interrupt line is still enabled */
3413 0 : if (readl(regs + I915_DEIER_REG) != 0) {
3414 0 : pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3415 :
3416 0 : writel(0, regs + I915_DEIER_REG);
3417 : }
3418 :
3419 0 : pci_iounmap(dev, regs);
3420 : }
3421 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3422 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3423 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3424 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3425 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3426 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3427 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3428 :
3429 : /*
3430 : * PCI devices which are on Intel chips can skip the 10ms delay
3431 : * before entering D3 mode.
3432 : */
3433 0 : static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3434 : {
3435 0 : dev->d3hot_delay = 0;
3436 0 : }
3437 : /* C600 Series devices do not need 10ms d3hot_delay */
3438 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3439 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3440 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3441 : /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3442 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3443 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3444 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3445 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3446 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3447 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3448 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3449 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3450 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3451 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3452 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3453 : /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3454 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3455 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3456 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3457 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3458 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3459 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3460 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3461 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3462 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3463 :
3464 : /*
3465 : * Some devices may pass our check in pci_intx_mask_supported() if
3466 : * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3467 : * support this feature.
3468 : */
3469 0 : static void quirk_broken_intx_masking(struct pci_dev *dev)
3470 : {
3471 0 : dev->broken_intx_masking = 1;
3472 0 : }
3473 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3474 : quirk_broken_intx_masking);
3475 : DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3476 : quirk_broken_intx_masking);
3477 : DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3478 : quirk_broken_intx_masking);
3479 :
3480 : /*
3481 : * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3482 : * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3483 : *
3484 : * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3485 : */
3486 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3487 : quirk_broken_intx_masking);
3488 :
3489 : /*
3490 : * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3491 : * DisINTx can be set but the interrupt status bit is non-functional.
3492 : */
3493 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3494 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3495 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3496 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3497 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3498 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3499 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3500 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3501 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3502 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3503 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3504 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3505 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3506 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3507 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3508 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3509 :
3510 : static u16 mellanox_broken_intx_devs[] = {
3511 : PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3512 : PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3513 : PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3514 : PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3515 : PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3516 : PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3517 : PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3518 : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3519 : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3520 : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3521 : PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3522 : PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3523 : PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3524 : PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3525 : };
3526 :
3527 : #define CONNECTX_4_CURR_MAX_MINOR 99
3528 : #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3529 :
3530 : /*
3531 : * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3532 : * If so, don't mark it as broken.
3533 : * FW minor > 99 means older FW version format and no INTx masking support.
3534 : * FW minor < 14 means new FW version format and no INTx masking support.
3535 : */
3536 0 : static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3537 : {
3538 : __be32 __iomem *fw_ver;
3539 : u16 fw_major;
3540 : u16 fw_minor;
3541 : u16 fw_subminor;
3542 : u32 fw_maj_min;
3543 : u32 fw_sub_min;
3544 : int i;
3545 :
3546 0 : for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3547 0 : if (pdev->device == mellanox_broken_intx_devs[i]) {
3548 0 : pdev->broken_intx_masking = 1;
3549 0 : return;
3550 : }
3551 : }
3552 :
3553 : /*
3554 : * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3555 : * support so shouldn't be checked further
3556 : */
3557 0 : if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3558 : return;
3559 :
3560 0 : if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3561 : pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3562 : return;
3563 :
3564 : /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3565 0 : if (pci_enable_device_mem(pdev)) {
3566 0 : pci_warn(pdev, "Can't enable device memory\n");
3567 0 : return;
3568 : }
3569 :
3570 0 : fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3571 0 : if (!fw_ver) {
3572 0 : pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3573 0 : goto out;
3574 : }
3575 :
3576 : /* Reading from resource space should be 32b aligned */
3577 0 : fw_maj_min = ioread32be(fw_ver);
3578 0 : fw_sub_min = ioread32be(fw_ver + 1);
3579 0 : fw_major = fw_maj_min & 0xffff;
3580 0 : fw_minor = fw_maj_min >> 16;
3581 0 : fw_subminor = fw_sub_min & 0xffff;
3582 0 : if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3583 : fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3584 0 : pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3585 : fw_major, fw_minor, fw_subminor, pdev->device ==
3586 : PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3587 0 : pdev->broken_intx_masking = 1;
3588 : }
3589 :
3590 0 : iounmap(fw_ver);
3591 :
3592 : out:
3593 0 : pci_disable_device(pdev);
3594 : }
3595 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3596 : mellanox_check_broken_intx_masking);
3597 :
3598 0 : static void quirk_no_bus_reset(struct pci_dev *dev)
3599 : {
3600 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3601 0 : }
3602 :
3603 : /*
3604 : * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3605 : * prevented for those affected devices.
3606 : */
3607 0 : static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3608 : {
3609 0 : if ((dev->device & 0xffc0) == 0x2340)
3610 : quirk_no_bus_reset(dev);
3611 0 : }
3612 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3613 : quirk_nvidia_no_bus_reset);
3614 :
3615 : /*
3616 : * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3617 : * The device will throw a Link Down error on AER-capable systems and
3618 : * regardless of AER, config space of the device is never accessible again
3619 : * and typically causes the system to hang or reset when access is attempted.
3620 : * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3621 : */
3622 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3623 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3624 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3625 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3626 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3627 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3628 :
3629 : /*
3630 : * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3631 : * reset when used with certain child devices. After the reset, config
3632 : * accesses to the child may fail.
3633 : */
3634 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3635 :
3636 : /*
3637 : * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3638 : * automatically disables LTSSM when Secondary Bus Reset is received and
3639 : * the device stops working. Prevent bus reset for these devices. With
3640 : * this change, the device can be assigned to VMs with VFIO, but it will
3641 : * leak state between VMs. Reference
3642 : * https://e2e.ti.com/support/processors/f/791/t/954382
3643 : */
3644 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3645 :
3646 0 : static void quirk_no_pm_reset(struct pci_dev *dev)
3647 : {
3648 : /*
3649 : * We can't do a bus reset on root bus devices, but an ineffective
3650 : * PM reset may be better than nothing.
3651 : */
3652 0 : if (!pci_is_root_bus(dev->bus))
3653 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3654 0 : }
3655 :
3656 : /*
3657 : * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3658 : * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3659 : * to have no effect on the device: it retains the framebuffer contents and
3660 : * monitor sync. Advertising this support makes other layers, like VFIO,
3661 : * assume pci_reset_function() is viable for this device. Mark it as
3662 : * unavailable to skip it when testing reset methods.
3663 : */
3664 : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3665 : PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3666 :
3667 : /*
3668 : * Thunderbolt controllers with broken MSI hotplug signaling:
3669 : * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3670 : * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3671 : */
3672 0 : static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3673 : {
3674 0 : if (pdev->is_hotplug_bridge &&
3675 0 : (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3676 0 : pdev->revision <= 1))
3677 0 : pdev->no_msi = 1;
3678 0 : }
3679 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3680 : quirk_thunderbolt_hotplug_msi);
3681 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3682 : quirk_thunderbolt_hotplug_msi);
3683 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3684 : quirk_thunderbolt_hotplug_msi);
3685 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3686 : quirk_thunderbolt_hotplug_msi);
3687 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3688 : quirk_thunderbolt_hotplug_msi);
3689 :
3690 : #ifdef CONFIG_ACPI
3691 : /*
3692 : * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3693 : *
3694 : * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3695 : * shutdown before suspend. Otherwise the native host interface (NHI) will not
3696 : * be present after resume if a device was plugged in before suspend.
3697 : *
3698 : * The Thunderbolt controller consists of a PCIe switch with downstream
3699 : * bridges leading to the NHI and to the tunnel PCI bridges.
3700 : *
3701 : * This quirk cuts power to the whole chip. Therefore we have to apply it
3702 : * during suspend_noirq of the upstream bridge.
3703 : *
3704 : * Power is automagically restored before resume. No action is needed.
3705 : */
3706 : static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3707 : {
3708 : acpi_handle bridge, SXIO, SXFP, SXLV;
3709 :
3710 : if (!x86_apple_machine)
3711 : return;
3712 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3713 : return;
3714 :
3715 : /*
3716 : * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3717 : * We don't know how to turn it back on again, but firmware does,
3718 : * so we can only use SXIO/SXFP/SXLF if we're suspending via
3719 : * firmware.
3720 : */
3721 : if (!pm_suspend_via_firmware())
3722 : return;
3723 :
3724 : bridge = ACPI_HANDLE(&dev->dev);
3725 : if (!bridge)
3726 : return;
3727 :
3728 : /*
3729 : * SXIO and SXLV are present only on machines requiring this quirk.
3730 : * Thunderbolt bridges in external devices might have the same
3731 : * device ID as those on the host, but they will not have the
3732 : * associated ACPI methods. This implicitly checks that we are at
3733 : * the right bridge.
3734 : */
3735 : if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3736 : || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3737 : || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3738 : return;
3739 : pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3740 :
3741 : /* magic sequence */
3742 : acpi_execute_simple_method(SXIO, NULL, 1);
3743 : acpi_execute_simple_method(SXFP, NULL, 0);
3744 : msleep(300);
3745 : acpi_execute_simple_method(SXLV, NULL, 0);
3746 : acpi_execute_simple_method(SXIO, NULL, 0);
3747 : acpi_execute_simple_method(SXLV, NULL, 0);
3748 : }
3749 : DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3750 : PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3751 : quirk_apple_poweroff_thunderbolt);
3752 : #endif
3753 :
3754 : /*
3755 : * Following are device-specific reset methods which can be used to
3756 : * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3757 : * not available.
3758 : */
3759 0 : static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe)
3760 : {
3761 : /*
3762 : * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3763 : *
3764 : * The 82599 supports FLR on VFs, but FLR support is reported only
3765 : * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3766 : * Thus we must call pcie_flr() directly without first checking if it is
3767 : * supported.
3768 : */
3769 0 : if (!probe)
3770 0 : pcie_flr(dev);
3771 0 : return 0;
3772 : }
3773 :
3774 : #define SOUTH_CHICKEN2 0xc2004
3775 : #define PCH_PP_STATUS 0xc7200
3776 : #define PCH_PP_CONTROL 0xc7204
3777 : #define MSG_CTL 0x45010
3778 : #define NSDE_PWR_STATE 0xd0100
3779 : #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3780 :
3781 0 : static int reset_ivb_igd(struct pci_dev *dev, bool probe)
3782 : {
3783 : void __iomem *mmio_base;
3784 : unsigned long timeout;
3785 : u32 val;
3786 :
3787 0 : if (probe)
3788 : return 0;
3789 :
3790 0 : mmio_base = pci_iomap(dev, 0, 0);
3791 0 : if (!mmio_base)
3792 : return -ENOMEM;
3793 :
3794 0 : iowrite32(0x00000002, mmio_base + MSG_CTL);
3795 :
3796 : /*
3797 : * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3798 : * driver loaded sets the right bits. However, this's a reset and
3799 : * the bits have been set by i915 previously, so we clobber
3800 : * SOUTH_CHICKEN2 register directly here.
3801 : */
3802 0 : iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3803 :
3804 0 : val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3805 0 : iowrite32(val, mmio_base + PCH_PP_CONTROL);
3806 :
3807 0 : timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3808 : do {
3809 0 : val = ioread32(mmio_base + PCH_PP_STATUS);
3810 0 : if ((val & 0xb0000000) == 0)
3811 : goto reset_complete;
3812 0 : msleep(10);
3813 0 : } while (time_before(jiffies, timeout));
3814 0 : pci_warn(dev, "timeout during reset\n");
3815 :
3816 : reset_complete:
3817 0 : iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3818 :
3819 0 : pci_iounmap(dev, mmio_base);
3820 0 : return 0;
3821 : }
3822 :
3823 : /* Device-specific reset method for Chelsio T4-based adapters */
3824 0 : static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)
3825 : {
3826 : u16 old_command;
3827 : u16 msix_flags;
3828 :
3829 : /*
3830 : * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3831 : * that we have no device-specific reset method.
3832 : */
3833 0 : if ((dev->device & 0xf000) != 0x4000)
3834 : return -ENOTTY;
3835 :
3836 : /*
3837 : * If this is the "probe" phase, return 0 indicating that we can
3838 : * reset this device.
3839 : */
3840 0 : if (probe)
3841 : return 0;
3842 :
3843 : /*
3844 : * T4 can wedge if there are DMAs in flight within the chip and Bus
3845 : * Master has been disabled. We need to have it on till the Function
3846 : * Level Reset completes. (BUS_MASTER is disabled in
3847 : * pci_reset_function()).
3848 : */
3849 0 : pci_read_config_word(dev, PCI_COMMAND, &old_command);
3850 0 : pci_write_config_word(dev, PCI_COMMAND,
3851 : old_command | PCI_COMMAND_MASTER);
3852 :
3853 : /*
3854 : * Perform the actual device function reset, saving and restoring
3855 : * configuration information around the reset.
3856 : */
3857 0 : pci_save_state(dev);
3858 :
3859 : /*
3860 : * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3861 : * are disabled when an MSI-X interrupt message needs to be delivered.
3862 : * So we briefly re-enable MSI-X interrupts for the duration of the
3863 : * FLR. The pci_restore_state() below will restore the original
3864 : * MSI-X state.
3865 : */
3866 0 : pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3867 0 : if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3868 0 : pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3869 : msix_flags |
3870 : PCI_MSIX_FLAGS_ENABLE |
3871 : PCI_MSIX_FLAGS_MASKALL);
3872 :
3873 0 : pcie_flr(dev);
3874 :
3875 : /*
3876 : * Restore the configuration information (BAR values, etc.) including
3877 : * the original PCI Configuration Space Command word, and return
3878 : * success.
3879 : */
3880 0 : pci_restore_state(dev);
3881 0 : pci_write_config_word(dev, PCI_COMMAND, old_command);
3882 0 : return 0;
3883 : }
3884 :
3885 : #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3886 : #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3887 : #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3888 :
3889 : /*
3890 : * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3891 : * FLR where config space reads from the device return -1. We seem to be
3892 : * able to avoid this condition if we disable the NVMe controller prior to
3893 : * FLR. This quirk is generic for any NVMe class device requiring similar
3894 : * assistance to quiesce the device prior to FLR.
3895 : *
3896 : * NVMe specification: https://nvmexpress.org/resources/specifications/
3897 : * Revision 1.0e:
3898 : * Chapter 2: Required and optional PCI config registers
3899 : * Chapter 3: NVMe control registers
3900 : * Chapter 7.3: Reset behavior
3901 : */
3902 0 : static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)
3903 : {
3904 : void __iomem *bar;
3905 : u16 cmd;
3906 : u32 cfg;
3907 :
3908 0 : if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3909 0 : pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0))
3910 : return -ENOTTY;
3911 :
3912 0 : if (probe)
3913 : return 0;
3914 :
3915 0 : bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3916 0 : if (!bar)
3917 : return -ENOTTY;
3918 :
3919 0 : pci_read_config_word(dev, PCI_COMMAND, &cmd);
3920 0 : pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3921 :
3922 0 : cfg = readl(bar + NVME_REG_CC);
3923 :
3924 : /* Disable controller if enabled */
3925 0 : if (cfg & NVME_CC_ENABLE) {
3926 0 : u32 cap = readl(bar + NVME_REG_CAP);
3927 : unsigned long timeout;
3928 :
3929 : /*
3930 : * Per nvme_disable_ctrl() skip shutdown notification as it
3931 : * could complete commands to the admin queue. We only intend
3932 : * to quiesce the device before reset.
3933 : */
3934 0 : cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3935 :
3936 0 : writel(cfg, bar + NVME_REG_CC);
3937 :
3938 : /*
3939 : * Some controllers require an additional delay here, see
3940 : * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3941 : * supported by this quirk.
3942 : */
3943 :
3944 : /* Cap register provides max timeout in 500ms increments */
3945 0 : timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3946 :
3947 : for (;;) {
3948 0 : u32 status = readl(bar + NVME_REG_CSTS);
3949 :
3950 : /* Ready status becomes zero on disable complete */
3951 0 : if (!(status & NVME_CSTS_RDY))
3952 : break;
3953 :
3954 0 : msleep(100);
3955 :
3956 0 : if (time_after(jiffies, timeout)) {
3957 0 : pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3958 0 : break;
3959 : }
3960 : }
3961 : }
3962 :
3963 0 : pci_iounmap(dev, bar);
3964 :
3965 0 : pcie_flr(dev);
3966 :
3967 0 : return 0;
3968 : }
3969 :
3970 : /*
3971 : * Intel DC P3700 NVMe controller will timeout waiting for ready status
3972 : * to change after NVMe enable if the driver starts interacting with the
3973 : * device too soon after FLR. A 250ms delay after FLR has heuristically
3974 : * proven to produce reliably working results for device assignment cases.
3975 : */
3976 0 : static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)
3977 : {
3978 0 : if (probe)
3979 0 : return pcie_reset_flr(dev, PCI_RESET_PROBE);
3980 :
3981 0 : pcie_reset_flr(dev, PCI_RESET_DO_RESET);
3982 :
3983 0 : msleep(250);
3984 :
3985 0 : return 0;
3986 : }
3987 :
3988 : #define PCI_DEVICE_ID_HINIC_VF 0x375E
3989 : #define HINIC_VF_FLR_TYPE 0x1000
3990 : #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
3991 : #define HINIC_VF_OP 0xE80
3992 : #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
3993 : #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
3994 :
3995 : /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3996 0 : static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)
3997 : {
3998 : unsigned long timeout;
3999 : void __iomem *bar;
4000 : u32 val;
4001 :
4002 0 : if (probe)
4003 : return 0;
4004 :
4005 0 : bar = pci_iomap(pdev, 0, 0);
4006 0 : if (!bar)
4007 : return -ENOTTY;
4008 :
4009 : /* Get and check firmware capabilities */
4010 0 : val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4011 0 : if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4012 0 : pci_iounmap(pdev, bar);
4013 0 : return -ENOTTY;
4014 : }
4015 :
4016 : /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
4017 0 : val = ioread32be(bar + HINIC_VF_OP);
4018 0 : val = val | HINIC_VF_FLR_PROC_BIT;
4019 0 : iowrite32be(val, bar + HINIC_VF_OP);
4020 :
4021 0 : pcie_flr(pdev);
4022 :
4023 : /*
4024 : * The device must recapture its Bus and Device Numbers after FLR
4025 : * in order generate Completions. Issue a config write to let the
4026 : * device capture this information.
4027 : */
4028 0 : pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
4029 :
4030 : /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
4031 0 : timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
4032 : do {
4033 0 : val = ioread32be(bar + HINIC_VF_OP);
4034 0 : if (!(val & HINIC_VF_FLR_PROC_BIT))
4035 : goto reset_complete;
4036 0 : msleep(20);
4037 0 : } while (time_before(jiffies, timeout));
4038 :
4039 0 : val = ioread32be(bar + HINIC_VF_OP);
4040 0 : if (!(val & HINIC_VF_FLR_PROC_BIT))
4041 : goto reset_complete;
4042 :
4043 0 : pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
4044 :
4045 : reset_complete:
4046 0 : pci_iounmap(pdev, bar);
4047 :
4048 0 : return 0;
4049 : }
4050 :
4051 : static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4052 : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4053 : reset_intel_82599_sfp_virtfn },
4054 : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4055 : reset_ivb_igd },
4056 : { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4057 : reset_ivb_igd },
4058 : { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4059 : { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4060 : { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4061 : { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4062 : reset_chelsio_generic_dev },
4063 : { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4064 : reset_hinic_vf_dev },
4065 : { 0 }
4066 : };
4067 :
4068 : /*
4069 : * These device-specific reset methods are here rather than in a driver
4070 : * because when a host assigns a device to a guest VM, the host may need
4071 : * to reset the device but probably doesn't have a driver for it.
4072 : */
4073 0 : int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
4074 : {
4075 : const struct pci_dev_reset_methods *i;
4076 :
4077 0 : for (i = pci_dev_reset_methods; i->reset; i++) {
4078 0 : if ((i->vendor == dev->vendor ||
4079 0 : i->vendor == (u16)PCI_ANY_ID) &&
4080 0 : (i->device == dev->device ||
4081 : i->device == (u16)PCI_ANY_ID))
4082 0 : return i->reset(dev, probe);
4083 : }
4084 :
4085 : return -ENOTTY;
4086 : }
4087 :
4088 0 : static void quirk_dma_func0_alias(struct pci_dev *dev)
4089 : {
4090 0 : if (PCI_FUNC(dev->devfn) != 0)
4091 0 : pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4092 0 : }
4093 :
4094 : /*
4095 : * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4096 : *
4097 : * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4098 : */
4099 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4100 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4101 :
4102 0 : static void quirk_dma_func1_alias(struct pci_dev *dev)
4103 : {
4104 0 : if (PCI_FUNC(dev->devfn) != 1)
4105 0 : pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4106 0 : }
4107 :
4108 : /*
4109 : * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4110 : * SKUs function 1 is present and is a legacy IDE controller, in other
4111 : * SKUs this function is not present, making this a ghost requester.
4112 : * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4113 : */
4114 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4115 : quirk_dma_func1_alias);
4116 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4117 : quirk_dma_func1_alias);
4118 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4119 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4120 : quirk_dma_func1_alias);
4121 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4122 : quirk_dma_func1_alias);
4123 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4124 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4125 : quirk_dma_func1_alias);
4126 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4127 : quirk_dma_func1_alias);
4128 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4129 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4130 : quirk_dma_func1_alias);
4131 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4132 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4133 : quirk_dma_func1_alias);
4134 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4135 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4136 : quirk_dma_func1_alias);
4137 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4138 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4139 : quirk_dma_func1_alias);
4140 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4141 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4142 : quirk_dma_func1_alias);
4143 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4144 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4145 : quirk_dma_func1_alias);
4146 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4147 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4148 : quirk_dma_func1_alias);
4149 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4150 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4151 : quirk_dma_func1_alias);
4152 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4153 : quirk_dma_func1_alias);
4154 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4155 : quirk_dma_func1_alias);
4156 : /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4157 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4158 : PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4159 : quirk_dma_func1_alias);
4160 : /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4161 : DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4162 : 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4163 : quirk_dma_func1_alias);
4164 :
4165 : /*
4166 : * Some devices DMA with the wrong devfn, not just the wrong function.
4167 : * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4168 : * the alias is "fixed" and independent of the device devfn.
4169 : *
4170 : * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4171 : * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4172 : * single device on the secondary bus. In reality, the single exposed
4173 : * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4174 : * that provides a bridge to the internal bus of the I/O processor. The
4175 : * controller supports private devices, which can be hidden from PCI config
4176 : * space. In the case of the Adaptec 3405, a private device at 01.0
4177 : * appears to be the DMA engine, which therefore needs to become a DMA
4178 : * alias for the device.
4179 : */
4180 : static const struct pci_device_id fixed_dma_alias_tbl[] = {
4181 : { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4182 : PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4183 : .driver_data = PCI_DEVFN(1, 0) },
4184 : { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4185 : PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4186 : .driver_data = PCI_DEVFN(1, 0) },
4187 : { 0 }
4188 : };
4189 :
4190 0 : static void quirk_fixed_dma_alias(struct pci_dev *dev)
4191 : {
4192 : const struct pci_device_id *id;
4193 :
4194 0 : id = pci_match_id(fixed_dma_alias_tbl, dev);
4195 0 : if (id)
4196 0 : pci_add_dma_alias(dev, id->driver_data, 1);
4197 0 : }
4198 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4199 :
4200 : /*
4201 : * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4202 : * using the wrong DMA alias for the device. Some of these devices can be
4203 : * used as either forward or reverse bridges, so we need to test whether the
4204 : * device is operating in the correct mode. We could probably apply this
4205 : * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4206 : * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4207 : * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4208 : */
4209 0 : static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4210 : {
4211 0 : if (!pci_is_root_bus(pdev->bus) &&
4212 0 : pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4213 0 : !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4214 0 : pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4215 0 : pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4216 0 : }
4217 : /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4218 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4219 : quirk_use_pcie_bridge_dma_alias);
4220 : /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4221 : DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4222 : /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4223 : DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4224 : /* ITE 8893 has the same problem as the 8892 */
4225 : DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4226 : /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4227 : DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4228 :
4229 : /*
4230 : * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4231 : * be added as aliases to the DMA device in order to allow buffer access
4232 : * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4233 : * programmed in the EEPROM.
4234 : */
4235 0 : static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4236 : {
4237 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4238 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4239 0 : pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4240 0 : }
4241 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4242 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4243 :
4244 : /*
4245 : * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4246 : * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4247 : *
4248 : * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4249 : * when IOMMU is enabled. These aliases allow computational unit access to
4250 : * host memory. These aliases mark the whole VCA device as one IOMMU
4251 : * group.
4252 : *
4253 : * All possible slot numbers (0x20) are used, since we are unable to tell
4254 : * what slot is used on other side. This quirk is intended for both host
4255 : * and computational unit sides. The VCA devices have up to five functions
4256 : * (four for DMA channels and one additional).
4257 : */
4258 0 : static void quirk_pex_vca_alias(struct pci_dev *pdev)
4259 : {
4260 0 : const unsigned int num_pci_slots = 0x20;
4261 : unsigned int slot;
4262 :
4263 0 : for (slot = 0; slot < num_pci_slots; slot++)
4264 0 : pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4265 0 : }
4266 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4267 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4268 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4269 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4270 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4271 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4272 :
4273 : /*
4274 : * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4275 : * associated not at the root bus, but at a bridge below. This quirk avoids
4276 : * generating invalid DMA aliases.
4277 : */
4278 0 : static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4279 : {
4280 0 : pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4281 0 : }
4282 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4283 : quirk_bridge_cavm_thrx2_pcie_root);
4284 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4285 : quirk_bridge_cavm_thrx2_pcie_root);
4286 :
4287 : /*
4288 : * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4289 : * class code. Fix it.
4290 : */
4291 0 : static void quirk_tw686x_class(struct pci_dev *pdev)
4292 : {
4293 0 : u32 class = pdev->class;
4294 :
4295 : /* Use "Multimedia controller" class */
4296 0 : pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4297 0 : pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4298 : class, pdev->class);
4299 0 : }
4300 : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4301 : quirk_tw686x_class);
4302 : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4303 : quirk_tw686x_class);
4304 : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4305 : quirk_tw686x_class);
4306 : DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4307 : quirk_tw686x_class);
4308 :
4309 : /*
4310 : * Some devices have problems with Transaction Layer Packets with the Relaxed
4311 : * Ordering Attribute set. Such devices should mark themselves and other
4312 : * device drivers should check before sending TLPs with RO set.
4313 : */
4314 0 : static void quirk_relaxedordering_disable(struct pci_dev *dev)
4315 : {
4316 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4317 0 : pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4318 0 : }
4319 :
4320 : /*
4321 : * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4322 : * Complex have a Flow Control Credit issue which can cause performance
4323 : * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4324 : */
4325 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4326 : quirk_relaxedordering_disable);
4327 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4328 : quirk_relaxedordering_disable);
4329 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4330 : quirk_relaxedordering_disable);
4331 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4332 : quirk_relaxedordering_disable);
4333 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4334 : quirk_relaxedordering_disable);
4335 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4336 : quirk_relaxedordering_disable);
4337 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4338 : quirk_relaxedordering_disable);
4339 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4340 : quirk_relaxedordering_disable);
4341 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4342 : quirk_relaxedordering_disable);
4343 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4344 : quirk_relaxedordering_disable);
4345 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4346 : quirk_relaxedordering_disable);
4347 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4348 : quirk_relaxedordering_disable);
4349 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4350 : quirk_relaxedordering_disable);
4351 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4352 : quirk_relaxedordering_disable);
4353 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4354 : quirk_relaxedordering_disable);
4355 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4356 : quirk_relaxedordering_disable);
4357 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4358 : quirk_relaxedordering_disable);
4359 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4360 : quirk_relaxedordering_disable);
4361 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4362 : quirk_relaxedordering_disable);
4363 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4364 : quirk_relaxedordering_disable);
4365 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4366 : quirk_relaxedordering_disable);
4367 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4368 : quirk_relaxedordering_disable);
4369 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4370 : quirk_relaxedordering_disable);
4371 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4372 : quirk_relaxedordering_disable);
4373 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4374 : quirk_relaxedordering_disable);
4375 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4376 : quirk_relaxedordering_disable);
4377 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4378 : quirk_relaxedordering_disable);
4379 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4380 : quirk_relaxedordering_disable);
4381 :
4382 : /*
4383 : * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4384 : * where Upstream Transaction Layer Packets with the Relaxed Ordering
4385 : * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4386 : * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4387 : * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4388 : * November 10, 2010). As a result, on this platform we can't use Relaxed
4389 : * Ordering for Upstream TLPs.
4390 : */
4391 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4392 : quirk_relaxedordering_disable);
4393 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4394 : quirk_relaxedordering_disable);
4395 : DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4396 : quirk_relaxedordering_disable);
4397 :
4398 : /*
4399 : * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4400 : * values for the Attribute as were supplied in the header of the
4401 : * corresponding Request, except as explicitly allowed when IDO is used."
4402 : *
4403 : * If a non-compliant device generates a completion with a different
4404 : * attribute than the request, the receiver may accept it (which itself
4405 : * seems non-compliant based on sec 2.3.2), or it may handle it as a
4406 : * Malformed TLP or an Unexpected Completion, which will probably lead to a
4407 : * device access timeout.
4408 : *
4409 : * If the non-compliant device generates completions with zero attributes
4410 : * (instead of copying the attributes from the request), we can work around
4411 : * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4412 : * upstream devices so they always generate requests with zero attributes.
4413 : *
4414 : * This affects other devices under the same Root Port, but since these
4415 : * attributes are performance hints, there should be no functional problem.
4416 : *
4417 : * Note that Configuration Space accesses are never supposed to have TLP
4418 : * Attributes, so we're safe waiting till after any Configuration Space
4419 : * accesses to do the Root Port fixup.
4420 : */
4421 0 : static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4422 : {
4423 0 : struct pci_dev *root_port = pcie_find_root_port(pdev);
4424 :
4425 0 : if (!root_port) {
4426 0 : pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4427 0 : return;
4428 : }
4429 :
4430 0 : pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4431 : dev_name(&pdev->dev));
4432 0 : pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4433 : PCI_EXP_DEVCTL_RELAX_EN |
4434 : PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4435 : }
4436 :
4437 : /*
4438 : * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4439 : * Completion it generates.
4440 : */
4441 0 : static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4442 : {
4443 : /*
4444 : * This mask/compare operation selects for Physical Function 4 on a
4445 : * T5. We only need to fix up the Root Port once for any of the
4446 : * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4447 : * 0x54xx so we use that one.
4448 : */
4449 0 : if ((pdev->device & 0xff00) == 0x5400)
4450 0 : quirk_disable_root_port_attributes(pdev);
4451 0 : }
4452 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4453 : quirk_chelsio_T5_disable_root_port_attributes);
4454 :
4455 : /*
4456 : * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4457 : * by a device
4458 : * @acs_ctrl_req: Bitmask of desired ACS controls
4459 : * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4460 : * the hardware design
4461 : *
4462 : * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4463 : * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4464 : * caller desires. Return 0 otherwise.
4465 : */
4466 : static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4467 : {
4468 0 : if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4469 : return 1;
4470 : return 0;
4471 : }
4472 :
4473 : /*
4474 : * AMD has indicated that the devices below do not support peer-to-peer
4475 : * in any system where they are found in the southbridge with an AMD
4476 : * IOMMU in the system. Multifunction devices that do not support
4477 : * peer-to-peer between functions can claim to support a subset of ACS.
4478 : * Such devices effectively enable request redirect (RR) and completion
4479 : * redirect (CR) since all transactions are redirected to the upstream
4480 : * root complex.
4481 : *
4482 : * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4483 : * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4484 : * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4485 : *
4486 : * 1002:4385 SBx00 SMBus Controller
4487 : * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4488 : * 1002:4383 SBx00 Azalia (Intel HDA)
4489 : * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4490 : * 1002:4384 SBx00 PCI to PCI Bridge
4491 : * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4492 : *
4493 : * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4494 : *
4495 : * 1022:780f [AMD] FCH PCI Bridge
4496 : * 1022:7809 [AMD] FCH USB OHCI Controller
4497 : */
4498 0 : static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4499 : {
4500 : #ifdef CONFIG_ACPI
4501 : struct acpi_table_header *header = NULL;
4502 : acpi_status status;
4503 :
4504 : /* Targeting multifunction devices on the SB (appears on root bus) */
4505 : if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4506 : return -ENODEV;
4507 :
4508 : /* The IVRS table describes the AMD IOMMU */
4509 : status = acpi_get_table("IVRS", 0, &header);
4510 : if (ACPI_FAILURE(status))
4511 : return -ENODEV;
4512 :
4513 : acpi_put_table(header);
4514 :
4515 : /* Filter out flags not applicable to multifunction */
4516 : acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4517 :
4518 : return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4519 : #else
4520 0 : return -ENODEV;
4521 : #endif
4522 : }
4523 :
4524 : static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4525 : {
4526 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4527 : return false;
4528 :
4529 0 : switch (dev->device) {
4530 : /*
4531 : * Effectively selects all downstream ports for whole ThunderX1
4532 : * (which represents 8 SoCs).
4533 : */
4534 : case 0xa000 ... 0xa7ff: /* ThunderX1 */
4535 : case 0xaf84: /* ThunderX2 */
4536 : case 0xb884: /* ThunderX3 */
4537 : return true;
4538 : default:
4539 : return false;
4540 : }
4541 : }
4542 :
4543 0 : static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4544 : {
4545 0 : if (!pci_quirk_cavium_acs_match(dev))
4546 : return -ENOTTY;
4547 :
4548 : /*
4549 : * Cavium Root Ports don't advertise an ACS capability. However,
4550 : * the RTL internally implements similar protection as if ACS had
4551 : * Source Validation, Request Redirection, Completion Redirection,
4552 : * and Upstream Forwarding features enabled. Assert that the
4553 : * hardware implements and enables equivalent ACS functionality for
4554 : * these flags.
4555 : */
4556 : return pci_acs_ctrl_enabled(acs_flags,
4557 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4558 : }
4559 :
4560 0 : static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4561 : {
4562 : /*
4563 : * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4564 : * transactions with others, allowing masking out these bits as if they
4565 : * were unimplemented in the ACS capability.
4566 : */
4567 0 : return pci_acs_ctrl_enabled(acs_flags,
4568 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4569 : }
4570 :
4571 : /*
4572 : * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4573 : * But the implementation could block peer-to-peer transactions between them
4574 : * and provide ACS-like functionality.
4575 : */
4576 0 : static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4577 : {
4578 0 : if (!pci_is_pcie(dev) ||
4579 0 : ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4580 0 : (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4581 : return -ENOTTY;
4582 :
4583 0 : switch (dev->device) {
4584 : case 0x0710 ... 0x071e:
4585 : case 0x0721:
4586 : case 0x0723 ... 0x0732:
4587 : return pci_acs_ctrl_enabled(acs_flags,
4588 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4589 : }
4590 :
4591 : return false;
4592 : }
4593 :
4594 : /*
4595 : * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4596 : * transactions and validate bus numbers in requests, but do not provide an
4597 : * actual PCIe ACS capability. This is the list of device IDs known to fall
4598 : * into that category as provided by Intel in Red Hat bugzilla 1037684.
4599 : */
4600 : static const u16 pci_quirk_intel_pch_acs_ids[] = {
4601 : /* Ibexpeak PCH */
4602 : 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4603 : 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4604 : /* Cougarpoint PCH */
4605 : 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4606 : 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4607 : /* Pantherpoint PCH */
4608 : 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4609 : 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4610 : /* Lynxpoint-H PCH */
4611 : 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4612 : 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4613 : /* Lynxpoint-LP PCH */
4614 : 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4615 : 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4616 : /* Wildcat PCH */
4617 : 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4618 : 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4619 : /* Patsburg (X79) PCH */
4620 : 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4621 : /* Wellsburg (X99) PCH */
4622 : 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4623 : 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4624 : /* Lynx Point (9 series) PCH */
4625 : 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4626 : };
4627 :
4628 : static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4629 : {
4630 : int i;
4631 :
4632 : /* Filter out a few obvious non-matches first */
4633 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4634 : return false;
4635 :
4636 0 : for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4637 0 : if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4638 : return true;
4639 :
4640 : return false;
4641 : }
4642 :
4643 0 : static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4644 : {
4645 0 : if (!pci_quirk_intel_pch_acs_match(dev))
4646 : return -ENOTTY;
4647 :
4648 0 : if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4649 : return pci_acs_ctrl_enabled(acs_flags,
4650 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4651 :
4652 : return pci_acs_ctrl_enabled(acs_flags, 0);
4653 : }
4654 :
4655 : /*
4656 : * These QCOM Root Ports do provide ACS-like features to disable peer
4657 : * transactions and validate bus numbers in requests, but do not provide an
4658 : * actual PCIe ACS capability. Hardware supports source validation but it
4659 : * will report the issue as Completer Abort instead of ACS Violation.
4660 : * Hardware doesn't support peer-to-peer and each Root Port is a Root
4661 : * Complex with unique segment numbers. It is not possible for one Root
4662 : * Port to pass traffic to another Root Port. All PCIe transactions are
4663 : * terminated inside the Root Port.
4664 : */
4665 0 : static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4666 : {
4667 0 : return pci_acs_ctrl_enabled(acs_flags,
4668 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4669 : }
4670 :
4671 : /*
4672 : * Each of these NXP Root Ports is in a Root Complex with a unique segment
4673 : * number and does provide isolation features to disable peer transactions
4674 : * and validate bus numbers in requests, but does not provide an ACS
4675 : * capability.
4676 : */
4677 0 : static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4678 : {
4679 0 : return pci_acs_ctrl_enabled(acs_flags,
4680 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4681 : }
4682 :
4683 0 : static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4684 : {
4685 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4686 : return -ENOTTY;
4687 :
4688 : /*
4689 : * Amazon's Annapurna Labs root ports don't include an ACS capability,
4690 : * but do include ACS-like functionality. The hardware doesn't support
4691 : * peer-to-peer transactions via the root port and each has a unique
4692 : * segment number.
4693 : *
4694 : * Additionally, the root ports cannot send traffic to each other.
4695 : */
4696 0 : acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4697 :
4698 0 : return acs_flags ? 0 : 1;
4699 : }
4700 :
4701 : /*
4702 : * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4703 : * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4704 : * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4705 : * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4706 : * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4707 : * control register is at offset 8 instead of 6 and we should probably use
4708 : * dword accesses to them. This applies to the following PCI Device IDs, as
4709 : * found in volume 1 of the datasheet[2]:
4710 : *
4711 : * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4712 : * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4713 : *
4714 : * N.B. This doesn't fix what lspci shows.
4715 : *
4716 : * The 100 series chipset specification update includes this as errata #23[3].
4717 : *
4718 : * The 200 series chipset (Union Point) has the same bug according to the
4719 : * specification update (Intel 200 Series Chipset Family Platform Controller
4720 : * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4721 : * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4722 : * chipset include:
4723 : *
4724 : * 0xa290-0xa29f PCI Express Root port #{0-16}
4725 : * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4726 : *
4727 : * Mobile chipsets are also affected, 7th & 8th Generation
4728 : * Specification update confirms ACS errata 22, status no fix: (7th Generation
4729 : * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4730 : * Processor Family I/O for U Quad Core Platforms Specification Update,
4731 : * August 2017, Revision 002, Document#: 334660-002)[6]
4732 : * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4733 : * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4734 : * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4735 : *
4736 : * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4737 : *
4738 : * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4739 : * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4740 : * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4741 : * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4742 : * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4743 : * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4744 : * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4745 : */
4746 0 : static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4747 : {
4748 0 : if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4749 : return false;
4750 :
4751 0 : switch (dev->device) {
4752 : case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4753 : case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4754 : case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4755 : return true;
4756 : }
4757 :
4758 0 : return false;
4759 : }
4760 :
4761 : #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4762 :
4763 0 : static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4764 : {
4765 : int pos;
4766 : u32 cap, ctrl;
4767 :
4768 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
4769 : return -ENOTTY;
4770 :
4771 0 : pos = dev->acs_cap;
4772 0 : if (!pos)
4773 : return -ENOTTY;
4774 :
4775 : /* see pci_acs_flags_enabled() */
4776 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4777 0 : acs_flags &= (cap | PCI_ACS_EC);
4778 :
4779 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4780 :
4781 0 : return pci_acs_ctrl_enabled(acs_flags, ctrl);
4782 : }
4783 :
4784 0 : static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4785 : {
4786 : /*
4787 : * SV, TB, and UF are not relevant to multifunction endpoints.
4788 : *
4789 : * Multifunction devices are only required to implement RR, CR, and DT
4790 : * in their ACS capability if they support peer-to-peer transactions.
4791 : * Devices matching this quirk have been verified by the vendor to not
4792 : * perform peer-to-peer with other functions, allowing us to mask out
4793 : * these bits as if they were unimplemented in the ACS capability.
4794 : */
4795 0 : return pci_acs_ctrl_enabled(acs_flags,
4796 : PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4797 : PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4798 : }
4799 :
4800 0 : static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4801 : {
4802 : /*
4803 : * Intel RCiEP's are required to allow p2p only on translated
4804 : * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4805 : * "Root-Complex Peer to Peer Considerations".
4806 : */
4807 0 : if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4808 : return -ENOTTY;
4809 :
4810 : return pci_acs_ctrl_enabled(acs_flags,
4811 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4812 : }
4813 :
4814 0 : static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4815 : {
4816 : /*
4817 : * iProc PAXB Root Ports don't advertise an ACS capability, but
4818 : * they do not allow peer-to-peer transactions between Root Ports.
4819 : * Allow each Root Port to be in a separate IOMMU group by masking
4820 : * SV/RR/CR/UF bits.
4821 : */
4822 0 : return pci_acs_ctrl_enabled(acs_flags,
4823 : PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4824 : }
4825 :
4826 : static const struct pci_dev_acs_enabled {
4827 : u16 vendor;
4828 : u16 device;
4829 : int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4830 : } pci_dev_acs_enabled[] = {
4831 : { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4832 : { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4833 : { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4834 : { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4835 : { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4836 : { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4837 : { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4838 : { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4839 : { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4840 : { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4841 : { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4842 : { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4843 : { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4844 : { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4845 : { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4846 : { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4847 : { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4848 : { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4849 : { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4850 : { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4851 : { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4852 : { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4853 : { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4854 : { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4855 : { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4856 : { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4857 : { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4858 : { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4859 : { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4860 : { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4861 : { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4862 : /* 82580 */
4863 : { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4864 : { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4865 : { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4866 : { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4867 : { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4868 : { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4869 : { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4870 : /* 82576 */
4871 : { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4872 : { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4873 : { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4874 : { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4875 : { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4876 : { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4877 : { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4878 : { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4879 : /* 82575 */
4880 : { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4881 : { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4882 : { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4883 : /* I350 */
4884 : { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4885 : { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4886 : { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4887 : { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4888 : /* 82571 (Quads omitted due to non-ACS switch) */
4889 : { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4890 : { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4891 : { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4892 : { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4893 : /* I219 */
4894 : { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4895 : { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4896 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4897 : /* QCOM QDF2xxx root ports */
4898 : { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4899 : { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4900 : /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4901 : { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4902 : /* Intel PCH root ports */
4903 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4904 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4905 : { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4906 : { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4907 : /* Cavium ThunderX */
4908 : { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4909 : /* Cavium multi-function devices */
4910 : { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4911 : { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4912 : { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4913 : /* APM X-Gene */
4914 : { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4915 : /* Ampere Computing */
4916 : { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4917 : { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4918 : { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4919 : { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4920 : { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4921 : { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4922 : { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4923 : { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4924 : /* Broadcom multi-function device */
4925 : { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4926 : { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4927 : /* Amazon Annapurna Labs */
4928 : { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4929 : /* Zhaoxin multi-function devices */
4930 : { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4931 : { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4932 : { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4933 : /* NXP root ports, xx=16, 12, or 08 cores */
4934 : /* LX2xx0A : without security features + CAN-FD */
4935 : { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
4936 : { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
4937 : { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
4938 : /* LX2xx0C : security features + CAN-FD */
4939 : { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
4940 : { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
4941 : { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
4942 : /* LX2xx0E : security features + CAN */
4943 : { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
4944 : { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
4945 : { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
4946 : /* LX2xx0N : without security features + CAN */
4947 : { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
4948 : { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
4949 : { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
4950 : /* LX2xx2A : without security features + CAN-FD */
4951 : { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
4952 : { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
4953 : { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
4954 : /* LX2xx2C : security features + CAN-FD */
4955 : { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
4956 : { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
4957 : { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
4958 : /* LX2xx2E : security features + CAN */
4959 : { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
4960 : { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
4961 : { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
4962 : /* LX2xx2N : without security features + CAN */
4963 : { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
4964 : { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
4965 : { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
4966 : /* Zhaoxin Root/Downstream Ports */
4967 : { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
4968 : { 0 }
4969 : };
4970 :
4971 : /*
4972 : * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4973 : * @dev: PCI device
4974 : * @acs_flags: Bitmask of desired ACS controls
4975 : *
4976 : * Returns:
4977 : * -ENOTTY: No quirk applies to this device; we can't tell whether the
4978 : * device provides the desired controls
4979 : * 0: Device does not provide all the desired controls
4980 : * >0: Device provides all the controls in @acs_flags
4981 : */
4982 0 : int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4983 : {
4984 : const struct pci_dev_acs_enabled *i;
4985 : int ret;
4986 :
4987 : /*
4988 : * Allow devices that do not expose standard PCIe ACS capabilities
4989 : * or control to indicate their support here. Multi-function express
4990 : * devices which do not allow internal peer-to-peer between functions,
4991 : * but do not implement PCIe ACS may wish to return true here.
4992 : */
4993 0 : for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4994 0 : if ((i->vendor == dev->vendor ||
4995 0 : i->vendor == (u16)PCI_ANY_ID) &&
4996 0 : (i->device == dev->device ||
4997 : i->device == (u16)PCI_ANY_ID)) {
4998 0 : ret = i->acs_enabled(dev, acs_flags);
4999 0 : if (ret >= 0)
5000 : return ret;
5001 : }
5002 : }
5003 :
5004 : return -ENOTTY;
5005 : }
5006 :
5007 : /* Config space offset of Root Complex Base Address register */
5008 : #define INTEL_LPC_RCBA_REG 0xf0
5009 : /* 31:14 RCBA address */
5010 : #define INTEL_LPC_RCBA_MASK 0xffffc000
5011 : /* RCBA Enable */
5012 : #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5013 :
5014 : /* Backbone Scratch Pad Register */
5015 : #define INTEL_BSPR_REG 0x1104
5016 : /* Backbone Peer Non-Posted Disable */
5017 : #define INTEL_BSPR_REG_BPNPD (1 << 8)
5018 : /* Backbone Peer Posted Disable */
5019 : #define INTEL_BSPR_REG_BPPD (1 << 9)
5020 :
5021 : /* Upstream Peer Decode Configuration Register */
5022 : #define INTEL_UPDCR_REG 0x1014
5023 : /* 5:0 Peer Decode Enable bits */
5024 : #define INTEL_UPDCR_REG_MASK 0x3f
5025 :
5026 0 : static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
5027 : {
5028 : u32 rcba, bspr, updcr;
5029 : void __iomem *rcba_mem;
5030 :
5031 : /*
5032 : * Read the RCBA register from the LPC (D31:F0). PCH root ports
5033 : * are D28:F* and therefore get probed before LPC, thus we can't
5034 : * use pci_get_slot()/pci_read_config_dword() here.
5035 : */
5036 0 : pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
5037 : INTEL_LPC_RCBA_REG, &rcba);
5038 0 : if (!(rcba & INTEL_LPC_RCBA_ENABLE))
5039 : return -EINVAL;
5040 :
5041 0 : rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
5042 : PAGE_ALIGN(INTEL_UPDCR_REG));
5043 0 : if (!rcba_mem)
5044 : return -ENOMEM;
5045 :
5046 : /*
5047 : * The BSPR can disallow peer cycles, but it's set by soft strap and
5048 : * therefore read-only. If both posted and non-posted peer cycles are
5049 : * disallowed, we're ok. If either are allowed, then we need to use
5050 : * the UPDCR to disable peer decodes for each port. This provides the
5051 : * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5052 : */
5053 0 : bspr = readl(rcba_mem + INTEL_BSPR_REG);
5054 0 : bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5055 0 : if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5056 0 : updcr = readl(rcba_mem + INTEL_UPDCR_REG);
5057 0 : if (updcr & INTEL_UPDCR_REG_MASK) {
5058 0 : pci_info(dev, "Disabling UPDCR peer decodes\n");
5059 0 : updcr &= ~INTEL_UPDCR_REG_MASK;
5060 0 : writel(updcr, rcba_mem + INTEL_UPDCR_REG);
5061 : }
5062 : }
5063 :
5064 0 : iounmap(rcba_mem);
5065 0 : return 0;
5066 : }
5067 :
5068 : /* Miscellaneous Port Configuration register */
5069 : #define INTEL_MPC_REG 0xd8
5070 : /* MPC: Invalid Receive Bus Number Check Enable */
5071 : #define INTEL_MPC_REG_IRBNCE (1 << 26)
5072 :
5073 0 : static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5074 : {
5075 : u32 mpc;
5076 :
5077 : /*
5078 : * When enabled, the IRBNCE bit of the MPC register enables the
5079 : * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5080 : * ensures that requester IDs fall within the bus number range
5081 : * of the bridge. Enable if not already.
5082 : */
5083 0 : pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
5084 0 : if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5085 0 : pci_info(dev, "Enabling MPC IRBNCE\n");
5086 0 : mpc |= INTEL_MPC_REG_IRBNCE;
5087 0 : pci_write_config_word(dev, INTEL_MPC_REG, mpc);
5088 : }
5089 0 : }
5090 :
5091 : /*
5092 : * Currently this quirk does the equivalent of
5093 : * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5094 : *
5095 : * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5096 : * if dev->external_facing || dev->untrusted
5097 : */
5098 0 : static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5099 : {
5100 0 : if (!pci_quirk_intel_pch_acs_match(dev))
5101 : return -ENOTTY;
5102 :
5103 0 : if (pci_quirk_enable_intel_lpc_acs(dev)) {
5104 0 : pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5105 0 : return 0;
5106 : }
5107 :
5108 0 : pci_quirk_enable_intel_rp_mpc_acs(dev);
5109 :
5110 0 : dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5111 :
5112 0 : pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5113 :
5114 0 : return 0;
5115 : }
5116 :
5117 0 : static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5118 : {
5119 : int pos;
5120 : u32 cap, ctrl;
5121 :
5122 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
5123 : return -ENOTTY;
5124 :
5125 0 : pos = dev->acs_cap;
5126 0 : if (!pos)
5127 : return -ENOTTY;
5128 :
5129 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5130 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5131 :
5132 0 : ctrl |= (cap & PCI_ACS_SV);
5133 0 : ctrl |= (cap & PCI_ACS_RR);
5134 0 : ctrl |= (cap & PCI_ACS_CR);
5135 0 : ctrl |= (cap & PCI_ACS_UF);
5136 :
5137 0 : if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
5138 0 : ctrl |= (cap & PCI_ACS_TB);
5139 :
5140 0 : pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5141 :
5142 0 : pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5143 :
5144 0 : return 0;
5145 : }
5146 :
5147 0 : static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5148 : {
5149 : int pos;
5150 : u32 cap, ctrl;
5151 :
5152 0 : if (!pci_quirk_intel_spt_pch_acs_match(dev))
5153 : return -ENOTTY;
5154 :
5155 0 : pos = dev->acs_cap;
5156 0 : if (!pos)
5157 : return -ENOTTY;
5158 :
5159 0 : pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5160 0 : pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5161 :
5162 0 : ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5163 :
5164 0 : pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5165 :
5166 0 : pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5167 :
5168 0 : return 0;
5169 : }
5170 :
5171 : static const struct pci_dev_acs_ops {
5172 : u16 vendor;
5173 : u16 device;
5174 : int (*enable_acs)(struct pci_dev *dev);
5175 : int (*disable_acs_redir)(struct pci_dev *dev);
5176 : } pci_dev_acs_ops[] = {
5177 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5178 : .enable_acs = pci_quirk_enable_intel_pch_acs,
5179 : },
5180 : { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5181 : .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5182 : .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5183 : },
5184 : };
5185 :
5186 0 : int pci_dev_specific_enable_acs(struct pci_dev *dev)
5187 : {
5188 : const struct pci_dev_acs_ops *p;
5189 : int i, ret;
5190 :
5191 0 : for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5192 0 : p = &pci_dev_acs_ops[i];
5193 0 : if ((p->vendor == dev->vendor ||
5194 0 : p->vendor == (u16)PCI_ANY_ID) &&
5195 0 : (p->device == dev->device ||
5196 0 : p->device == (u16)PCI_ANY_ID) &&
5197 0 : p->enable_acs) {
5198 0 : ret = p->enable_acs(dev);
5199 0 : if (ret >= 0)
5200 : return ret;
5201 : }
5202 : }
5203 :
5204 : return -ENOTTY;
5205 : }
5206 :
5207 0 : int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5208 : {
5209 : const struct pci_dev_acs_ops *p;
5210 : int i, ret;
5211 :
5212 0 : for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5213 0 : p = &pci_dev_acs_ops[i];
5214 0 : if ((p->vendor == dev->vendor ||
5215 0 : p->vendor == (u16)PCI_ANY_ID) &&
5216 0 : (p->device == dev->device ||
5217 0 : p->device == (u16)PCI_ANY_ID) &&
5218 0 : p->disable_acs_redir) {
5219 0 : ret = p->disable_acs_redir(dev);
5220 0 : if (ret >= 0)
5221 : return ret;
5222 : }
5223 : }
5224 :
5225 : return -ENOTTY;
5226 : }
5227 :
5228 : /*
5229 : * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5230 : * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5231 : * Next Capability pointer in the MSI Capability Structure should point to
5232 : * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5233 : * the list.
5234 : */
5235 0 : static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5236 : {
5237 0 : int pos, i = 0;
5238 : u8 next_cap;
5239 : u16 reg16, *cap;
5240 : struct pci_cap_saved_state *state;
5241 :
5242 : /* Bail if the hardware bug is fixed */
5243 0 : if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5244 0 : return;
5245 :
5246 : /* Bail if MSI Capability Structure is not found for some reason */
5247 0 : pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5248 0 : if (!pos)
5249 : return;
5250 :
5251 : /*
5252 : * Bail if Next Capability pointer in the MSI Capability Structure
5253 : * is not the expected incorrect 0x00.
5254 : */
5255 0 : pci_read_config_byte(pdev, pos + 1, &next_cap);
5256 0 : if (next_cap)
5257 : return;
5258 :
5259 : /*
5260 : * PCIe Capability Structure is expected to be at 0x50 and should
5261 : * terminate the list (Next Capability pointer is 0x00). Verify
5262 : * Capability Id and Next Capability pointer is as expected.
5263 : * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5264 : * to correctly set kernel data structures which have already been
5265 : * set incorrectly due to the hardware bug.
5266 : */
5267 0 : pos = 0x50;
5268 0 : pci_read_config_word(pdev, pos, ®16);
5269 0 : if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5270 : u32 status;
5271 : #ifndef PCI_EXP_SAVE_REGS
5272 : #define PCI_EXP_SAVE_REGS 7
5273 : #endif
5274 0 : int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5275 :
5276 0 : pdev->pcie_cap = pos;
5277 0 : pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5278 0 : pdev->pcie_flags_reg = reg16;
5279 0 : pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5280 0 : pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5281 :
5282 0 : pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5283 0 : if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5284 0 : PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5285 0 : pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5286 :
5287 0 : if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5288 0 : return;
5289 :
5290 : /* Save PCIe cap */
5291 0 : state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5292 0 : if (!state)
5293 : return;
5294 :
5295 0 : state->cap.cap_nr = PCI_CAP_ID_EXP;
5296 0 : state->cap.cap_extended = 0;
5297 0 : state->cap.size = size;
5298 0 : cap = (u16 *)&state->cap.data[0];
5299 0 : pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5300 0 : pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5301 0 : pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5302 0 : pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5303 0 : pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5304 0 : pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5305 0 : pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5306 0 : hlist_add_head(&state->next, &pdev->saved_cap_space);
5307 : }
5308 : }
5309 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5310 :
5311 : /*
5312 : * FLR may cause the following to devices to hang:
5313 : *
5314 : * AMD Starship/Matisse HD Audio Controller 0x1487
5315 : * AMD Starship USB 3.0 Host Controller 0x148c
5316 : * AMD Matisse USB 3.0 Host Controller 0x149c
5317 : * Intel 82579LM Gigabit Ethernet Controller 0x1502
5318 : * Intel 82579V Gigabit Ethernet Controller 0x1503
5319 : *
5320 : */
5321 0 : static void quirk_no_flr(struct pci_dev *dev)
5322 : {
5323 0 : dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5324 0 : }
5325 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5326 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5327 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5328 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5329 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5330 :
5331 0 : static void quirk_no_ext_tags(struct pci_dev *pdev)
5332 : {
5333 0 : struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5334 :
5335 0 : if (!bridge)
5336 : return;
5337 :
5338 0 : bridge->no_ext_tags = 1;
5339 0 : pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5340 :
5341 0 : pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5342 : }
5343 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5344 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5345 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5346 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5347 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5348 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5349 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5350 :
5351 : #ifdef CONFIG_PCI_ATS
5352 : /*
5353 : * Some devices require additional driver setup to enable ATS. Don't use
5354 : * ATS for those devices as ATS will be enabled before the driver has had a
5355 : * chance to load and configure the device.
5356 : */
5357 : static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5358 : {
5359 : if (pdev->device == 0x15d8) {
5360 : if (pdev->revision == 0xcf &&
5361 : pdev->subsystem_vendor == 0xea50 &&
5362 : (pdev->subsystem_device == 0xce19 ||
5363 : pdev->subsystem_device == 0xcc10 ||
5364 : pdev->subsystem_device == 0xcc08))
5365 : goto no_ats;
5366 : else
5367 : return;
5368 : }
5369 :
5370 : no_ats:
5371 : pci_info(pdev, "disabling ATS\n");
5372 : pdev->ats_cap = 0;
5373 : }
5374 :
5375 : /* AMD Stoney platform GPU */
5376 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5377 : /* AMD Iceland dGPU */
5378 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5379 : /* AMD Navi10 dGPU */
5380 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5381 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5382 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5383 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5384 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5385 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5386 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5387 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5388 : /* AMD Navi14 dGPU */
5389 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5390 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5391 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5392 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5393 : /* AMD Raven platform iGPU */
5394 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5395 : #endif /* CONFIG_PCI_ATS */
5396 :
5397 : /* Freescale PCIe doesn't support MSI in RC mode */
5398 0 : static void quirk_fsl_no_msi(struct pci_dev *pdev)
5399 : {
5400 0 : if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5401 0 : pdev->no_msi = 1;
5402 0 : }
5403 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5404 :
5405 : /*
5406 : * Although not allowed by the spec, some multi-function devices have
5407 : * dependencies of one function (consumer) on another (supplier). For the
5408 : * consumer to work in D0, the supplier must also be in D0. Create a
5409 : * device link from the consumer to the supplier to enforce this
5410 : * dependency. Runtime PM is allowed by default on the consumer to prevent
5411 : * it from permanently keeping the supplier awake.
5412 : */
5413 0 : static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5414 : unsigned int supplier, unsigned int class,
5415 : unsigned int class_shift)
5416 : {
5417 : struct pci_dev *supplier_pdev;
5418 :
5419 0 : if (PCI_FUNC(pdev->devfn) != consumer)
5420 : return;
5421 :
5422 0 : supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5423 0 : pdev->bus->number,
5424 0 : PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5425 0 : if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5426 0 : pci_dev_put(supplier_pdev);
5427 0 : return;
5428 : }
5429 :
5430 0 : if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5431 : DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5432 0 : pci_info(pdev, "D0 power state depends on %s\n",
5433 : pci_name(supplier_pdev));
5434 : else
5435 0 : pci_err(pdev, "Cannot enforce power dependency on %s\n",
5436 : pci_name(supplier_pdev));
5437 :
5438 0 : pm_runtime_allow(&pdev->dev);
5439 0 : pci_dev_put(supplier_pdev);
5440 : }
5441 :
5442 : /*
5443 : * Create device link for GPUs with integrated HDA controller for streaming
5444 : * audio to attached displays.
5445 : */
5446 0 : static void quirk_gpu_hda(struct pci_dev *hda)
5447 : {
5448 0 : pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5449 0 : }
5450 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5451 : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5452 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5453 : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5454 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5455 : PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5456 :
5457 : /*
5458 : * Create device link for GPUs with integrated USB xHCI Host
5459 : * controller to VGA.
5460 : */
5461 0 : static void quirk_gpu_usb(struct pci_dev *usb)
5462 : {
5463 0 : pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5464 0 : }
5465 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5466 : PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5467 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5468 : PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5469 :
5470 : /*
5471 : * Create device link for GPUs with integrated Type-C UCSI controller
5472 : * to VGA. Currently there is no class code defined for UCSI device over PCI
5473 : * so using UNKNOWN class for now and it will be updated when UCSI
5474 : * over PCI gets a class code.
5475 : */
5476 : #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5477 0 : static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5478 : {
5479 0 : pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5480 0 : }
5481 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5482 : PCI_CLASS_SERIAL_UNKNOWN, 8,
5483 : quirk_gpu_usb_typec_ucsi);
5484 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5485 : PCI_CLASS_SERIAL_UNKNOWN, 8,
5486 : quirk_gpu_usb_typec_ucsi);
5487 :
5488 : /*
5489 : * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5490 : * disabled. https://devtalk.nvidia.com/default/topic/1024022
5491 : */
5492 0 : static void quirk_nvidia_hda(struct pci_dev *gpu)
5493 : {
5494 : u8 hdr_type;
5495 : u32 val;
5496 :
5497 : /* There was no integrated HDA controller before MCP89 */
5498 0 : if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5499 0 : return;
5500 :
5501 : /* Bit 25 at offset 0x488 enables the HDA controller */
5502 0 : pci_read_config_dword(gpu, 0x488, &val);
5503 0 : if (val & BIT(25))
5504 : return;
5505 :
5506 0 : pci_info(gpu, "Enabling HDA controller\n");
5507 0 : pci_write_config_dword(gpu, 0x488, val | BIT(25));
5508 :
5509 : /* The GPU becomes a multi-function device when the HDA is enabled */
5510 0 : pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5511 0 : gpu->multifunction = !!(hdr_type & 0x80);
5512 : }
5513 : DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5514 : PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5515 : DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5516 : PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5517 :
5518 : /*
5519 : * Some IDT switches incorrectly flag an ACS Source Validation error on
5520 : * completions for config read requests even though PCIe r4.0, sec
5521 : * 6.12.1.1, says that completions are never affected by ACS Source
5522 : * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5523 : *
5524 : * Item #36 - Downstream port applies ACS Source Validation to Completions
5525 : * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5526 : * completions are never affected by ACS Source Validation. However,
5527 : * completions received by a downstream port of the PCIe switch from a
5528 : * device that has not yet captured a PCIe bus number are incorrectly
5529 : * dropped by ACS Source Validation by the switch downstream port.
5530 : *
5531 : * The workaround suggested by IDT is to issue a config write to the
5532 : * downstream device before issuing the first config read. This allows the
5533 : * downstream device to capture its bus and device numbers (see PCIe r4.0,
5534 : * sec 2.2.9), thus avoiding the ACS error on the completion.
5535 : *
5536 : * However, we don't know when the device is ready to accept the config
5537 : * write, so we do config reads until we receive a non-Config Request Retry
5538 : * Status, then do the config write.
5539 : *
5540 : * To avoid hitting the erratum when doing the config reads, we disable ACS
5541 : * SV around this process.
5542 : */
5543 0 : int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5544 : {
5545 : int pos;
5546 0 : u16 ctrl = 0;
5547 : bool found;
5548 0 : struct pci_dev *bridge = bus->self;
5549 :
5550 0 : pos = bridge->acs_cap;
5551 :
5552 : /* Disable ACS SV before initial config reads */
5553 0 : if (pos) {
5554 0 : pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5555 0 : if (ctrl & PCI_ACS_SV)
5556 0 : pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5557 : ctrl & ~PCI_ACS_SV);
5558 : }
5559 :
5560 0 : found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5561 :
5562 : /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5563 0 : if (found)
5564 0 : pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5565 :
5566 : /* Re-enable ACS_SV if it was previously enabled */
5567 0 : if (ctrl & PCI_ACS_SV)
5568 0 : pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5569 :
5570 0 : return found;
5571 : }
5572 :
5573 : /*
5574 : * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5575 : * NT endpoints via the internal switch fabric. These IDs replace the
5576 : * originating requestor ID TLPs which access host memory on peer NTB
5577 : * ports. Therefore, all proxy IDs must be aliased to the NTB device
5578 : * to permit access when the IOMMU is turned on.
5579 : */
5580 0 : static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5581 : {
5582 : void __iomem *mmio;
5583 : struct ntb_info_regs __iomem *mmio_ntb;
5584 : struct ntb_ctrl_regs __iomem *mmio_ctrl;
5585 : u64 partition_map;
5586 : u8 partition;
5587 : int pp;
5588 :
5589 0 : if (pci_enable_device(pdev)) {
5590 0 : pci_err(pdev, "Cannot enable Switchtec device\n");
5591 0 : return;
5592 : }
5593 :
5594 0 : mmio = pci_iomap(pdev, 0, 0);
5595 0 : if (mmio == NULL) {
5596 0 : pci_disable_device(pdev);
5597 0 : pci_err(pdev, "Cannot iomap Switchtec device\n");
5598 0 : return;
5599 : }
5600 :
5601 0 : pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5602 :
5603 0 : mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5604 0 : mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5605 :
5606 0 : partition = ioread8(&mmio_ntb->partition_id);
5607 :
5608 0 : partition_map = ioread32(&mmio_ntb->ep_map);
5609 0 : partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5610 0 : partition_map &= ~(1ULL << partition);
5611 :
5612 0 : for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5613 : struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5614 0 : u32 table_sz = 0;
5615 : int te;
5616 :
5617 0 : if (!(partition_map & (1ULL << pp)))
5618 0 : continue;
5619 :
5620 : pci_dbg(pdev, "Processing partition %d\n", pp);
5621 :
5622 0 : mmio_peer_ctrl = &mmio_ctrl[pp];
5623 :
5624 0 : table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5625 0 : if (!table_sz) {
5626 0 : pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5627 0 : continue;
5628 : }
5629 :
5630 0 : if (table_sz > 512) {
5631 0 : pci_warn(pdev,
5632 : "Invalid Switchtec partition %d table_sz %d\n",
5633 : pp, table_sz);
5634 0 : continue;
5635 : }
5636 :
5637 0 : for (te = 0; te < table_sz; te++) {
5638 : u32 rid_entry;
5639 : u8 devfn;
5640 :
5641 0 : rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5642 0 : devfn = (rid_entry >> 1) & 0xFF;
5643 : pci_dbg(pdev,
5644 : "Aliasing Partition %d Proxy ID %02x.%d\n",
5645 : pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5646 0 : pci_add_dma_alias(pdev, devfn, 1);
5647 : }
5648 : }
5649 :
5650 0 : pci_iounmap(pdev, mmio);
5651 0 : pci_disable_device(pdev);
5652 : }
5653 : #define SWITCHTEC_QUIRK(vid) \
5654 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5655 : PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5656 :
5657 : SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5658 : SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5659 : SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5660 : SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5661 : SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5662 : SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5663 : SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5664 : SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5665 : SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5666 : SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5667 : SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5668 : SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5669 : SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5670 : SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5671 : SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5672 : SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5673 : SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5674 : SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5675 : SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5676 : SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5677 : SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5678 : SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5679 : SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5680 : SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5681 : SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5682 : SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5683 : SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5684 : SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5685 : SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5686 : SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5687 : SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5688 : SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5689 : SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5690 : SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5691 : SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5692 : SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5693 : SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5694 : SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5695 : SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5696 : SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5697 : SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5698 : SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5699 : SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5700 : SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5701 : SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5702 : SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5703 : SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5704 : SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5705 : SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */
5706 : SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */
5707 : SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */
5708 : SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */
5709 : SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */
5710 : SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */
5711 : SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */
5712 : SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */
5713 : SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */
5714 :
5715 : /*
5716 : * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5717 : * These IDs are used to forward responses to the originator on the other
5718 : * side of the NTB. Alias all possible IDs to the NTB to permit access when
5719 : * the IOMMU is turned on.
5720 : */
5721 0 : static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5722 : {
5723 0 : pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5724 : /* PLX NTB may use all 256 devfns */
5725 0 : pci_add_dma_alias(pdev, 0, 256);
5726 0 : }
5727 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5728 : DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5729 :
5730 : /*
5731 : * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5732 : * not always reset the secondary Nvidia GPU between reboots if the system
5733 : * is configured to use Hybrid Graphics mode. This results in the GPU
5734 : * being left in whatever state it was in during the *previous* boot, which
5735 : * causes spurious interrupts from the GPU, which in turn causes us to
5736 : * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5737 : * this also completely breaks nouveau.
5738 : *
5739 : * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5740 : * clean state and fixes all these issues.
5741 : *
5742 : * When the machine is configured in Dedicated display mode, the issue
5743 : * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5744 : * mode, so we can detect that and avoid resetting it.
5745 : */
5746 0 : static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5747 : {
5748 : void __iomem *map;
5749 : int ret;
5750 :
5751 0 : if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5752 0 : pdev->subsystem_device != 0x222e ||
5753 0 : !pci_reset_supported(pdev))
5754 : return;
5755 :
5756 0 : if (pci_enable_device_mem(pdev))
5757 : return;
5758 :
5759 : /*
5760 : * Based on nvkm_device_ctor() in
5761 : * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5762 : */
5763 0 : map = pci_iomap(pdev, 0, 0x23000);
5764 0 : if (!map) {
5765 0 : pci_err(pdev, "Can't map MMIO space\n");
5766 0 : goto out_disable;
5767 : }
5768 :
5769 : /*
5770 : * Make sure the GPU looks like it's been POSTed before resetting
5771 : * it.
5772 : */
5773 0 : if (ioread32(map + 0x2240c) & 0x2) {
5774 0 : pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5775 0 : ret = pci_reset_bus(pdev);
5776 0 : if (ret < 0)
5777 0 : pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5778 : }
5779 :
5780 0 : iounmap(map);
5781 : out_disable:
5782 0 : pci_disable_device(pdev);
5783 : }
5784 : DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5785 : PCI_CLASS_DISPLAY_VGA, 8,
5786 : quirk_reset_lenovo_thinkpad_p50_nvgpu);
5787 :
5788 : /*
5789 : * Device [1b21:2142]
5790 : * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5791 : */
5792 0 : static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5793 : {
5794 0 : pci_info(dev, "PME# does not work under D0, disabling it\n");
5795 0 : dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5796 0 : }
5797 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5798 :
5799 : /*
5800 : * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5801 : *
5802 : * These devices advertise PME# support in all power states but don't
5803 : * reliably assert it.
5804 : *
5805 : * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5806 : * says "The MSI Function is not implemented on this device" in chapters
5807 : * 7.3.27, 7.3.29-7.3.31.
5808 : */
5809 0 : static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
5810 : {
5811 : #ifdef CONFIG_PCI_MSI
5812 0 : pci_info(dev, "MSI is not implemented on this device, disabling it\n");
5813 0 : dev->no_msi = 1;
5814 : #endif
5815 0 : pci_info(dev, "PME# is unreliable, disabling it\n");
5816 0 : dev->pme_support = 0;
5817 0 : }
5818 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
5819 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
5820 :
5821 0 : static void apex_pci_fixup_class(struct pci_dev *pdev)
5822 : {
5823 0 : pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5824 0 : }
5825 : DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5826 : PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
5827 :
5828 : /*
5829 : * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
5830 : * ACS P2P Request Redirect is not functional
5831 : *
5832 : * When ACS P2P Request Redirect is enabled and bandwidth is not balanced
5833 : * between upstream and downstream ports, packets are queued in an internal
5834 : * buffer until CPLD packet. The workaround is to use the switch in store and
5835 : * forward mode.
5836 : */
5837 : #define PI7C9X2Gxxx_MODE_REG 0x74
5838 : #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0)
5839 0 : static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev)
5840 : {
5841 : struct pci_dev *upstream;
5842 : u16 val;
5843 :
5844 : /* Downstream ports only */
5845 0 : if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
5846 0 : return;
5847 :
5848 : /* Check for ACS P2P Request Redirect use */
5849 0 : if (!pdev->acs_cap)
5850 : return;
5851 0 : pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val);
5852 0 : if (!(val & PCI_ACS_RR))
5853 : return;
5854 :
5855 0 : upstream = pci_upstream_bridge(pdev);
5856 0 : if (!upstream)
5857 : return;
5858 :
5859 0 : pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val);
5860 0 : if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) {
5861 0 : pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n");
5862 0 : pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val |
5863 : PI7C9X2Gxxx_STORE_FORWARD_MODE);
5864 : }
5865 : }
5866 : /*
5867 : * Apply fixup on enable and on resume, in order to apply the fix up whenever
5868 : * ACS configuration changes or switch mode is reset
5869 : */
5870 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
5871 : pci_fixup_pericom_acs_store_forward);
5872 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
5873 : pci_fixup_pericom_acs_store_forward);
5874 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
5875 : pci_fixup_pericom_acs_store_forward);
5876 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
5877 : pci_fixup_pericom_acs_store_forward);
5878 : DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
5879 : pci_fixup_pericom_acs_store_forward);
5880 : DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
5881 : pci_fixup_pericom_acs_store_forward);
5882 :
5883 0 : static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
5884 : {
5885 0 : pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
5886 0 : }
5887 : DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
5888 :
5889 0 : static void rom_bar_overlap_defect(struct pci_dev *dev)
5890 : {
5891 0 : pci_info(dev, "working around ROM BAR overlap defect\n");
5892 0 : dev->rom_bar_overlap = 1;
5893 0 : }
5894 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
5895 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
5896 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
5897 : DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
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