Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0 */
2 : #ifndef _LINUX_IRQ_H
3 : #define _LINUX_IRQ_H
4 :
5 : /*
6 : * Please do not include this file in generic code. There is currently
7 : * no requirement for any architecture to implement anything held
8 : * within this file.
9 : *
10 : * Thanks. --rmk
11 : */
12 :
13 : #include <linux/cache.h>
14 : #include <linux/spinlock.h>
15 : #include <linux/cpumask.h>
16 : #include <linux/irqhandler.h>
17 : #include <linux/irqreturn.h>
18 : #include <linux/irqnr.h>
19 : #include <linux/topology.h>
20 : #include <linux/io.h>
21 : #include <linux/slab.h>
22 :
23 : #include <asm/irq.h>
24 : #include <asm/ptrace.h>
25 : #include <asm/irq_regs.h>
26 :
27 : struct seq_file;
28 : struct module;
29 : struct msi_msg;
30 : struct irq_affinity_desc;
31 : enum irqchip_irq_state;
32 :
33 : /*
34 : * IRQ line status.
35 : *
36 : * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
37 : *
38 : * IRQ_TYPE_NONE - default, unspecified type
39 : * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 : * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 : * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 : * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 : * IRQ_TYPE_LEVEL_LOW - low level triggered
44 : * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 : * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 : * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 : * to setup the HW to a sane default (used
48 : * by irqdomain map() callbacks to synchronize
49 : * the HW state and SW flags for a newly
50 : * allocated descriptor).
51 : *
52 : * IRQ_TYPE_PROBE - Special flag for probing in progress
53 : *
54 : * Bits which can be modified via irq_set/clear/modify_status_flags()
55 : * IRQ_LEVEL - Interrupt is level type. Will be also
56 : * updated in the code when the above trigger
57 : * bits are modified via irq_set_irq_type()
58 : * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 : * it from affinity setting
60 : * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 : * IRQ_NOREQUEST - Interrupt cannot be requested via
62 : * request_irq()
63 : * IRQ_NOTHREAD - Interrupt cannot be threaded
64 : * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
65 : * request/setup_irq()
66 : * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 : * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
68 : * IRQ_NESTED_THREAD - Interrupt nests into another thread
69 : * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
70 : * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 : * it from the spurious interrupt detection
72 : * mechanism and from core side polling.
73 : * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
74 : * IRQ_HIDDEN - Don't show up in /proc/interrupts
75 : * IRQ_NO_DEBUG - Exclude from note_interrupt() debugging
76 : */
77 : enum {
78 : IRQ_TYPE_NONE = 0x00000000,
79 : IRQ_TYPE_EDGE_RISING = 0x00000001,
80 : IRQ_TYPE_EDGE_FALLING = 0x00000002,
81 : IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 : IRQ_TYPE_LEVEL_HIGH = 0x00000004,
83 : IRQ_TYPE_LEVEL_LOW = 0x00000008,
84 : IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 : IRQ_TYPE_SENSE_MASK = 0x0000000f,
86 : IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
87 :
88 : IRQ_TYPE_PROBE = 0x00000010,
89 :
90 : IRQ_LEVEL = (1 << 8),
91 : IRQ_PER_CPU = (1 << 9),
92 : IRQ_NOPROBE = (1 << 10),
93 : IRQ_NOREQUEST = (1 << 11),
94 : IRQ_NOAUTOEN = (1 << 12),
95 : IRQ_NO_BALANCING = (1 << 13),
96 : IRQ_MOVE_PCNTXT = (1 << 14),
97 : IRQ_NESTED_THREAD = (1 << 15),
98 : IRQ_NOTHREAD = (1 << 16),
99 : IRQ_PER_CPU_DEVID = (1 << 17),
100 : IRQ_IS_POLLED = (1 << 18),
101 : IRQ_DISABLE_UNLAZY = (1 << 19),
102 : IRQ_HIDDEN = (1 << 20),
103 : IRQ_NO_DEBUG = (1 << 21),
104 : };
105 :
106 : #define IRQF_MODIFY_MASK \
107 : (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
108 : IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
109 : IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
110 : IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
111 :
112 : #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
113 :
114 : /*
115 : * Return value for chip->irq_set_affinity()
116 : *
117 : * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
118 : * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
119 : * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
120 : * support stacked irqchips, which indicates skipping
121 : * all descendant irqchips.
122 : */
123 : enum {
124 : IRQ_SET_MASK_OK = 0,
125 : IRQ_SET_MASK_OK_NOCOPY,
126 : IRQ_SET_MASK_OK_DONE,
127 : };
128 :
129 : struct msi_desc;
130 : struct irq_domain;
131 :
132 : /**
133 : * struct irq_common_data - per irq data shared by all irqchips
134 : * @state_use_accessors: status information for irq chip functions.
135 : * Use accessor functions to deal with it
136 : * @node: node index useful for balancing
137 : * @handler_data: per-IRQ data for the irq_chip methods
138 : * @affinity: IRQ affinity on SMP. If this is an IPI
139 : * related irq, then this is the mask of the
140 : * CPUs to which an IPI can be sent.
141 : * @effective_affinity: The effective IRQ affinity on SMP as some irq
142 : * chips do not allow multi CPU destinations.
143 : * A subset of @affinity.
144 : * @msi_desc: MSI descriptor
145 : * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
146 : */
147 : struct irq_common_data {
148 : unsigned int __private state_use_accessors;
149 : #ifdef CONFIG_NUMA
150 : unsigned int node;
151 : #endif
152 : void *handler_data;
153 : struct msi_desc *msi_desc;
154 : cpumask_var_t affinity;
155 : #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
156 : cpumask_var_t effective_affinity;
157 : #endif
158 : #ifdef CONFIG_GENERIC_IRQ_IPI
159 : unsigned int ipi_offset;
160 : #endif
161 : };
162 :
163 : /**
164 : * struct irq_data - per irq chip data passed down to chip functions
165 : * @mask: precomputed bitmask for accessing the chip registers
166 : * @irq: interrupt number
167 : * @hwirq: hardware interrupt number, local to the interrupt domain
168 : * @common: point to data shared by all irqchips
169 : * @chip: low level interrupt hardware access
170 : * @domain: Interrupt translation domain; responsible for mapping
171 : * between hwirq number and linux irq number.
172 : * @parent_data: pointer to parent struct irq_data to support hierarchy
173 : * irq_domain
174 : * @chip_data: platform-specific per-chip private data for the chip
175 : * methods, to allow shared chip implementations
176 : */
177 : struct irq_data {
178 : u32 mask;
179 : unsigned int irq;
180 : unsigned long hwirq;
181 : struct irq_common_data *common;
182 : struct irq_chip *chip;
183 : struct irq_domain *domain;
184 : #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
185 : struct irq_data *parent_data;
186 : #endif
187 : void *chip_data;
188 : };
189 :
190 : /*
191 : * Bit masks for irq_common_data.state_use_accessors
192 : *
193 : * IRQD_TRIGGER_MASK - Mask for the trigger type bits
194 : * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
195 : * IRQD_ACTIVATED - Interrupt has already been activated
196 : * IRQD_NO_BALANCING - Balancing disabled for this IRQ
197 : * IRQD_PER_CPU - Interrupt is per cpu
198 : * IRQD_AFFINITY_SET - Interrupt affinity was set
199 : * IRQD_LEVEL - Interrupt is level triggered
200 : * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
201 : * from suspend
202 : * IRQD_MOVE_PCNTXT - Interrupt can be moved in process
203 : * context
204 : * IRQD_IRQ_DISABLED - Disabled state of the interrupt
205 : * IRQD_IRQ_MASKED - Masked state of the interrupt
206 : * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
207 : * IRQD_WAKEUP_ARMED - Wakeup mode armed
208 : * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
209 : * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
210 : * IRQD_IRQ_STARTED - Startup state of the interrupt
211 : * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
212 : * mask. Applies only to affinity managed irqs.
213 : * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
214 : * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
215 : * IRQD_CAN_RESERVE - Can use reservation mode
216 : * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
217 : * required
218 : * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
219 : * from actual interrupt context.
220 : * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
221 : * irq_chip::irq_set_affinity() when deactivated.
222 : * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if
223 : * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set.
224 : */
225 : enum {
226 : IRQD_TRIGGER_MASK = 0xf,
227 : IRQD_SETAFFINITY_PENDING = (1 << 8),
228 : IRQD_ACTIVATED = (1 << 9),
229 : IRQD_NO_BALANCING = (1 << 10),
230 : IRQD_PER_CPU = (1 << 11),
231 : IRQD_AFFINITY_SET = (1 << 12),
232 : IRQD_LEVEL = (1 << 13),
233 : IRQD_WAKEUP_STATE = (1 << 14),
234 : IRQD_MOVE_PCNTXT = (1 << 15),
235 : IRQD_IRQ_DISABLED = (1 << 16),
236 : IRQD_IRQ_MASKED = (1 << 17),
237 : IRQD_IRQ_INPROGRESS = (1 << 18),
238 : IRQD_WAKEUP_ARMED = (1 << 19),
239 : IRQD_FORWARDED_TO_VCPU = (1 << 20),
240 : IRQD_AFFINITY_MANAGED = (1 << 21),
241 : IRQD_IRQ_STARTED = (1 << 22),
242 : IRQD_MANAGED_SHUTDOWN = (1 << 23),
243 : IRQD_SINGLE_TARGET = (1 << 24),
244 : IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
245 : IRQD_CAN_RESERVE = (1 << 26),
246 : IRQD_MSI_NOMASK_QUIRK = (1 << 27),
247 : IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28),
248 : IRQD_AFFINITY_ON_ACTIVATE = (1 << 29),
249 : IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30),
250 : };
251 :
252 : #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
253 :
254 : static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
255 : {
256 : return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
257 : }
258 :
259 : static inline bool irqd_is_per_cpu(struct irq_data *d)
260 : {
261 : return __irqd_to_state(d) & IRQD_PER_CPU;
262 : }
263 :
264 : static inline bool irqd_can_balance(struct irq_data *d)
265 : {
266 : return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
267 : }
268 :
269 : static inline bool irqd_affinity_was_set(struct irq_data *d)
270 : {
271 : return __irqd_to_state(d) & IRQD_AFFINITY_SET;
272 : }
273 :
274 : static inline void irqd_mark_affinity_was_set(struct irq_data *d)
275 : {
276 : __irqd_to_state(d) |= IRQD_AFFINITY_SET;
277 : }
278 :
279 : static inline bool irqd_trigger_type_was_set(struct irq_data *d)
280 : {
281 0 : return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
282 : }
283 :
284 : static inline u32 irqd_get_trigger_type(struct irq_data *d)
285 : {
286 2 : return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
287 : }
288 :
289 : /*
290 : * Must only be called inside irq_chip.irq_set_type() functions or
291 : * from the DT/ACPI setup code.
292 : */
293 : static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
294 : {
295 0 : __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
296 0 : __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
297 0 : __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
298 : }
299 :
300 : static inline bool irqd_is_level_type(struct irq_data *d)
301 : {
302 : return __irqd_to_state(d) & IRQD_LEVEL;
303 : }
304 :
305 : /*
306 : * Must only be called of irqchip.irq_set_affinity() or low level
307 : * hierarchy domain allocation functions.
308 : */
309 : static inline void irqd_set_single_target(struct irq_data *d)
310 : {
311 : __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
312 : }
313 :
314 : static inline bool irqd_is_single_target(struct irq_data *d)
315 : {
316 : return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
317 : }
318 :
319 : static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
320 : {
321 : __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
322 : }
323 :
324 : static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
325 : {
326 : return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
327 : }
328 :
329 : static inline bool irqd_is_enabled_on_suspend(struct irq_data *d)
330 : {
331 0 : return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND;
332 : }
333 :
334 : static inline bool irqd_is_wakeup_set(struct irq_data *d)
335 : {
336 0 : return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
337 : }
338 :
339 : static inline bool irqd_can_move_in_process_context(struct irq_data *d)
340 : {
341 : return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
342 : }
343 :
344 : static inline bool irqd_irq_disabled(struct irq_data *d)
345 : {
346 15 : return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
347 : }
348 :
349 : static inline bool irqd_irq_masked(struct irq_data *d)
350 : {
351 0 : return __irqd_to_state(d) & IRQD_IRQ_MASKED;
352 : }
353 :
354 : static inline bool irqd_irq_inprogress(struct irq_data *d)
355 : {
356 0 : return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
357 : }
358 :
359 : static inline bool irqd_is_wakeup_armed(struct irq_data *d)
360 : {
361 0 : return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
362 : }
363 :
364 : static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
365 : {
366 : return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
367 : }
368 :
369 : static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
370 : {
371 : __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
372 : }
373 :
374 : static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
375 : {
376 : __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
377 : }
378 :
379 : static inline bool irqd_affinity_is_managed(struct irq_data *d)
380 : {
381 2 : return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
382 : }
383 :
384 : static inline bool irqd_is_activated(struct irq_data *d)
385 : {
386 4 : return __irqd_to_state(d) & IRQD_ACTIVATED;
387 : }
388 :
389 : static inline void irqd_set_activated(struct irq_data *d)
390 : {
391 2 : __irqd_to_state(d) |= IRQD_ACTIVATED;
392 : }
393 :
394 : static inline void irqd_clr_activated(struct irq_data *d)
395 : {
396 0 : __irqd_to_state(d) &= ~IRQD_ACTIVATED;
397 : }
398 :
399 : static inline bool irqd_is_started(struct irq_data *d)
400 : {
401 2 : return __irqd_to_state(d) & IRQD_IRQ_STARTED;
402 : }
403 :
404 : static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
405 : {
406 : return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
407 : }
408 :
409 : static inline void irqd_set_can_reserve(struct irq_data *d)
410 : {
411 : __irqd_to_state(d) |= IRQD_CAN_RESERVE;
412 : }
413 :
414 : static inline void irqd_clr_can_reserve(struct irq_data *d)
415 : {
416 0 : __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
417 : }
418 :
419 : static inline bool irqd_can_reserve(struct irq_data *d)
420 : {
421 : return __irqd_to_state(d) & IRQD_CAN_RESERVE;
422 : }
423 :
424 : static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
425 : {
426 0 : __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
427 : }
428 :
429 : static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
430 : {
431 : __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
432 : }
433 :
434 : static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
435 : {
436 : return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
437 : }
438 :
439 : static inline void irqd_set_affinity_on_activate(struct irq_data *d)
440 : {
441 : __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
442 : }
443 :
444 : static inline bool irqd_affinity_on_activate(struct irq_data *d)
445 : {
446 : return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
447 : }
448 :
449 : #undef __irqd_to_state
450 :
451 : static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
452 : {
453 : return d->hwirq;
454 : }
455 :
456 : /**
457 : * struct irq_chip - hardware interrupt chip descriptor
458 : *
459 : * @name: name for /proc/interrupts
460 : * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
461 : * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
462 : * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
463 : * @irq_disable: disable the interrupt
464 : * @irq_ack: start of a new interrupt
465 : * @irq_mask: mask an interrupt source
466 : * @irq_mask_ack: ack and mask an interrupt source
467 : * @irq_unmask: unmask an interrupt source
468 : * @irq_eoi: end of interrupt
469 : * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
470 : * argument is true, it tells the driver to
471 : * unconditionally apply the affinity setting. Sanity
472 : * checks against the supplied affinity mask are not
473 : * required. This is used for CPU hotplug where the
474 : * target CPU is not yet set in the cpu_online_mask.
475 : * @irq_retrigger: resend an IRQ to the CPU
476 : * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
477 : * @irq_set_wake: enable/disable power-management wake-on of an IRQ
478 : * @irq_bus_lock: function to lock access to slow bus (i2c) chips
479 : * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
480 : * @irq_cpu_online: configure an interrupt source for a secondary CPU
481 : * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
482 : * @irq_suspend: function called from core code on suspend once per
483 : * chip, when one or more interrupts are installed
484 : * @irq_resume: function called from core code on resume once per chip,
485 : * when one ore more interrupts are installed
486 : * @irq_pm_shutdown: function called from core code on shutdown once per chip
487 : * @irq_calc_mask: Optional function to set irq_data.mask for special cases
488 : * @irq_print_chip: optional to print special chip info in show_interrupts
489 : * @irq_request_resources: optional to request resources before calling
490 : * any other callback related to this irq
491 : * @irq_release_resources: optional to release resources acquired with
492 : * irq_request_resources
493 : * @irq_compose_msi_msg: optional to compose message content for MSI
494 : * @irq_write_msi_msg: optional to write message content for MSI
495 : * @irq_get_irqchip_state: return the internal state of an interrupt
496 : * @irq_set_irqchip_state: set the internal state of a interrupt
497 : * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
498 : * @ipi_send_single: send a single IPI to destination cpus
499 : * @ipi_send_mask: send an IPI to destination cpus in cpumask
500 : * @irq_nmi_setup: function called from core code before enabling an NMI
501 : * @irq_nmi_teardown: function called from core code after disabling an NMI
502 : * @flags: chip specific flags
503 : */
504 : struct irq_chip {
505 : const char *name;
506 : unsigned int (*irq_startup)(struct irq_data *data);
507 : void (*irq_shutdown)(struct irq_data *data);
508 : void (*irq_enable)(struct irq_data *data);
509 : void (*irq_disable)(struct irq_data *data);
510 :
511 : void (*irq_ack)(struct irq_data *data);
512 : void (*irq_mask)(struct irq_data *data);
513 : void (*irq_mask_ack)(struct irq_data *data);
514 : void (*irq_unmask)(struct irq_data *data);
515 : void (*irq_eoi)(struct irq_data *data);
516 :
517 : int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
518 : int (*irq_retrigger)(struct irq_data *data);
519 : int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
520 : int (*irq_set_wake)(struct irq_data *data, unsigned int on);
521 :
522 : void (*irq_bus_lock)(struct irq_data *data);
523 : void (*irq_bus_sync_unlock)(struct irq_data *data);
524 :
525 : #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE
526 : void (*irq_cpu_online)(struct irq_data *data);
527 : void (*irq_cpu_offline)(struct irq_data *data);
528 : #endif
529 : void (*irq_suspend)(struct irq_data *data);
530 : void (*irq_resume)(struct irq_data *data);
531 : void (*irq_pm_shutdown)(struct irq_data *data);
532 :
533 : void (*irq_calc_mask)(struct irq_data *data);
534 :
535 : void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
536 : int (*irq_request_resources)(struct irq_data *data);
537 : void (*irq_release_resources)(struct irq_data *data);
538 :
539 : void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
540 : void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
541 :
542 : int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
543 : int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
544 :
545 : int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
546 :
547 : void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
548 : void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
549 :
550 : int (*irq_nmi_setup)(struct irq_data *data);
551 : void (*irq_nmi_teardown)(struct irq_data *data);
552 :
553 : unsigned long flags;
554 : };
555 :
556 : /*
557 : * irq_chip specific flags
558 : *
559 : * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
560 : * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
561 : * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
562 : * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
563 : * when irq enabled
564 : * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
565 : * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
566 : * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
567 : * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs
568 : * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
569 : * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs
570 : * in the suspend path if they are in disabled state
571 : * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
572 : */
573 : enum {
574 : IRQCHIP_SET_TYPE_MASKED = (1 << 0),
575 : IRQCHIP_EOI_IF_HANDLED = (1 << 1),
576 : IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
577 : IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
578 : IRQCHIP_SKIP_SET_WAKE = (1 << 4),
579 : IRQCHIP_ONESHOT_SAFE = (1 << 5),
580 : IRQCHIP_EOI_THREADED = (1 << 6),
581 : IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
582 : IRQCHIP_SUPPORTS_NMI = (1 << 8),
583 : IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9),
584 : IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10),
585 : };
586 :
587 : #include <linux/irqdesc.h>
588 :
589 : /*
590 : * Pick up the arch-dependent methods:
591 : */
592 : #include <asm/hw_irq.h>
593 :
594 : #ifndef NR_IRQS_LEGACY
595 : # define NR_IRQS_LEGACY 0
596 : #endif
597 :
598 : #ifndef ARCH_IRQ_INIT_FLAGS
599 : # define ARCH_IRQ_INIT_FLAGS 0
600 : #endif
601 :
602 : #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
603 :
604 : struct irqaction;
605 : extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
606 : extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
607 :
608 : #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE
609 : extern void irq_cpu_online(void);
610 : extern void irq_cpu_offline(void);
611 : #endif
612 : extern int irq_set_affinity_locked(struct irq_data *data,
613 : const struct cpumask *cpumask, bool force);
614 : extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
615 :
616 : #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
617 : extern void irq_migrate_all_off_this_cpu(void);
618 : extern int irq_affinity_online_cpu(unsigned int cpu);
619 : #else
620 : # define irq_affinity_online_cpu NULL
621 : #endif
622 :
623 : #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
624 : void __irq_move_irq(struct irq_data *data);
625 : static inline void irq_move_irq(struct irq_data *data)
626 : {
627 : if (unlikely(irqd_is_setaffinity_pending(data)))
628 : __irq_move_irq(data);
629 : }
630 : void irq_move_masked_irq(struct irq_data *data);
631 : void irq_force_complete_move(struct irq_desc *desc);
632 : #else
633 : static inline void irq_move_irq(struct irq_data *data) { }
634 : static inline void irq_move_masked_irq(struct irq_data *data) { }
635 : static inline void irq_force_complete_move(struct irq_desc *desc) { }
636 : #endif
637 :
638 : extern int no_irq_affinity;
639 :
640 : #ifdef CONFIG_HARDIRQS_SW_RESEND
641 : int irq_set_parent(int irq, int parent_irq);
642 : #else
643 : static inline int irq_set_parent(int irq, int parent_irq)
644 : {
645 : return 0;
646 : }
647 : #endif
648 :
649 : /*
650 : * Built-in IRQ handlers for various IRQ types,
651 : * callable via desc->handle_irq()
652 : */
653 : extern void handle_level_irq(struct irq_desc *desc);
654 : extern void handle_fasteoi_irq(struct irq_desc *desc);
655 : extern void handle_edge_irq(struct irq_desc *desc);
656 : extern void handle_edge_eoi_irq(struct irq_desc *desc);
657 : extern void handle_simple_irq(struct irq_desc *desc);
658 : extern void handle_untracked_irq(struct irq_desc *desc);
659 : extern void handle_percpu_irq(struct irq_desc *desc);
660 : extern void handle_percpu_devid_irq(struct irq_desc *desc);
661 : extern void handle_bad_irq(struct irq_desc *desc);
662 : extern void handle_nested_irq(unsigned int irq);
663 :
664 : extern void handle_fasteoi_nmi(struct irq_desc *desc);
665 : extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
666 :
667 : extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
668 : extern int irq_chip_pm_get(struct irq_data *data);
669 : extern int irq_chip_pm_put(struct irq_data *data);
670 : #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
671 : extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
672 : extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
673 : extern int irq_chip_set_parent_state(struct irq_data *data,
674 : enum irqchip_irq_state which,
675 : bool val);
676 : extern int irq_chip_get_parent_state(struct irq_data *data,
677 : enum irqchip_irq_state which,
678 : bool *state);
679 : extern void irq_chip_enable_parent(struct irq_data *data);
680 : extern void irq_chip_disable_parent(struct irq_data *data);
681 : extern void irq_chip_ack_parent(struct irq_data *data);
682 : extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
683 : extern void irq_chip_mask_parent(struct irq_data *data);
684 : extern void irq_chip_mask_ack_parent(struct irq_data *data);
685 : extern void irq_chip_unmask_parent(struct irq_data *data);
686 : extern void irq_chip_eoi_parent(struct irq_data *data);
687 : extern int irq_chip_set_affinity_parent(struct irq_data *data,
688 : const struct cpumask *dest,
689 : bool force);
690 : extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
691 : extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
692 : void *vcpu_info);
693 : extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
694 : extern int irq_chip_request_resources_parent(struct irq_data *data);
695 : extern void irq_chip_release_resources_parent(struct irq_data *data);
696 : #endif
697 :
698 : /* Handling of unhandled and spurious interrupts: */
699 : extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
700 :
701 :
702 : /* Enable/disable irq debugging output: */
703 : extern int noirqdebug_setup(char *str);
704 :
705 : /* Checks whether the interrupt can be requested by request_irq(): */
706 : extern int can_request_irq(unsigned int irq, unsigned long irqflags);
707 :
708 : /* Dummy irq-chip implementations: */
709 : extern struct irq_chip no_irq_chip;
710 : extern struct irq_chip dummy_irq_chip;
711 :
712 : extern void
713 : irq_set_chip_and_handler_name(unsigned int irq, const struct irq_chip *chip,
714 : irq_flow_handler_t handle, const char *name);
715 :
716 : static inline void irq_set_chip_and_handler(unsigned int irq,
717 : const struct irq_chip *chip,
718 : irq_flow_handler_t handle)
719 : {
720 64 : irq_set_chip_and_handler_name(irq, chip, handle, NULL);
721 : }
722 :
723 : extern int irq_set_percpu_devid(unsigned int irq);
724 : extern int irq_set_percpu_devid_partition(unsigned int irq,
725 : const struct cpumask *affinity);
726 : extern int irq_get_percpu_devid_partition(unsigned int irq,
727 : struct cpumask *affinity);
728 :
729 : extern void
730 : __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
731 : const char *name);
732 :
733 : static inline void
734 : irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
735 : {
736 0 : __irq_set_handler(irq, handle, 0, NULL);
737 : }
738 :
739 : /*
740 : * Set a highlevel chained flow handler for a given IRQ.
741 : * (a chained handler is automatically enabled and set to
742 : * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
743 : */
744 : static inline void
745 : irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
746 : {
747 : __irq_set_handler(irq, handle, 1, NULL);
748 : }
749 :
750 : /*
751 : * Set a highlevel chained flow handler and its data for a given IRQ.
752 : * (a chained handler is automatically enabled and set to
753 : * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
754 : */
755 : void
756 : irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
757 : void *data);
758 :
759 : void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
760 :
761 : static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
762 : {
763 0 : irq_modify_status(irq, 0, set);
764 : }
765 :
766 : static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
767 : {
768 0 : irq_modify_status(irq, clr, 0);
769 : }
770 :
771 : static inline void irq_set_noprobe(unsigned int irq)
772 : {
773 : irq_modify_status(irq, 0, IRQ_NOPROBE);
774 : }
775 :
776 : static inline void irq_set_probe(unsigned int irq)
777 : {
778 : irq_modify_status(irq, IRQ_NOPROBE, 0);
779 : }
780 :
781 : static inline void irq_set_nothread(unsigned int irq)
782 : {
783 : irq_modify_status(irq, 0, IRQ_NOTHREAD);
784 : }
785 :
786 : static inline void irq_set_thread(unsigned int irq)
787 : {
788 : irq_modify_status(irq, IRQ_NOTHREAD, 0);
789 : }
790 :
791 : static inline void irq_set_nested_thread(unsigned int irq, bool nest)
792 : {
793 : if (nest)
794 : irq_set_status_flags(irq, IRQ_NESTED_THREAD);
795 : else
796 : irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
797 : }
798 :
799 : static inline void irq_set_percpu_devid_flags(unsigned int irq)
800 : {
801 0 : irq_set_status_flags(irq,
802 : IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
803 : IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
804 : }
805 :
806 : /* Set/get chip/data for an IRQ: */
807 : extern int irq_set_chip(unsigned int irq, const struct irq_chip *chip);
808 : extern int irq_set_handler_data(unsigned int irq, void *data);
809 : extern int irq_set_chip_data(unsigned int irq, void *data);
810 : extern int irq_set_irq_type(unsigned int irq, unsigned int type);
811 : extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
812 : extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
813 : struct msi_desc *entry);
814 : extern struct irq_data *irq_get_irq_data(unsigned int irq);
815 :
816 : static inline struct irq_chip *irq_get_chip(unsigned int irq)
817 : {
818 : struct irq_data *d = irq_get_irq_data(irq);
819 : return d ? d->chip : NULL;
820 : }
821 :
822 : static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
823 : {
824 : return d->chip;
825 : }
826 :
827 : static inline void *irq_get_chip_data(unsigned int irq)
828 : {
829 : struct irq_data *d = irq_get_irq_data(irq);
830 : return d ? d->chip_data : NULL;
831 : }
832 :
833 : static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
834 : {
835 : return d->chip_data;
836 : }
837 :
838 : static inline void *irq_get_handler_data(unsigned int irq)
839 : {
840 : struct irq_data *d = irq_get_irq_data(irq);
841 : return d ? d->common->handler_data : NULL;
842 : }
843 :
844 : static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
845 : {
846 : return d->common->handler_data;
847 : }
848 :
849 : static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
850 : {
851 0 : struct irq_data *d = irq_get_irq_data(irq);
852 0 : return d ? d->common->msi_desc : NULL;
853 : }
854 :
855 : static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
856 : {
857 0 : return d->common->msi_desc;
858 : }
859 :
860 : static inline u32 irq_get_trigger_type(unsigned int irq)
861 : {
862 0 : struct irq_data *d = irq_get_irq_data(irq);
863 0 : return d ? irqd_get_trigger_type(d) : 0;
864 : }
865 :
866 : static inline int irq_common_data_get_node(struct irq_common_data *d)
867 : {
868 : #ifdef CONFIG_NUMA
869 : return d->node;
870 : #else
871 : return 0;
872 : #endif
873 : }
874 :
875 : static inline int irq_data_get_node(struct irq_data *d)
876 : {
877 0 : return irq_common_data_get_node(d->common);
878 : }
879 :
880 : static inline struct cpumask *irq_get_affinity_mask(int irq)
881 : {
882 : struct irq_data *d = irq_get_irq_data(irq);
883 :
884 : return d ? d->common->affinity : NULL;
885 : }
886 :
887 : static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
888 : {
889 : return d->common->affinity;
890 : }
891 :
892 : #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
893 : static inline
894 : struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
895 : {
896 : return d->common->effective_affinity;
897 : }
898 : static inline void irq_data_update_effective_affinity(struct irq_data *d,
899 : const struct cpumask *m)
900 : {
901 : cpumask_copy(d->common->effective_affinity, m);
902 : }
903 : #else
904 : static inline void irq_data_update_effective_affinity(struct irq_data *d,
905 : const struct cpumask *m)
906 : {
907 : }
908 : static inline
909 : struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
910 : {
911 : return d->common->affinity;
912 : }
913 : #endif
914 :
915 : static inline struct cpumask *irq_get_effective_affinity_mask(unsigned int irq)
916 : {
917 : struct irq_data *d = irq_get_irq_data(irq);
918 :
919 : return d ? irq_data_get_effective_affinity_mask(d) : NULL;
920 : }
921 :
922 : unsigned int arch_dynirq_lower_bound(unsigned int from);
923 :
924 : int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
925 : struct module *owner,
926 : const struct irq_affinity_desc *affinity);
927 :
928 : int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
929 : unsigned int cnt, int node, struct module *owner,
930 : const struct irq_affinity_desc *affinity);
931 :
932 : /* use macros to avoid needing export.h for THIS_MODULE */
933 : #define irq_alloc_descs(irq, from, cnt, node) \
934 : __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
935 :
936 : #define irq_alloc_desc(node) \
937 : irq_alloc_descs(-1, 1, 1, node)
938 :
939 : #define irq_alloc_desc_at(at, node) \
940 : irq_alloc_descs(at, at, 1, node)
941 :
942 : #define irq_alloc_desc_from(from, node) \
943 : irq_alloc_descs(-1, from, 1, node)
944 :
945 : #define irq_alloc_descs_from(from, cnt, node) \
946 : irq_alloc_descs(-1, from, cnt, node)
947 :
948 : #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
949 : __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
950 :
951 : #define devm_irq_alloc_desc(dev, node) \
952 : devm_irq_alloc_descs(dev, -1, 1, 1, node)
953 :
954 : #define devm_irq_alloc_desc_at(dev, at, node) \
955 : devm_irq_alloc_descs(dev, at, at, 1, node)
956 :
957 : #define devm_irq_alloc_desc_from(dev, from, node) \
958 : devm_irq_alloc_descs(dev, -1, from, 1, node)
959 :
960 : #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
961 : devm_irq_alloc_descs(dev, -1, from, cnt, node)
962 :
963 : void irq_free_descs(unsigned int irq, unsigned int cnt);
964 : static inline void irq_free_desc(unsigned int irq)
965 : {
966 0 : irq_free_descs(irq, 1);
967 : }
968 :
969 : #ifdef CONFIG_GENERIC_IRQ_LEGACY
970 : void irq_init_desc(unsigned int irq);
971 : #endif
972 :
973 : /**
974 : * struct irq_chip_regs - register offsets for struct irq_gci
975 : * @enable: Enable register offset to reg_base
976 : * @disable: Disable register offset to reg_base
977 : * @mask: Mask register offset to reg_base
978 : * @ack: Ack register offset to reg_base
979 : * @eoi: Eoi register offset to reg_base
980 : * @type: Type configuration register offset to reg_base
981 : * @polarity: Polarity configuration register offset to reg_base
982 : */
983 : struct irq_chip_regs {
984 : unsigned long enable;
985 : unsigned long disable;
986 : unsigned long mask;
987 : unsigned long ack;
988 : unsigned long eoi;
989 : unsigned long type;
990 : unsigned long polarity;
991 : };
992 :
993 : /**
994 : * struct irq_chip_type - Generic interrupt chip instance for a flow type
995 : * @chip: The real interrupt chip which provides the callbacks
996 : * @regs: Register offsets for this chip
997 : * @handler: Flow handler associated with this chip
998 : * @type: Chip can handle these flow types
999 : * @mask_cache_priv: Cached mask register private to the chip type
1000 : * @mask_cache: Pointer to cached mask register
1001 : *
1002 : * A irq_generic_chip can have several instances of irq_chip_type when
1003 : * it requires different functions and register offsets for different
1004 : * flow types.
1005 : */
1006 : struct irq_chip_type {
1007 : struct irq_chip chip;
1008 : struct irq_chip_regs regs;
1009 : irq_flow_handler_t handler;
1010 : u32 type;
1011 : u32 mask_cache_priv;
1012 : u32 *mask_cache;
1013 : };
1014 :
1015 : /**
1016 : * struct irq_chip_generic - Generic irq chip data structure
1017 : * @lock: Lock to protect register and cache data access
1018 : * @reg_base: Register base address (virtual)
1019 : * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
1020 : * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
1021 : * @suspend: Function called from core code on suspend once per
1022 : * chip; can be useful instead of irq_chip::suspend to
1023 : * handle chip details even when no interrupts are in use
1024 : * @resume: Function called from core code on resume once per chip;
1025 : * can be useful instead of irq_chip::suspend to handle
1026 : * chip details even when no interrupts are in use
1027 : * @irq_base: Interrupt base nr for this chip
1028 : * @irq_cnt: Number of interrupts handled by this chip
1029 : * @mask_cache: Cached mask register shared between all chip types
1030 : * @type_cache: Cached type register
1031 : * @polarity_cache: Cached polarity register
1032 : * @wake_enabled: Interrupt can wakeup from suspend
1033 : * @wake_active: Interrupt is marked as an wakeup from suspend source
1034 : * @num_ct: Number of available irq_chip_type instances (usually 1)
1035 : * @private: Private data for non generic chip callbacks
1036 : * @installed: bitfield to denote installed interrupts
1037 : * @unused: bitfield to denote unused interrupts
1038 : * @domain: irq domain pointer
1039 : * @list: List head for keeping track of instances
1040 : * @chip_types: Array of interrupt irq_chip_types
1041 : *
1042 : * Note, that irq_chip_generic can have multiple irq_chip_type
1043 : * implementations which can be associated to a particular irq line of
1044 : * an irq_chip_generic instance. That allows to share and protect
1045 : * state in an irq_chip_generic instance when we need to implement
1046 : * different flow mechanisms (level/edge) for it.
1047 : */
1048 : struct irq_chip_generic {
1049 : raw_spinlock_t lock;
1050 : void __iomem *reg_base;
1051 : u32 (*reg_readl)(void __iomem *addr);
1052 : void (*reg_writel)(u32 val, void __iomem *addr);
1053 : void (*suspend)(struct irq_chip_generic *gc);
1054 : void (*resume)(struct irq_chip_generic *gc);
1055 : unsigned int irq_base;
1056 : unsigned int irq_cnt;
1057 : u32 mask_cache;
1058 : u32 type_cache;
1059 : u32 polarity_cache;
1060 : u32 wake_enabled;
1061 : u32 wake_active;
1062 : unsigned int num_ct;
1063 : void *private;
1064 : unsigned long installed;
1065 : unsigned long unused;
1066 : struct irq_domain *domain;
1067 : struct list_head list;
1068 : struct irq_chip_type chip_types[];
1069 : };
1070 :
1071 : /**
1072 : * enum irq_gc_flags - Initialization flags for generic irq chips
1073 : * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1074 : * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1075 : * irq chips which need to call irq_set_wake() on
1076 : * the parent irq. Usually GPIO implementations
1077 : * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1078 : * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1079 : * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1080 : */
1081 : enum irq_gc_flags {
1082 : IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1083 : IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
1084 : IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
1085 : IRQ_GC_NO_MASK = 1 << 3,
1086 : IRQ_GC_BE_IO = 1 << 4,
1087 : };
1088 :
1089 : /*
1090 : * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1091 : * @irqs_per_chip: Number of interrupts per chip
1092 : * @num_chips: Number of chips
1093 : * @irq_flags_to_set: IRQ* flags to set on irq setup
1094 : * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1095 : * @gc_flags: Generic chip specific setup flags
1096 : * @gc: Array of pointers to generic interrupt chips
1097 : */
1098 : struct irq_domain_chip_generic {
1099 : unsigned int irqs_per_chip;
1100 : unsigned int num_chips;
1101 : unsigned int irq_flags_to_clear;
1102 : unsigned int irq_flags_to_set;
1103 : enum irq_gc_flags gc_flags;
1104 : struct irq_chip_generic *gc[];
1105 : };
1106 :
1107 : /* Generic chip callback functions */
1108 : void irq_gc_noop(struct irq_data *d);
1109 : void irq_gc_mask_disable_reg(struct irq_data *d);
1110 : void irq_gc_mask_set_bit(struct irq_data *d);
1111 : void irq_gc_mask_clr_bit(struct irq_data *d);
1112 : void irq_gc_unmask_enable_reg(struct irq_data *d);
1113 : void irq_gc_ack_set_bit(struct irq_data *d);
1114 : void irq_gc_ack_clr_bit(struct irq_data *d);
1115 : void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1116 : void irq_gc_eoi(struct irq_data *d);
1117 : int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1118 :
1119 : /* Setup functions for irq_chip_generic */
1120 : int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1121 : irq_hw_number_t hw_irq);
1122 : struct irq_chip_generic *
1123 : irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1124 : void __iomem *reg_base, irq_flow_handler_t handler);
1125 : void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1126 : enum irq_gc_flags flags, unsigned int clr,
1127 : unsigned int set);
1128 : int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1129 : void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1130 : unsigned int clr, unsigned int set);
1131 :
1132 : struct irq_chip_generic *
1133 : devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1134 : unsigned int irq_base, void __iomem *reg_base,
1135 : irq_flow_handler_t handler);
1136 : int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1137 : u32 msk, enum irq_gc_flags flags,
1138 : unsigned int clr, unsigned int set);
1139 :
1140 : struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1141 :
1142 : int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1143 : int num_ct, const char *name,
1144 : irq_flow_handler_t handler,
1145 : unsigned int clr, unsigned int set,
1146 : enum irq_gc_flags flags);
1147 :
1148 : #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1149 : handler, clr, set, flags) \
1150 : ({ \
1151 : MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1152 : __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1153 : handler, clr, set, flags); \
1154 : })
1155 :
1156 : static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1157 : {
1158 : kfree(gc);
1159 : }
1160 :
1161 : static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1162 : u32 msk, unsigned int clr,
1163 : unsigned int set)
1164 : {
1165 : irq_remove_generic_chip(gc, msk, clr, set);
1166 : irq_free_generic_chip(gc);
1167 : }
1168 :
1169 : static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1170 : {
1171 : return container_of(d->chip, struct irq_chip_type, chip);
1172 : }
1173 :
1174 : #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1175 :
1176 : #ifdef CONFIG_SMP
1177 : static inline void irq_gc_lock(struct irq_chip_generic *gc)
1178 : {
1179 : raw_spin_lock(&gc->lock);
1180 : }
1181 :
1182 : static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1183 : {
1184 : raw_spin_unlock(&gc->lock);
1185 : }
1186 : #else
1187 : static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
1188 : static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1189 : #endif
1190 :
1191 : /*
1192 : * The irqsave variants are for usage in non interrupt code. Do not use
1193 : * them in irq_chip callbacks. Use irq_gc_lock() instead.
1194 : */
1195 : #define irq_gc_lock_irqsave(gc, flags) \
1196 : raw_spin_lock_irqsave(&(gc)->lock, flags)
1197 :
1198 : #define irq_gc_unlock_irqrestore(gc, flags) \
1199 : raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1200 :
1201 : static inline void irq_reg_writel(struct irq_chip_generic *gc,
1202 : u32 val, int reg_offset)
1203 : {
1204 : if (gc->reg_writel)
1205 : gc->reg_writel(val, gc->reg_base + reg_offset);
1206 : else
1207 : writel(val, gc->reg_base + reg_offset);
1208 : }
1209 :
1210 : static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1211 : int reg_offset)
1212 : {
1213 : if (gc->reg_readl)
1214 : return gc->reg_readl(gc->reg_base + reg_offset);
1215 : else
1216 : return readl(gc->reg_base + reg_offset);
1217 : }
1218 :
1219 : struct irq_matrix;
1220 : struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1221 : unsigned int alloc_start,
1222 : unsigned int alloc_end);
1223 : void irq_matrix_online(struct irq_matrix *m);
1224 : void irq_matrix_offline(struct irq_matrix *m);
1225 : void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1226 : int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1227 : void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1228 : int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1229 : unsigned int *mapped_cpu);
1230 : void irq_matrix_reserve(struct irq_matrix *m);
1231 : void irq_matrix_remove_reserved(struct irq_matrix *m);
1232 : int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1233 : bool reserved, unsigned int *mapped_cpu);
1234 : void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1235 : unsigned int bit, bool managed);
1236 : void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1237 : unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1238 : unsigned int irq_matrix_allocated(struct irq_matrix *m);
1239 : unsigned int irq_matrix_reserved(struct irq_matrix *m);
1240 : void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1241 :
1242 : /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1243 : #define INVALID_HWIRQ (~0UL)
1244 : irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1245 : int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1246 : int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1247 : int ipi_send_single(unsigned int virq, unsigned int cpu);
1248 : int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1249 :
1250 : #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1251 : /*
1252 : * Registers a generic IRQ handling function as the top-level IRQ handler in
1253 : * the system, which is generally the first C code called from an assembly
1254 : * architecture-specific interrupt handler.
1255 : *
1256 : * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1257 : * registered.
1258 : */
1259 : int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1260 :
1261 : /*
1262 : * Allows interrupt handlers to find the irqchip that's been registered as the
1263 : * top-level IRQ handler.
1264 : */
1265 : extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1266 : asmlinkage void generic_handle_arch_irq(struct pt_regs *regs);
1267 : #else
1268 : #ifndef set_handle_irq
1269 : #define set_handle_irq(handle_irq) \
1270 : do { \
1271 : (void)handle_irq; \
1272 : WARN_ON(1); \
1273 : } while (0)
1274 : #endif
1275 : #endif
1276 :
1277 : #endif /* _LINUX_IRQ_H */
|
