LCOV - code coverage report

Current view: top level - drivers/gpu/drm/amd/amdgpu - gfx_v10_0.c (source / functions) Hit Total Coverage Test: coverage.info Lines: 0 3033 0.0 % Date: 2022-12-09 01:23:36 Functions: 0 168 0.0 %

Function Name	Hit count
gfx10_kiq_invalidate_tlbs	0
gfx10_kiq_map_queues	0
gfx10_kiq_query_status	0
gfx10_kiq_set_resources	0
gfx10_kiq_unmap_queues	0
gfx_v10_0_apply_medium_grain_clock_gating_workaround	0
gfx_v10_0_calc_toc_total_size	0
gfx_v10_0_check_fw_write_wait	0
gfx_v10_0_check_grbm_cam_remapping	0
gfx_v10_0_compute_mqd_init	0
gfx_v10_0_compute_ring_init	0
gfx_v10_0_constants_init	0
gfx_v10_0_cp_async_gfx_ring_resume	0
gfx_v10_0_cp_compute_enable	0
gfx_v10_0_cp_compute_load_microcode	0
gfx_v10_0_cp_gfx_enable	0
gfx_v10_0_cp_gfx_load_ce_microcode	0
gfx_v10_0_cp_gfx_load_me_microcode	0
gfx_v10_0_cp_gfx_load_microcode	0
gfx_v10_0_cp_gfx_load_pfp_microcode	0
gfx_v10_0_cp_gfx_resume	0
gfx_v10_0_cp_gfx_set_doorbell.isra.9	0
gfx_v10_0_cp_gfx_start	0
gfx_v10_0_cp_gfx_switch_pipe	0
gfx_v10_0_cp_resume	0
gfx_v10_0_disable_gpa_mode	0
gfx_v10_0_early_init	0
gfx_v10_0_emit_mem_sync	0
gfx_v10_0_enable_gui_idle_interrupt	0
gfx_v10_0_eop_irq	0
gfx_v10_0_free_microcode	0
gfx_v10_0_get_clockgating_state	0
gfx_v10_0_get_csb_buffer	0
gfx_v10_0_get_csb_size	0
gfx_v10_0_get_cu_active_bitmap_per_sh	0
gfx_v10_0_get_cu_info	0
gfx_v10_0_get_gpu_clock_counter	0
gfx_v10_0_get_rb_active_bitmap	0
gfx_v10_0_get_tcc_info	0
gfx_v10_0_get_wgp_active_bitmap_per_sh	0
gfx_v10_0_gfx_init_queue	0
gfx_v10_0_gfx_mqd_init	0
gfx_v10_0_gfx_mqd_set_priority.isra.8	0
gfx_v10_0_gfx_ring_init	0
gfx_v10_0_gpu_early_init	0
gfx_v10_0_handle_priv_fault.isra.11	0
gfx_v10_0_hw_fini	0
gfx_v10_0_hw_init	0
gfx_v10_0_init_compute_vmid	0
gfx_v10_0_init_csb	0
gfx_v10_0_init_gds_vmid	0
gfx_v10_0_init_golden_registers	0
gfx_v10_0_init_microcode	0
gfx_v10_0_init_pa_sc_tile_steering_override	0
gfx_v10_0_init_rlc_ext_microcode	0
gfx_v10_0_init_rlcg_reg_access_ctrl	0
gfx_v10_0_init_spm_golden_registers	0
gfx_v10_0_init_tap_delays_microcode	0
gfx_v10_0_is_idle	0
gfx_v10_0_is_rlc_enabled	0
gfx_v10_0_is_rlcg_access_range	0
gfx_v10_0_kcq_init_queue	0
gfx_v10_0_kcq_resume	0
gfx_v10_0_kiq_disable_kgq	0
gfx_v10_0_kiq_enable_kgq	0
gfx_v10_0_kiq_init_queue	0
gfx_v10_0_kiq_init_register	0
gfx_v10_0_kiq_irq	0
gfx_v10_0_kiq_resume	0
gfx_v10_0_kiq_set_interrupt_state	0
gfx_v10_0_kiq_setting	0
gfx_v10_0_late_init	0
gfx_v10_0_me_init	0
gfx_v10_0_mec_fini	0
gfx_v10_0_mec_init	0
gfx_v10_0_parse_rlc_toc	0
gfx_v10_0_priv_inst_irq	0
gfx_v10_0_priv_reg_irq	0
gfx_v10_0_read_wave_data	0
gfx_v10_0_read_wave_sgprs	0
gfx_v10_0_read_wave_vgprs	0
gfx_v10_0_resume	0
gfx_v10_0_ring_emit_ce_meta	0
gfx_v10_0_ring_emit_cntxcntl	0
gfx_v10_0_ring_emit_de_meta	0
gfx_v10_0_ring_emit_fence	0
gfx_v10_0_ring_emit_fence_kiq	0
gfx_v10_0_ring_emit_frame_cntl	0
gfx_v10_0_ring_emit_gds_switch	0
gfx_v10_0_ring_emit_hdp_flush	0
gfx_v10_0_ring_emit_ib_compute	0
gfx_v10_0_ring_emit_ib_gfx	0
gfx_v10_0_ring_emit_init_cond_exec	0
gfx_v10_0_ring_emit_patch_cond_exec	0
gfx_v10_0_ring_emit_pipeline_sync	0
gfx_v10_0_ring_emit_reg_wait	0
gfx_v10_0_ring_emit_reg_write_reg_wait	0
gfx_v10_0_ring_emit_rreg	0
gfx_v10_0_ring_emit_sb	0
gfx_v10_0_ring_emit_vm_flush	0
gfx_v10_0_ring_emit_wreg	0
gfx_v10_0_ring_get_rptr_compute	0
gfx_v10_0_ring_get_rptr_gfx	0
gfx_v10_0_ring_get_wptr_compute	0
gfx_v10_0_ring_get_wptr_gfx	0
gfx_v10_0_ring_invalidate_tlbs	0
gfx_v10_0_ring_preempt_ib	0
gfx_v10_0_ring_set_wptr_compute	0
gfx_v10_0_ring_set_wptr_gfx	0
gfx_v10_0_ring_soft_recovery	0
gfx_v10_0_ring_test_ib	0
gfx_v10_0_ring_test_ring	0
gfx_v10_0_rlc_backdoor_autoload_buffer_fini	0
gfx_v10_0_rlc_backdoor_autoload_buffer_init	0
gfx_v10_0_rlc_backdoor_autoload_config_ce_cache	0
gfx_v10_0_rlc_backdoor_autoload_config_me_cache	0
gfx_v10_0_rlc_backdoor_autoload_config_mec_cache	0
gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache	0
gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode	0
gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode	0
gfx_v10_0_rlc_backdoor_autoload_copy_ucode.isra.10	0
gfx_v10_0_rlc_backdoor_autoload_enable	0
gfx_v10_0_rlc_enable_srm	0
gfx_v10_0_rlc_fini	0
gfx_v10_0_rlc_init	0
gfx_v10_0_rlc_load_microcode	0
gfx_v10_0_rlc_reset	0
gfx_v10_0_rlc_resume	0
gfx_v10_0_rlc_smu_handshake_cntl	0
gfx_v10_0_rlc_start	0
gfx_v10_0_rlc_stop	0
gfx_v10_0_select_me_pipe_q	0
gfx_v10_0_select_se_sh	0
gfx_v10_0_set_clockgating_state	0
gfx_v10_0_set_compute_eop_interrupt_state	0
gfx_v10_0_set_eop_interrupt_state	0
gfx_v10_0_set_gfx_eop_interrupt_state	0
gfx_v10_0_set_powergating_state	0
gfx_v10_0_set_priv_inst_fault_state	0
gfx_v10_0_set_priv_reg_fault_state	0
gfx_v10_0_set_safe_mode	0
gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh	0
gfx_v10_0_setup_grbm_cam_remapping	0
gfx_v10_0_setup_rb	0
gfx_v10_0_soft_reset	0
gfx_v10_0_suspend	0
gfx_v10_0_sw_fini	0
gfx_v10_0_sw_init	0
gfx_v10_0_tcp_harvest	0
gfx_v10_0_unset_safe_mode	0
gfx_v10_0_update_3d_clock_gating	0
gfx_v10_0_update_coarse_grain_clock_gating	0
gfx_v10_0_update_fine_grain_clock_gating	0
gfx_v10_0_update_gfx_clock_gating	0
gfx_v10_0_update_medium_grain_clock_gating	0
gfx_v10_0_update_perfmon_mgcg	0
gfx_v10_0_update_spm_vmid	0
gfx_v10_0_wait_for_idle	0
gfx_v10_0_wait_for_rlc_autoload_complete	0
gfx_v10_0_wait_reg_mem	0
gfx_v10_0_write_data_to_reg	0
gfx_v10_3_get_disabled_sa	0
gfx_v10_3_program_pbb_mode	0
gfx_v10_3_set_power_brake_sequence	0
gfx_v10_cntl_pg	0
gfx_v10_cntl_power_gating	0
wave_read_ind	0
wave_read_regs	0

Generated by: LCOV version 1.14