Line data Source code
1 : /*
2 : * Copyright 2019 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <linux/delay.h>
25 : #include <linux/kernel.h>
26 : #include <linux/firmware.h>
27 : #include <linux/module.h>
28 : #include <linux/pci.h>
29 : #include "amdgpu.h"
30 : #include "amdgpu_gfx.h"
31 : #include "amdgpu_psp.h"
32 : #include "nv.h"
33 : #include "nvd.h"
34 :
35 : #include "gc/gc_10_1_0_offset.h"
36 : #include "gc/gc_10_1_0_sh_mask.h"
37 : #include "smuio/smuio_11_0_0_offset.h"
38 : #include "smuio/smuio_11_0_0_sh_mask.h"
39 : #include "navi10_enum.h"
40 : #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41 :
42 : #include "soc15.h"
43 : #include "soc15d.h"
44 : #include "soc15_common.h"
45 : #include "clearstate_gfx10.h"
46 : #include "v10_structs.h"
47 : #include "gfx_v10_0.h"
48 : #include "nbio_v2_3.h"
49 :
50 : /*
51 : * Navi10 has two graphic rings to share each graphic pipe.
52 : * 1. Primary ring
53 : * 2. Async ring
54 : */
55 : #define GFX10_NUM_GFX_RINGS_NV1X 1
56 : #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2
57 : #define GFX10_MEC_HPD_SIZE 2048
58 :
59 : #define F32_CE_PROGRAM_RAM_SIZE 65536
60 : #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
61 :
62 : #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
63 : #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
64 : #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 : #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 : #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 : #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68 :
69 : #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
70 : #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
71 :
72 : #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
73 : #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1
74 : #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
75 : #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1
76 :
77 : #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78 : #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
79 : #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
80 : #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1
81 : #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
82 : #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
83 : #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec
84 : #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0
85 : #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1
86 : #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
87 : #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2
88 : #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
89 : #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3
90 : #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
91 : #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4
92 : #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0
93 : #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5
94 : #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0
95 : #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6
96 : #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
97 : #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a
98 : #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L
99 : #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL
100 : #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
101 : #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL
102 : #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
103 : #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
104 :
105 : #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
106 : #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
107 : #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
108 : #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
109 :
110 : #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d
111 : #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1
112 : #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e
113 : #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1
114 :
115 : #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
116 : #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
117 : #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
118 : #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
119 : #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
120 : #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
121 : #define mmVGT_TF_RING_SIZE_Vangogh 0x224e
122 : #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
123 : #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
124 : #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
125 : #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
126 : #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
127 : #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
128 : #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
129 : #define mmSPI_CONFIG_CNTL_Vangogh 0x2440
130 : #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
131 : #define mmGCR_GENERAL_CNTL_Vangogh 0x1580
132 : #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
133 : #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
134 :
135 : #define mmCP_HYP_PFP_UCODE_ADDR 0x5814
136 : #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
137 : #define mmCP_HYP_PFP_UCODE_DATA 0x5815
138 : #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
139 : #define mmCP_HYP_CE_UCODE_ADDR 0x5818
140 : #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
141 : #define mmCP_HYP_CE_UCODE_DATA 0x5819
142 : #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1
143 : #define mmCP_HYP_ME_UCODE_ADDR 0x5816
144 : #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
145 : #define mmCP_HYP_ME_UCODE_DATA 0x5817
146 : #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
147 :
148 : #define mmCPG_PSP_DEBUG 0x5c10
149 : #define mmCPG_PSP_DEBUG_BASE_IDX 1
150 : #define mmCPC_PSP_DEBUG 0x5c11
151 : #define mmCPC_PSP_DEBUG_BASE_IDX 1
152 : #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
153 : #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
154 :
155 : //CC_GC_SA_UNIT_DISABLE
156 : #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9
157 : #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0
158 : #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
159 : #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
160 : //GC_USER_SA_UNIT_DISABLE
161 : #define mmGC_USER_SA_UNIT_DISABLE 0x0fea
162 : #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0
163 : #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
164 : #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
165 : //PA_SC_ENHANCE_3
166 : #define mmPA_SC_ENHANCE_3 0x1085
167 : #define mmPA_SC_ENHANCE_3_BASE_IDX 0
168 : #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
169 : #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
170 :
171 : #define mmCGTT_SPI_CS_CLK_CTRL 0x507c
172 : #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
173 :
174 : #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3
175 : #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
176 : #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
177 : #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
178 :
179 : #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
180 : #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
181 :
182 : #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
183 : #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
184 :
185 : MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
186 : MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
187 : MODULE_FIRMWARE("amdgpu/navi10_me.bin");
188 : MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
189 : MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
190 : MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
191 :
192 : MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
193 : MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
194 : MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
195 : MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
196 : MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
197 : MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
198 : MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
199 : MODULE_FIRMWARE("amdgpu/navi14_me.bin");
200 : MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
201 : MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
202 : MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
203 :
204 : MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
205 : MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
206 : MODULE_FIRMWARE("amdgpu/navi12_me.bin");
207 : MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
208 : MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
209 : MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
210 :
211 : MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
212 : MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
213 : MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
214 : MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
215 : MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
216 : MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
217 :
218 : MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
219 : MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
220 : MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
221 : MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
222 : MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
223 : MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
224 :
225 : MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
226 : MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
227 : MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
228 : MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
229 : MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
230 : MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
231 :
232 : MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
233 : MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
234 : MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
235 : MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
236 : MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
237 : MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
238 :
239 : MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
240 : MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
241 : MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
242 : MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
243 : MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
244 : MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
245 :
246 : MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
247 : MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
248 : MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
249 : MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
250 : MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
251 : MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
252 :
253 : MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
254 : MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
255 : MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
256 : MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
257 : MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
258 : MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
259 :
260 : MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
261 : MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
262 : MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
263 : MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
264 : MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
265 : MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
266 :
267 : MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
268 : MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
269 : MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
270 : MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
271 : MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
272 : MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
273 :
274 : static const struct soc15_reg_golden golden_settings_gc_10_1[] =
275 : {
276 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
277 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
278 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
279 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
280 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
281 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
282 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
283 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
284 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
285 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
286 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
287 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
288 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
289 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
290 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
291 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
292 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
293 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
294 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
295 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
296 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
297 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
298 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
299 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
300 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
301 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
302 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
303 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
304 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
305 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
306 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
307 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
308 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
309 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
310 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
311 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
312 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
313 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
314 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
315 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
316 : };
317 :
318 : static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
319 : {
320 : /* Pending on emulation bring up */
321 : };
322 :
323 : static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
324 : {
325 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
326 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
327 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
328 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
329 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
330 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
331 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
332 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
333 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
334 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
335 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
336 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
337 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
338 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
339 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
340 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
341 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
342 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
343 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
344 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
345 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
346 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
347 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
348 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
349 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
350 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
351 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
352 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
353 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
354 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
355 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
356 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
357 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
358 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
359 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
360 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
361 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
362 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
363 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
364 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
365 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
366 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
367 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
368 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
369 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
370 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
371 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
372 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
373 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
374 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
375 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
376 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
377 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
378 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
379 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
380 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
381 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
382 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
383 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
384 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
385 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
386 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
387 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
388 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
389 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
390 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
391 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
392 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
393 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
394 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
395 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
396 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
397 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
398 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
399 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
400 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
401 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
402 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
403 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
404 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
405 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
406 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
407 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
408 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
409 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
410 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
411 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
412 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
413 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
414 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
415 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
416 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
417 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
418 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
419 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
420 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
421 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
422 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
423 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
424 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
425 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
426 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
427 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
428 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
429 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
430 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
431 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
432 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
433 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
434 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
435 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
436 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
437 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
438 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
439 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
440 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
441 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
442 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
443 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
444 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
445 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
446 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
447 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
448 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
449 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
450 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
451 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
452 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
453 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
454 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
455 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
456 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
457 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
458 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
459 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
460 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
461 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
462 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
463 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
464 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
465 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
466 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
467 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
468 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
469 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
470 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
471 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
472 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
473 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
474 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
475 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
476 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
477 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
478 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
479 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
480 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
481 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
482 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
483 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
484 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
485 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
486 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
487 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
488 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
489 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
490 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
491 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
492 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
493 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
494 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
495 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
496 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
497 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
498 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
499 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
500 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
501 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
502 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
503 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
504 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
505 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
506 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
507 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
508 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
509 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
510 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
511 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
512 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
513 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
514 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
515 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
516 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
517 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
518 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
519 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
520 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
521 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
522 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
523 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
524 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
525 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
526 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
527 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
528 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
529 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
530 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
531 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
532 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
533 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
534 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
535 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
536 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
537 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
538 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
539 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
540 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
541 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
542 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
543 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
544 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
545 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
546 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
547 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
548 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
549 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
550 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
551 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
552 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
553 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
554 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
555 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
556 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
557 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
558 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
559 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
560 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
561 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
562 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
563 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
564 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
565 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
566 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
567 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
568 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
569 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
570 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
571 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
572 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
573 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
574 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
575 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
576 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
577 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
578 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
579 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
580 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
581 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
582 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
583 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
584 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
585 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
586 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
587 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
588 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
589 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
590 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
591 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
592 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
593 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
594 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
595 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
596 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
597 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
598 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
599 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
600 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
601 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
602 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
603 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
604 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
605 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
606 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
607 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
608 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
609 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
610 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
611 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
612 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
613 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
614 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
615 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
616 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
617 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
618 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
619 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
620 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
621 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
622 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
623 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
624 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
625 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
626 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
627 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
628 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
629 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
630 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
631 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
632 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
633 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
634 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
635 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
636 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
637 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
638 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
639 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
640 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
641 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
642 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
643 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
644 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
645 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
646 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
647 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
648 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
649 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
650 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
651 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
652 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
653 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
654 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
655 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
656 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
657 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
658 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
659 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
660 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
661 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
662 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
663 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
664 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
665 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
666 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
667 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
668 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
669 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
670 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
671 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
672 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
673 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
674 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
675 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
676 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
677 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
678 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
679 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
680 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
681 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
682 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
683 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
684 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
685 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
686 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
687 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
688 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
689 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
690 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
691 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
692 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
693 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
694 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
695 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
696 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
697 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
698 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
699 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
700 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
701 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
702 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
703 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
704 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
705 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
706 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
707 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
708 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
709 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
710 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
711 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
712 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
713 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
714 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
715 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
716 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
717 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
718 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
719 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
720 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
721 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
722 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
723 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
724 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
725 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
726 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
727 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
728 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
729 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
730 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
731 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
732 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
733 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
734 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
735 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
736 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
737 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
738 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
739 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
740 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
741 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
742 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
743 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
744 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
745 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
746 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
747 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
748 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
749 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
750 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
751 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
752 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
753 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
754 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
755 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
756 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
757 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
758 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
759 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
760 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
761 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
762 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
763 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
764 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
765 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
766 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
767 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
768 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
769 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
770 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
771 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
772 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
773 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
774 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
775 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
776 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
777 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
778 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
779 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
780 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
781 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
782 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
783 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
784 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
785 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
786 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
787 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
788 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
789 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
790 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
791 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
792 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
793 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
794 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
795 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
796 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
797 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
798 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
799 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
800 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
801 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
802 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
803 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
804 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
805 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
806 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
807 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
808 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
809 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
810 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
811 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
812 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
813 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
814 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
815 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
816 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
817 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
818 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
819 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
820 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
821 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
822 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
823 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
824 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
825 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
826 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
827 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
828 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
829 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
830 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
831 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
832 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
833 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
834 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
835 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
836 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
837 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
838 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
839 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
840 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
841 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
842 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
843 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
844 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
845 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
846 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
847 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
848 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
849 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
850 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
851 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
852 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
853 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
854 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
855 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
856 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
857 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
858 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
859 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
860 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
861 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
862 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
863 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
864 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
865 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
866 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
867 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
868 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
869 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
870 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
871 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
872 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
873 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
874 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
875 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
876 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
877 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
878 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
879 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
880 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
881 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
882 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
883 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
884 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
885 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
886 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
887 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
888 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
889 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
890 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
891 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
892 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
893 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
894 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
895 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
896 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
897 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
898 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
899 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
900 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
901 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
902 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
903 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
904 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
905 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
906 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
907 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
908 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
909 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
910 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
911 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
912 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
913 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
914 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
915 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
916 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
917 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
918 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
919 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
920 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
921 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
922 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
923 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
924 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
925 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
926 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
927 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
928 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
929 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
930 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
931 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
932 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
933 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
934 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
935 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
936 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
937 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
938 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
939 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
940 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
941 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
942 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
943 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
944 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
945 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
946 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
947 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
948 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
949 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
950 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
951 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
952 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
953 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
954 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
955 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
956 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
957 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
958 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
959 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
960 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
961 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
962 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
963 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
964 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
965 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
966 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
967 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
968 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
969 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
970 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
971 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
972 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
973 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
974 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
975 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
976 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
977 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
978 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
979 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
980 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
981 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
982 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
983 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
984 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
985 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
986 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
987 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
988 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
989 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
990 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
991 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
992 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
993 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
994 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
995 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
996 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
997 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
998 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
999 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1000 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1002 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1004 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1006 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1008 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1012 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1016 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1018 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1020 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1022 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1024 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1026 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1028 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1030 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1032 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1034 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1036 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1038 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1040 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1042 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1044 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1046 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1048 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1050 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1052 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1054 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1056 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1058 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1060 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1062 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1064 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1066 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1068 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1070 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1072 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1074 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1076 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1078 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1080 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1082 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1084 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1086 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1088 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1090 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1092 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1094 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1096 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1098 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1100 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1102 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1104 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1108 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1112 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1114 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1116 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1118 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1120 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1122 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1124 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1126 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1128 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1130 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1132 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1134 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1136 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1138 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1140 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1142 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1144 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1148 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1152 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1156 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1160 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1162 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1164 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1166 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1168 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1170 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1172 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1174 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1176 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1178 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1180 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1182 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1184 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1186 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1188 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1190 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1192 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1194 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1196 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1198 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1200 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1204 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1208 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1210 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1212 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1214 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1216 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1218 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1220 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1222 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1224 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1226 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1228 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1230 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1232 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1234 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1236 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1238 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1240 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1244 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1248 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1252 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1256 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1258 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1260 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1262 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1264 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1266 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1268 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1270 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1272 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1274 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1276 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1278 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1280 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1282 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1284 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1286 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1288 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1292 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1296 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1300 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1304 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1306 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1308 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1310 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1312 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1314 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1316 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1318 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1320 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1322 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1324 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1326 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1328 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1330 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1331 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1332 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1334 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1336 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1338 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1340 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1342 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1344 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1346 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1348 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1350 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1352 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1354 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1355 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1356 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1358 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1360 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1362 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1364 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1366 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1368 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1369 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1370 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1372 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1374 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1376 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1377 : };
1378 :
1379 : static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1380 : {
1381 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1382 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1384 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1385 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1386 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1387 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1388 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1390 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1391 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1392 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1393 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1394 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1395 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1396 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1397 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1398 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1399 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1400 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1401 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1402 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1404 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1405 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1406 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1407 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1408 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1409 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1410 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1411 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1412 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1413 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1414 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1415 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1416 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1417 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1418 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1419 : };
1420 :
1421 : static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1422 : {
1423 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 : };
1466 :
1467 : static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1468 : {
1469 : /* Pending on emulation bring up */
1470 : };
1471 :
1472 : static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1473 : {
1474 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1475 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1477 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1479 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1481 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1483 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1485 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1487 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1489 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1493 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1497 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1501 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1503 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1505 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1507 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1509 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1511 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1513 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1515 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1517 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1523 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1525 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1527 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1529 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1531 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1533 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1537 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1539 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1541 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1543 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1545 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1547 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1549 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1551 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1553 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1555 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1557 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1559 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1561 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1563 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1565 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1567 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1569 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1571 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1573 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1575 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1577 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1579 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1581 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1585 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1587 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1589 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1591 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1593 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1595 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1597 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1599 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1601 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1603 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1605 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1607 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1609 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1611 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1613 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1615 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1617 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1619 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1621 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1623 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1625 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1627 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1629 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1631 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1633 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1635 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1637 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1639 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1641 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1643 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1645 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1647 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1649 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1651 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1653 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1655 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1657 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1659 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1661 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1663 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1665 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1667 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1669 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1671 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1673 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1675 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1677 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1679 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1681 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1683 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1687 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1691 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1693 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1695 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1697 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1701 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1703 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1705 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1707 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1709 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1711 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1713 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1715 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1717 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1719 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1721 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1723 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1725 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1727 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1729 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1731 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1733 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1735 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1737 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1739 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1741 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1743 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1745 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1747 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1749 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1751 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1753 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1755 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1757 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1759 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1761 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1763 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1765 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1767 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1769 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1771 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1773 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1775 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1777 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1779 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1781 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1783 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1785 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1787 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1789 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1791 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1793 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1797 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1799 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1801 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1805 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1807 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1809 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1813 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1815 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1817 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1821 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1823 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1825 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1827 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1829 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1831 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1833 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1835 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1837 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1839 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1841 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1843 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1845 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1847 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1849 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1851 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1853 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1855 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1857 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1861 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1863 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1865 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1867 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1869 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1871 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1873 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1875 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1877 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1881 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1885 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1889 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1893 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1895 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1897 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1899 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1901 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1903 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1905 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1907 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1909 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1911 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1913 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1915 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1917 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1921 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1925 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1927 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1929 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1931 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1933 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1937 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1939 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1941 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1943 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1945 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1947 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1949 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1951 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1953 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1955 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1957 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1959 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1961 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1963 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1965 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1967 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1969 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1971 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1973 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1975 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1977 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1979 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1981 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1983 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1985 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1987 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1989 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1991 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1993 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1995 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1997 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1999 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2001 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2003 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2005 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2007 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2009 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2011 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2013 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2017 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2019 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2021 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2025 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2027 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2029 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2031 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2033 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2037 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2041 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2045 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2047 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2049 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2051 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2053 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2055 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2057 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2059 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2061 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2063 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2065 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2067 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2069 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2071 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2073 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2075 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2077 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2079 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2081 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2083 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2085 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2086 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2087 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2089 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2090 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2091 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2093 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2094 : };
2095 :
2096 : static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2097 : {
2098 : /* Pending on emulation bring up */
2099 : };
2100 :
2101 : static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2102 : {
2103 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2104 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2106 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2108 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2113 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2114 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2115 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2116 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2118 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2120 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2122 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2126 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2130 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2134 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2142 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2144 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2146 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2150 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2152 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2154 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2161 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2162 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2163 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2164 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2166 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2168 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2170 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2172 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2174 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2178 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2180 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2182 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2186 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2188 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2190 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2192 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2194 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2196 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2198 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2200 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2202 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2204 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2206 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2208 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2210 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2212 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2214 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2216 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2218 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2222 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2226 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2228 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2230 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2232 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2234 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2238 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2240 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2242 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2246 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2248 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2250 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2252 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2254 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2256 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2258 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2260 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2262 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2264 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2266 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2268 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2270 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2272 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2274 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2276 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2278 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2280 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2282 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2284 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2286 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2290 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2294 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2296 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2298 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2300 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2302 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2304 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2306 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2308 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2310 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2312 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2314 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2316 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2318 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2320 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2322 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2324 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2326 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2328 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2334 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2336 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2341 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2342 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2349 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2350 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2352 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2357 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2358 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2365 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2366 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2368 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2373 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2374 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2376 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2381 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2382 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2384 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2389 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2390 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2397 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2398 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2400 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2405 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2406 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2413 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2414 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2421 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2422 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2429 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2430 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2438 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2440 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2446 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2454 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2462 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2470 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2472 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2478 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2480 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2486 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2488 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2494 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2496 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2502 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2504 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2510 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2512 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2518 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2520 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2526 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2528 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2534 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2542 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2544 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2550 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2558 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2560 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2566 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2568 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2574 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2576 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2582 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2584 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2590 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2592 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2598 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2600 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2606 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2608 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2614 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2616 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2622 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2624 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2630 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2638 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2646 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2654 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2662 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2664 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2670 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2678 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2680 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2686 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2688 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2694 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2696 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2702 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2710 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2712 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2718 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2720 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2726 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2728 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2734 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2736 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2742 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2744 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2750 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2758 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2760 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2766 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2768 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2774 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2776 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2782 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2790 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2792 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2798 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2806 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2814 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2822 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2830 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2838 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2840 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2846 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2848 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2854 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2862 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2870 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2872 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2878 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2886 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2888 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2894 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2902 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2904 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2910 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2912 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2918 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2920 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2926 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2934 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2936 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2942 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2950 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2952 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2958 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2960 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2966 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2968 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2974 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2976 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2982 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2984 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2990 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2992 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2998 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3000 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3006 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3008 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3014 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3016 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3022 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3030 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3038 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3046 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3054 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3056 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3062 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3070 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3072 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3078 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3086 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3088 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3094 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3096 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3102 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3104 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3110 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3112 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3114 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3116 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3118 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3120 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3126 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3128 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3134 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3136 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3138 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3140 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3142 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3144 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3146 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3148 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3150 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3152 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3154 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3155 : };
3156 :
3157 : static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3158 : {
3159 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3160 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3161 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3162 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3163 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3164 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3165 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3166 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3167 : SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3168 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3169 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3170 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3171 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3172 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3173 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3174 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3175 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3176 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3177 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3178 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3179 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3180 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3181 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3182 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3183 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3184 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3185 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3186 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3187 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3188 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3189 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3190 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3191 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3192 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3193 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3194 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3195 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3196 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3197 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3198 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3199 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3200 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3201 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3202 : };
3203 :
3204 : static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3205 : {
3206 : /* Pending on emulation bring up */
3207 : };
3208 :
3209 : static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3210 : {
3211 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3212 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3213 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3214 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3215 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3216 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3217 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3218 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3219 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3220 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3221 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3222 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3223 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3224 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3225 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3226 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3227 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3228 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3229 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3230 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3231 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3232 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3233 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3234 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3235 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3236 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3237 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3238 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3239 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3240 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3241 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3242 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3243 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3244 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3245 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3246 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3247 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3248 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3249 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3250 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3251 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3252 :
3253 : /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3254 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3255 : };
3256 :
3257 : static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3258 : {
3259 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3260 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3261 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3262 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3263 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3264 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3265 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3266 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3267 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3268 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3269 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3270 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3271 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3272 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3273 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3274 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3275 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3276 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3277 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3278 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3279 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3280 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3281 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3282 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3283 :
3284 : /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3285 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3286 : };
3287 :
3288 : static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3289 : {
3290 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3291 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3292 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3293 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3294 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3295 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3296 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3297 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3298 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3299 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3300 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3301 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3302 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3303 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3304 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3305 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3306 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3307 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3308 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3309 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3310 : };
3311 :
3312 : static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3313 : {
3314 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3315 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3316 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3317 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3318 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3319 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3320 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3321 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3322 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3323 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3324 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3325 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3326 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3327 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3328 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3329 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3330 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3331 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3332 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3333 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3334 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3335 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3336 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3337 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3338 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3339 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3340 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3341 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3342 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3343 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3344 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3345 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3346 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3347 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3348 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3349 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)
3350 : };
3351 :
3352 : static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3353 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3354 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3355 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3356 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3357 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3358 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3359 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3360 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3361 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3362 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3363 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3364 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3365 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3366 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3367 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3368 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3369 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3370 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3371 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3372 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3373 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3374 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3375 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3376 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3377 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3378 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3379 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3380 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3381 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3382 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3383 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3384 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3385 : };
3386 :
3387 : static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3388 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3389 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3390 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3391 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3392 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3393 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3394 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3395 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3396 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3397 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3398 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3399 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3400 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3401 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3402 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3403 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3404 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3405 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3406 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3407 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3408 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3409 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3410 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3411 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3412 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3413 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3414 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3415 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3416 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3417 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3418 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3419 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3420 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3421 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3422 : };
3423 :
3424 : static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3425 : {
3426 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3427 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3428 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3429 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3430 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3432 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3433 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3434 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3435 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3436 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3437 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3439 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3440 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3441 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3444 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3445 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3446 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3447 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3448 : };
3449 :
3450 : static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3451 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3452 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3453 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3454 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3455 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3456 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3457 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3458 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3459 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3460 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3461 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3462 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3463 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3464 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3465 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3466 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3467 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3468 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3469 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3470 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3471 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3472 : SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3473 : };
3474 :
3475 : #define DEFAULT_SH_MEM_CONFIG \
3476 : ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3477 : (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3478 : (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3479 : (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3480 :
3481 : /* TODO: pending on golden setting value of gb address config */
3482 : #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3483 :
3484 : static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3485 : static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3486 : static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3487 : static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3488 : static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3489 : static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3490 : struct amdgpu_cu_info *cu_info);
3491 : static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3492 : static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3493 : u32 sh_num, u32 instance);
3494 : static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3495 :
3496 : static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3497 : static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3498 : static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3499 : static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3500 : static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3501 : static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3502 : static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3503 : static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3504 : static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3505 : static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3506 : static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3507 : uint16_t pasid, uint32_t flush_type,
3508 : bool all_hub, uint8_t dst_sel);
3509 :
3510 0 : static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3511 : {
3512 0 : amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3513 0 : amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3514 : PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3515 0 : amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3516 0 : amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3517 0 : amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3518 0 : amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3519 0 : amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3520 0 : amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3521 0 : }
3522 :
3523 0 : static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3524 : struct amdgpu_ring *ring)
3525 : {
3526 0 : uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3527 0 : uint64_t wptr_addr = ring->wptr_gpu_addr;
3528 0 : uint32_t eng_sel = 0;
3529 :
3530 0 : switch (ring->funcs->type) {
3531 : case AMDGPU_RING_TYPE_COMPUTE:
3532 : eng_sel = 0;
3533 : break;
3534 : case AMDGPU_RING_TYPE_GFX:
3535 0 : eng_sel = 4;
3536 0 : break;
3537 : case AMDGPU_RING_TYPE_MES:
3538 0 : eng_sel = 5;
3539 0 : break;
3540 : default:
3541 0 : WARN_ON(1);
3542 : }
3543 :
3544 0 : amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3545 : /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3546 0 : amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3547 : PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3548 0 : PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3549 0 : PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3550 0 : PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3551 0 : PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3552 0 : PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3553 0 : PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3554 0 : PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3555 : PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3556 0 : amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3557 0 : amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3558 0 : amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3559 0 : amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3560 0 : amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3561 0 : }
3562 :
3563 0 : static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3564 : struct amdgpu_ring *ring,
3565 : enum amdgpu_unmap_queues_action action,
3566 : u64 gpu_addr, u64 seq)
3567 : {
3568 0 : struct amdgpu_device *adev = kiq_ring->adev;
3569 0 : uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3570 :
3571 0 : if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
3572 0 : amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3573 0 : return;
3574 : }
3575 :
3576 0 : amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3577 0 : amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3578 : PACKET3_UNMAP_QUEUES_ACTION(action) |
3579 0 : PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3580 0 : PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3581 : PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3582 0 : amdgpu_ring_write(kiq_ring,
3583 0 : PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3584 :
3585 0 : if (action == PREEMPT_QUEUES_NO_UNMAP) {
3586 0 : amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3587 0 : amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3588 0 : amdgpu_ring_write(kiq_ring, seq);
3589 : } else {
3590 0 : amdgpu_ring_write(kiq_ring, 0);
3591 0 : amdgpu_ring_write(kiq_ring, 0);
3592 0 : amdgpu_ring_write(kiq_ring, 0);
3593 : }
3594 : }
3595 :
3596 0 : static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3597 : struct amdgpu_ring *ring,
3598 : u64 addr,
3599 : u64 seq)
3600 : {
3601 0 : uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3602 :
3603 0 : amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3604 0 : amdgpu_ring_write(kiq_ring,
3605 : PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3606 : PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3607 : PACKET3_QUERY_STATUS_COMMAND(2));
3608 0 : amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3609 0 : PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3610 0 : PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3611 0 : amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3612 0 : amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3613 0 : amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3614 0 : amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3615 0 : }
3616 :
3617 0 : static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3618 : uint16_t pasid, uint32_t flush_type,
3619 : bool all_hub)
3620 : {
3621 0 : gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3622 0 : }
3623 :
3624 : static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3625 : .kiq_set_resources = gfx10_kiq_set_resources,
3626 : .kiq_map_queues = gfx10_kiq_map_queues,
3627 : .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3628 : .kiq_query_status = gfx10_kiq_query_status,
3629 : .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3630 : .set_resources_size = 8,
3631 : .map_queues_size = 7,
3632 : .unmap_queues_size = 6,
3633 : .query_status_size = 7,
3634 : .invalidate_tlbs_size = 2,
3635 : };
3636 :
3637 : static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3638 : {
3639 0 : adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3640 : }
3641 :
3642 0 : static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3643 : {
3644 0 : switch (adev->ip_versions[GC_HWIP][0]) {
3645 : case IP_VERSION(10, 1, 10):
3646 0 : soc15_program_register_sequence(adev,
3647 : golden_settings_gc_rlc_spm_10_0_nv10,
3648 : (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3649 0 : break;
3650 : case IP_VERSION(10, 1, 1):
3651 0 : soc15_program_register_sequence(adev,
3652 : golden_settings_gc_rlc_spm_10_1_nv14,
3653 : (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3654 0 : break;
3655 : case IP_VERSION(10, 1, 2):
3656 0 : soc15_program_register_sequence(adev,
3657 : golden_settings_gc_rlc_spm_10_1_2_nv12,
3658 : (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3659 0 : break;
3660 : default:
3661 : break;
3662 : }
3663 0 : }
3664 :
3665 0 : static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3666 : {
3667 0 : switch (adev->ip_versions[GC_HWIP][0]) {
3668 : case IP_VERSION(10, 1, 10):
3669 0 : soc15_program_register_sequence(adev,
3670 : golden_settings_gc_10_1,
3671 : (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3672 0 : soc15_program_register_sequence(adev,
3673 : golden_settings_gc_10_0_nv10,
3674 : (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3675 0 : break;
3676 : case IP_VERSION(10, 1, 1):
3677 0 : soc15_program_register_sequence(adev,
3678 : golden_settings_gc_10_1_1,
3679 : (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3680 0 : soc15_program_register_sequence(adev,
3681 : golden_settings_gc_10_1_nv14,
3682 : (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3683 0 : break;
3684 : case IP_VERSION(10, 1, 2):
3685 0 : soc15_program_register_sequence(adev,
3686 : golden_settings_gc_10_1_2,
3687 : (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3688 0 : soc15_program_register_sequence(adev,
3689 : golden_settings_gc_10_1_2_nv12,
3690 : (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3691 0 : break;
3692 : case IP_VERSION(10, 3, 0):
3693 0 : soc15_program_register_sequence(adev,
3694 : golden_settings_gc_10_3,
3695 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3696 0 : soc15_program_register_sequence(adev,
3697 : golden_settings_gc_10_3_sienna_cichlid,
3698 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3699 0 : break;
3700 : case IP_VERSION(10, 3, 2):
3701 0 : soc15_program_register_sequence(adev,
3702 : golden_settings_gc_10_3_2,
3703 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3704 0 : break;
3705 : case IP_VERSION(10, 3, 1):
3706 0 : soc15_program_register_sequence(adev,
3707 : golden_settings_gc_10_3_vangogh,
3708 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3709 0 : break;
3710 : case IP_VERSION(10, 3, 3):
3711 0 : soc15_program_register_sequence(adev,
3712 : golden_settings_gc_10_3_3,
3713 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3714 0 : break;
3715 : case IP_VERSION(10, 3, 4):
3716 0 : soc15_program_register_sequence(adev,
3717 : golden_settings_gc_10_3_4,
3718 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3719 0 : break;
3720 : case IP_VERSION(10, 3, 5):
3721 0 : soc15_program_register_sequence(adev,
3722 : golden_settings_gc_10_3_5,
3723 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3724 0 : break;
3725 : case IP_VERSION(10, 1, 3):
3726 : case IP_VERSION(10, 1, 4):
3727 0 : soc15_program_register_sequence(adev,
3728 : golden_settings_gc_10_0_cyan_skillfish,
3729 : (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3730 0 : break;
3731 : case IP_VERSION(10, 3, 6):
3732 0 : soc15_program_register_sequence(adev,
3733 : golden_settings_gc_10_3_6,
3734 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3735 0 : break;
3736 : case IP_VERSION(10, 3, 7):
3737 0 : soc15_program_register_sequence(adev,
3738 : golden_settings_gc_10_3_7,
3739 : (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3740 0 : break;
3741 : default:
3742 : break;
3743 : }
3744 0 : gfx_v10_0_init_spm_golden_registers(adev);
3745 0 : }
3746 :
3747 0 : static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3748 : bool wc, uint32_t reg, uint32_t val)
3749 : {
3750 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3751 0 : amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3752 0 : WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3753 0 : amdgpu_ring_write(ring, reg);
3754 0 : amdgpu_ring_write(ring, 0);
3755 0 : amdgpu_ring_write(ring, val);
3756 0 : }
3757 :
3758 0 : static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3759 : int mem_space, int opt, uint32_t addr0,
3760 : uint32_t addr1, uint32_t ref, uint32_t mask,
3761 : uint32_t inv)
3762 : {
3763 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3764 0 : amdgpu_ring_write(ring,
3765 : /* memory (1) or register (0) */
3766 0 : (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3767 0 : WAIT_REG_MEM_OPERATION(opt) | /* wait */
3768 0 : WAIT_REG_MEM_FUNCTION(3) | /* equal */
3769 0 : WAIT_REG_MEM_ENGINE(eng_sel)));
3770 :
3771 0 : if (mem_space)
3772 0 : BUG_ON(addr0 & 0x3); /* Dword align */
3773 0 : amdgpu_ring_write(ring, addr0);
3774 0 : amdgpu_ring_write(ring, addr1);
3775 0 : amdgpu_ring_write(ring, ref);
3776 0 : amdgpu_ring_write(ring, mask);
3777 0 : amdgpu_ring_write(ring, inv); /* poll interval */
3778 0 : }
3779 :
3780 0 : static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3781 : {
3782 0 : struct amdgpu_device *adev = ring->adev;
3783 0 : uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3784 0 : uint32_t tmp = 0;
3785 : unsigned i;
3786 : int r;
3787 :
3788 0 : WREG32(scratch, 0xCAFEDEAD);
3789 0 : r = amdgpu_ring_alloc(ring, 3);
3790 0 : if (r) {
3791 0 : DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3792 : ring->idx, r);
3793 0 : return r;
3794 : }
3795 :
3796 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3797 0 : amdgpu_ring_write(ring, scratch -
3798 : PACKET3_SET_UCONFIG_REG_START);
3799 0 : amdgpu_ring_write(ring, 0xDEADBEEF);
3800 0 : amdgpu_ring_commit(ring);
3801 :
3802 0 : for (i = 0; i < adev->usec_timeout; i++) {
3803 0 : tmp = RREG32(scratch);
3804 0 : if (tmp == 0xDEADBEEF)
3805 : break;
3806 0 : if (amdgpu_emu_mode == 1)
3807 0 : msleep(1);
3808 : else
3809 : udelay(1);
3810 : }
3811 :
3812 0 : if (i >= adev->usec_timeout)
3813 0 : r = -ETIMEDOUT;
3814 :
3815 : return r;
3816 : }
3817 :
3818 0 : static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3819 : {
3820 0 : struct amdgpu_device *adev = ring->adev;
3821 : struct amdgpu_ib ib;
3822 0 : struct dma_fence *f = NULL;
3823 : unsigned index;
3824 : uint64_t gpu_addr;
3825 : volatile uint32_t *cpu_ptr;
3826 : long r;
3827 :
3828 0 : memset(&ib, 0, sizeof(ib));
3829 :
3830 0 : if (ring->is_mes_queue) {
3831 : uint32_t padding, offset;
3832 :
3833 0 : offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3834 0 : padding = amdgpu_mes_ctx_get_offs(ring,
3835 : AMDGPU_MES_CTX_PADDING_OFFS);
3836 :
3837 0 : ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3838 0 : ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3839 :
3840 0 : gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3841 0 : cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3842 0 : *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3843 : } else {
3844 0 : r = amdgpu_device_wb_get(adev, &index);
3845 0 : if (r)
3846 : return r;
3847 :
3848 0 : gpu_addr = adev->wb.gpu_addr + (index * 4);
3849 0 : adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3850 0 : cpu_ptr = &adev->wb.wb[index];
3851 :
3852 0 : r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3853 0 : if (r) {
3854 0 : DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3855 0 : goto err1;
3856 : }
3857 : }
3858 :
3859 0 : ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3860 0 : ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3861 0 : ib.ptr[2] = lower_32_bits(gpu_addr);
3862 0 : ib.ptr[3] = upper_32_bits(gpu_addr);
3863 0 : ib.ptr[4] = 0xDEADBEEF;
3864 0 : ib.length_dw = 5;
3865 :
3866 0 : r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3867 0 : if (r)
3868 : goto err2;
3869 :
3870 0 : r = dma_fence_wait_timeout(f, false, timeout);
3871 0 : if (r == 0) {
3872 : r = -ETIMEDOUT;
3873 : goto err2;
3874 0 : } else if (r < 0) {
3875 : goto err2;
3876 : }
3877 :
3878 0 : if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3879 : r = 0;
3880 : else
3881 0 : r = -EINVAL;
3882 : err2:
3883 0 : if (!ring->is_mes_queue)
3884 0 : amdgpu_ib_free(adev, &ib, NULL);
3885 0 : dma_fence_put(f);
3886 : err1:
3887 0 : if (!ring->is_mes_queue)
3888 0 : amdgpu_device_wb_free(adev, index);
3889 0 : return r;
3890 : }
3891 :
3892 0 : static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3893 : {
3894 0 : release_firmware(adev->gfx.pfp_fw);
3895 0 : adev->gfx.pfp_fw = NULL;
3896 0 : release_firmware(adev->gfx.me_fw);
3897 0 : adev->gfx.me_fw = NULL;
3898 0 : release_firmware(adev->gfx.ce_fw);
3899 0 : adev->gfx.ce_fw = NULL;
3900 0 : release_firmware(adev->gfx.rlc_fw);
3901 0 : adev->gfx.rlc_fw = NULL;
3902 0 : release_firmware(adev->gfx.mec_fw);
3903 0 : adev->gfx.mec_fw = NULL;
3904 0 : release_firmware(adev->gfx.mec2_fw);
3905 0 : adev->gfx.mec2_fw = NULL;
3906 :
3907 0 : kfree(adev->gfx.rlc.register_list_format);
3908 0 : }
3909 :
3910 0 : static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3911 : {
3912 0 : adev->gfx.cp_fw_write_wait = false;
3913 :
3914 0 : switch (adev->ip_versions[GC_HWIP][0]) {
3915 : case IP_VERSION(10, 1, 10):
3916 : case IP_VERSION(10, 1, 2):
3917 : case IP_VERSION(10, 1, 1):
3918 : case IP_VERSION(10, 1, 3):
3919 : case IP_VERSION(10, 1, 4):
3920 0 : if ((adev->gfx.me_fw_version >= 0x00000046) &&
3921 0 : (adev->gfx.me_feature_version >= 27) &&
3922 0 : (adev->gfx.pfp_fw_version >= 0x00000068) &&
3923 0 : (adev->gfx.pfp_feature_version >= 27) &&
3924 0 : (adev->gfx.mec_fw_version >= 0x0000005b) &&
3925 0 : (adev->gfx.mec_feature_version >= 27))
3926 0 : adev->gfx.cp_fw_write_wait = true;
3927 : break;
3928 : case IP_VERSION(10, 3, 0):
3929 : case IP_VERSION(10, 3, 2):
3930 : case IP_VERSION(10, 3, 1):
3931 : case IP_VERSION(10, 3, 4):
3932 : case IP_VERSION(10, 3, 5):
3933 : case IP_VERSION(10, 3, 6):
3934 : case IP_VERSION(10, 3, 3):
3935 : case IP_VERSION(10, 3, 7):
3936 0 : adev->gfx.cp_fw_write_wait = true;
3937 0 : break;
3938 : default:
3939 : break;
3940 : }
3941 :
3942 0 : if (!adev->gfx.cp_fw_write_wait)
3943 0 : DRM_WARN_ONCE("CP firmware version too old, please update!");
3944 0 : }
3945 :
3946 :
3947 0 : static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3948 : {
3949 : const struct rlc_firmware_header_v2_1 *rlc_hdr;
3950 :
3951 0 : rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3952 0 : adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3953 0 : adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3954 0 : adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3955 0 : adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3956 0 : adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3957 0 : adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3958 0 : adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3959 0 : adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3960 0 : adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3961 0 : adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3962 0 : adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3963 0 : adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3964 0 : adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3965 0 : le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3966 0 : }
3967 :
3968 : static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3969 : {
3970 : const struct rlc_firmware_header_v2_2 *rlc_hdr;
3971 :
3972 0 : rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3973 0 : adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3974 0 : adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3975 0 : adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3976 0 : adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3977 : }
3978 :
3979 0 : static void gfx_v10_0_init_tap_delays_microcode(struct amdgpu_device *adev)
3980 : {
3981 : const struct rlc_firmware_header_v2_4 *rlc_hdr;
3982 :
3983 0 : rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;
3984 0 : adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);
3985 0 : adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);
3986 0 : adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);
3987 0 : adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);
3988 0 : adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);
3989 0 : adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);
3990 0 : adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);
3991 0 : adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);
3992 0 : adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);
3993 0 : adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);
3994 0 : }
3995 :
3996 : static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3997 : {
3998 0 : bool ret = false;
3999 :
4000 0 : switch (adev->pdev->revision) {
4001 : case 0xc2:
4002 : case 0xc3:
4003 : ret = true;
4004 : break;
4005 : default:
4006 0 : ret = false;
4007 : break;
4008 : }
4009 :
4010 : return ret ;
4011 : }
4012 :
4013 : static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4014 : {
4015 0 : switch (adev->ip_versions[GC_HWIP][0]) {
4016 : case IP_VERSION(10, 1, 10):
4017 0 : if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4018 0 : adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4019 : break;
4020 : default:
4021 : break;
4022 : }
4023 : }
4024 :
4025 0 : static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4026 : {
4027 : const char *chip_name;
4028 : char fw_name[40];
4029 0 : char *wks = "";
4030 : int err;
4031 0 : struct amdgpu_firmware_info *info = NULL;
4032 0 : const struct common_firmware_header *header = NULL;
4033 : const struct gfx_firmware_header_v1_0 *cp_hdr;
4034 : const struct rlc_firmware_header_v2_0 *rlc_hdr;
4035 0 : unsigned int *tmp = NULL;
4036 0 : unsigned int i = 0;
4037 : uint16_t version_major;
4038 : uint16_t version_minor;
4039 :
4040 0 : DRM_DEBUG("\n");
4041 :
4042 0 : switch (adev->ip_versions[GC_HWIP][0]) {
4043 : case IP_VERSION(10, 1, 10):
4044 : chip_name = "navi10";
4045 : break;
4046 : case IP_VERSION(10, 1, 1):
4047 0 : chip_name = "navi14";
4048 0 : if (!(adev->pdev->device == 0x7340 &&
4049 0 : adev->pdev->revision != 0x00))
4050 0 : wks = "_wks";
4051 : break;
4052 : case IP_VERSION(10, 1, 2):
4053 0 : chip_name = "navi12";
4054 0 : break;
4055 : case IP_VERSION(10, 3, 0):
4056 0 : chip_name = "sienna_cichlid";
4057 0 : break;
4058 : case IP_VERSION(10, 3, 2):
4059 0 : chip_name = "navy_flounder";
4060 0 : break;
4061 : case IP_VERSION(10, 3, 1):
4062 0 : chip_name = "vangogh";
4063 0 : break;
4064 : case IP_VERSION(10, 3, 4):
4065 0 : chip_name = "dimgrey_cavefish";
4066 0 : break;
4067 : case IP_VERSION(10, 3, 5):
4068 0 : chip_name = "beige_goby";
4069 0 : break;
4070 : case IP_VERSION(10, 3, 3):
4071 0 : chip_name = "yellow_carp";
4072 0 : break;
4073 : case IP_VERSION(10, 3, 6):
4074 0 : chip_name = "gc_10_3_6";
4075 0 : break;
4076 : case IP_VERSION(10, 1, 3):
4077 : case IP_VERSION(10, 1, 4):
4078 0 : chip_name = "cyan_skillfish2";
4079 0 : break;
4080 : case IP_VERSION(10, 3, 7):
4081 0 : chip_name = "gc_10_3_7";
4082 0 : break;
4083 : default:
4084 0 : BUG();
4085 : }
4086 :
4087 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4088 0 : err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4089 0 : if (err)
4090 : goto out;
4091 0 : err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4092 0 : if (err)
4093 : goto out;
4094 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4095 0 : adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4096 0 : adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4097 :
4098 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4099 0 : err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4100 0 : if (err)
4101 : goto out;
4102 0 : err = amdgpu_ucode_validate(adev->gfx.me_fw);
4103 0 : if (err)
4104 : goto out;
4105 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4106 0 : adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4107 0 : adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4108 :
4109 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4110 0 : err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4111 0 : if (err)
4112 : goto out;
4113 0 : err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4114 0 : if (err)
4115 : goto out;
4116 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4117 0 : adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4118 0 : adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4119 :
4120 0 : if (!amdgpu_sriov_vf(adev)) {
4121 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4122 0 : err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4123 0 : if (err)
4124 : goto out;
4125 0 : err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4126 0 : rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4127 0 : version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4128 0 : version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4129 :
4130 0 : adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4131 0 : adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4132 0 : adev->gfx.rlc.save_and_restore_offset =
4133 0 : le32_to_cpu(rlc_hdr->save_and_restore_offset);
4134 0 : adev->gfx.rlc.clear_state_descriptor_offset =
4135 0 : le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4136 0 : adev->gfx.rlc.avail_scratch_ram_locations =
4137 0 : le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4138 0 : adev->gfx.rlc.reg_restore_list_size =
4139 0 : le32_to_cpu(rlc_hdr->reg_restore_list_size);
4140 0 : adev->gfx.rlc.reg_list_format_start =
4141 0 : le32_to_cpu(rlc_hdr->reg_list_format_start);
4142 0 : adev->gfx.rlc.reg_list_format_separate_start =
4143 0 : le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4144 0 : adev->gfx.rlc.starting_offsets_start =
4145 0 : le32_to_cpu(rlc_hdr->starting_offsets_start);
4146 0 : adev->gfx.rlc.reg_list_format_size_bytes =
4147 0 : le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4148 0 : adev->gfx.rlc.reg_list_size_bytes =
4149 0 : le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4150 0 : adev->gfx.rlc.register_list_format =
4151 0 : kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4152 : adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4153 0 : if (!adev->gfx.rlc.register_list_format) {
4154 : err = -ENOMEM;
4155 : goto out;
4156 : }
4157 :
4158 0 : tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4159 0 : le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4160 0 : for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4161 0 : adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4162 :
4163 0 : adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4164 :
4165 0 : tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4166 0 : le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4167 0 : for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4168 0 : adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4169 :
4170 0 : if (version_major == 2) {
4171 0 : if (version_minor >= 1)
4172 0 : gfx_v10_0_init_rlc_ext_microcode(adev);
4173 0 : if (version_minor >= 2)
4174 : gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4175 0 : if (version_minor == 4) {
4176 0 : gfx_v10_0_init_tap_delays_microcode(adev);
4177 : }
4178 : }
4179 : }
4180 :
4181 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4182 0 : err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4183 0 : if (err)
4184 : goto out;
4185 0 : err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4186 0 : if (err)
4187 : goto out;
4188 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4189 0 : adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4190 0 : adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4191 :
4192 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4193 0 : err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4194 0 : if (!err) {
4195 0 : err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4196 0 : if (err)
4197 : goto out;
4198 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4199 0 : adev->gfx.mec2_fw->data;
4200 0 : adev->gfx.mec2_fw_version =
4201 0 : le32_to_cpu(cp_hdr->header.ucode_version);
4202 0 : adev->gfx.mec2_feature_version =
4203 0 : le32_to_cpu(cp_hdr->ucode_feature_version);
4204 : } else {
4205 0 : err = 0;
4206 0 : adev->gfx.mec2_fw = NULL;
4207 : }
4208 :
4209 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4210 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4211 0 : info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4212 0 : info->fw = adev->gfx.pfp_fw;
4213 0 : header = (const struct common_firmware_header *)info->fw->data;
4214 0 : adev->firmware.fw_size +=
4215 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4216 :
4217 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4218 0 : info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4219 0 : info->fw = adev->gfx.me_fw;
4220 0 : header = (const struct common_firmware_header *)info->fw->data;
4221 0 : adev->firmware.fw_size +=
4222 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4223 :
4224 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4225 0 : info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4226 0 : info->fw = adev->gfx.ce_fw;
4227 0 : header = (const struct common_firmware_header *)info->fw->data;
4228 0 : adev->firmware.fw_size +=
4229 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4230 :
4231 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4232 0 : info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4233 0 : info->fw = adev->gfx.rlc_fw;
4234 0 : if (info->fw) {
4235 0 : header = (const struct common_firmware_header *)info->fw->data;
4236 0 : adev->firmware.fw_size +=
4237 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4238 : }
4239 0 : if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4240 0 : adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4241 0 : adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4242 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4243 0 : info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4244 0 : info->fw = adev->gfx.rlc_fw;
4245 0 : adev->firmware.fw_size +=
4246 0 : ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4247 :
4248 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4249 0 : info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4250 0 : info->fw = adev->gfx.rlc_fw;
4251 0 : adev->firmware.fw_size +=
4252 0 : ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4253 :
4254 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4255 0 : info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4256 0 : info->fw = adev->gfx.rlc_fw;
4257 0 : adev->firmware.fw_size +=
4258 0 : ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4259 :
4260 0 : if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4261 0 : adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4262 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4263 0 : info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4264 0 : info->fw = adev->gfx.rlc_fw;
4265 0 : adev->firmware.fw_size +=
4266 0 : ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4267 :
4268 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4269 0 : info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4270 0 : info->fw = adev->gfx.rlc_fw;
4271 0 : adev->firmware.fw_size +=
4272 0 : ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4273 : }
4274 :
4275 : }
4276 :
4277 0 : if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {
4278 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
4279 0 : info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
4280 0 : info->fw = adev->gfx.rlc_fw;
4281 0 : adev->firmware.fw_size +=
4282 0 : ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
4283 : }
4284 :
4285 0 : if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {
4286 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
4287 0 : info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
4288 0 : info->fw = adev->gfx.rlc_fw;
4289 0 : adev->firmware.fw_size +=
4290 0 : ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
4291 : }
4292 :
4293 0 : if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {
4294 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
4295 0 : info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
4296 0 : info->fw = adev->gfx.rlc_fw;
4297 0 : adev->firmware.fw_size +=
4298 0 : ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
4299 : }
4300 :
4301 0 : if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {
4302 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
4303 0 : info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
4304 0 : info->fw = adev->gfx.rlc_fw;
4305 0 : adev->firmware.fw_size +=
4306 0 : ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
4307 : }
4308 :
4309 0 : if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {
4310 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
4311 0 : info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
4312 0 : info->fw = adev->gfx.rlc_fw;
4313 0 : adev->firmware.fw_size +=
4314 0 : ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
4315 : }
4316 :
4317 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4318 0 : info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4319 0 : info->fw = adev->gfx.mec_fw;
4320 0 : header = (const struct common_firmware_header *)info->fw->data;
4321 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4322 0 : adev->firmware.fw_size +=
4323 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4324 : le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4325 :
4326 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4327 0 : info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4328 0 : info->fw = adev->gfx.mec_fw;
4329 0 : adev->firmware.fw_size +=
4330 0 : ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4331 :
4332 0 : if (adev->gfx.mec2_fw) {
4333 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4334 0 : info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4335 0 : info->fw = adev->gfx.mec2_fw;
4336 0 : header = (const struct common_firmware_header *)info->fw->data;
4337 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4338 0 : adev->firmware.fw_size +=
4339 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4340 : le32_to_cpu(cp_hdr->jt_size) * 4,
4341 : PAGE_SIZE);
4342 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4343 0 : info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4344 0 : info->fw = adev->gfx.mec2_fw;
4345 0 : adev->firmware.fw_size +=
4346 0 : ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4347 : PAGE_SIZE);
4348 : }
4349 : }
4350 :
4351 0 : gfx_v10_0_check_fw_write_wait(adev);
4352 : out:
4353 0 : if (err) {
4354 0 : dev_err(adev->dev,
4355 : "gfx10: Failed to load firmware \"%s\"\n",
4356 : fw_name);
4357 0 : release_firmware(adev->gfx.pfp_fw);
4358 0 : adev->gfx.pfp_fw = NULL;
4359 0 : release_firmware(adev->gfx.me_fw);
4360 0 : adev->gfx.me_fw = NULL;
4361 0 : release_firmware(adev->gfx.ce_fw);
4362 0 : adev->gfx.ce_fw = NULL;
4363 0 : release_firmware(adev->gfx.rlc_fw);
4364 0 : adev->gfx.rlc_fw = NULL;
4365 0 : release_firmware(adev->gfx.mec_fw);
4366 0 : adev->gfx.mec_fw = NULL;
4367 0 : release_firmware(adev->gfx.mec2_fw);
4368 0 : adev->gfx.mec2_fw = NULL;
4369 : }
4370 :
4371 0 : gfx_v10_0_check_gfxoff_flag(adev);
4372 :
4373 0 : return err;
4374 : }
4375 :
4376 0 : static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4377 : {
4378 0 : u32 count = 0;
4379 0 : const struct cs_section_def *sect = NULL;
4380 0 : const struct cs_extent_def *ext = NULL;
4381 :
4382 : /* begin clear state */
4383 0 : count += 2;
4384 : /* context control state */
4385 0 : count += 3;
4386 :
4387 0 : for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4388 0 : for (ext = sect->section; ext->extent != NULL; ++ext) {
4389 0 : if (sect->id == SECT_CONTEXT)
4390 0 : count += 2 + ext->reg_count;
4391 : else
4392 : return 0;
4393 : }
4394 : }
4395 :
4396 : /* set PA_SC_TILE_STEERING_OVERRIDE */
4397 0 : count += 3;
4398 : /* end clear state */
4399 0 : count += 2;
4400 : /* clear state */
4401 0 : count += 2;
4402 :
4403 0 : return count;
4404 : }
4405 :
4406 0 : static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4407 : volatile u32 *buffer)
4408 : {
4409 0 : u32 count = 0, i;
4410 0 : const struct cs_section_def *sect = NULL;
4411 0 : const struct cs_extent_def *ext = NULL;
4412 : int ctx_reg_offset;
4413 :
4414 0 : if (adev->gfx.rlc.cs_data == NULL)
4415 : return;
4416 0 : if (buffer == NULL)
4417 : return;
4418 :
4419 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4420 0 : buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4421 :
4422 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4423 0 : buffer[count++] = cpu_to_le32(0x80000000);
4424 0 : buffer[count++] = cpu_to_le32(0x80000000);
4425 :
4426 0 : for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4427 0 : for (ext = sect->section; ext->extent != NULL; ++ext) {
4428 0 : if (sect->id == SECT_CONTEXT) {
4429 0 : buffer[count++] =
4430 0 : cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4431 0 : buffer[count++] = cpu_to_le32(ext->reg_index -
4432 : PACKET3_SET_CONTEXT_REG_START);
4433 0 : for (i = 0; i < ext->reg_count; i++)
4434 0 : buffer[count++] = cpu_to_le32(ext->extent[i]);
4435 : } else {
4436 : return;
4437 : }
4438 : }
4439 : }
4440 :
4441 0 : ctx_reg_offset =
4442 0 : SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4443 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4444 0 : buffer[count++] = cpu_to_le32(ctx_reg_offset);
4445 0 : buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4446 :
4447 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4448 0 : buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4449 :
4450 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4451 0 : buffer[count++] = cpu_to_le32(0);
4452 : }
4453 :
4454 0 : static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4455 : {
4456 : /* clear state block */
4457 0 : amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4458 0 : &adev->gfx.rlc.clear_state_gpu_addr,
4459 0 : (void **)&adev->gfx.rlc.cs_ptr);
4460 :
4461 : /* jump table block */
4462 0 : amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4463 0 : &adev->gfx.rlc.cp_table_gpu_addr,
4464 0 : (void **)&adev->gfx.rlc.cp_table_ptr);
4465 0 : }
4466 :
4467 0 : static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4468 : {
4469 : struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4470 :
4471 0 : reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4472 0 : reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4473 0 : reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4474 0 : reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4475 0 : reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4476 0 : reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4477 0 : reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4478 0 : switch (adev->ip_versions[GC_HWIP][0]) {
4479 : case IP_VERSION(10, 3, 0):
4480 0 : reg_access_ctrl->spare_int =
4481 0 : SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4482 0 : break;
4483 : default:
4484 0 : reg_access_ctrl->spare_int =
4485 0 : SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4486 0 : break;
4487 : }
4488 0 : adev->gfx.rlc.rlcg_reg_access_supported = true;
4489 0 : }
4490 :
4491 0 : static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4492 : {
4493 : const struct cs_section_def *cs_data;
4494 : int r;
4495 :
4496 0 : adev->gfx.rlc.cs_data = gfx10_cs_data;
4497 :
4498 0 : cs_data = adev->gfx.rlc.cs_data;
4499 :
4500 : if (cs_data) {
4501 : /* init clear state block */
4502 0 : r = amdgpu_gfx_rlc_init_csb(adev);
4503 0 : if (r)
4504 : return r;
4505 : }
4506 :
4507 : /* init spm vmid with 0xf */
4508 0 : if (adev->gfx.rlc.funcs->update_spm_vmid)
4509 0 : adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4510 :
4511 :
4512 : return 0;
4513 : }
4514 :
4515 0 : static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4516 : {
4517 0 : amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4518 0 : amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4519 0 : }
4520 :
4521 0 : static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4522 : {
4523 : int r;
4524 :
4525 0 : bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4526 :
4527 0 : amdgpu_gfx_graphics_queue_acquire(adev);
4528 :
4529 0 : r = gfx_v10_0_init_microcode(adev);
4530 0 : if (r)
4531 0 : DRM_ERROR("Failed to load gfx firmware!\n");
4532 :
4533 0 : return r;
4534 : }
4535 :
4536 0 : static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4537 : {
4538 : int r;
4539 : u32 *hpd;
4540 0 : const __le32 *fw_data = NULL;
4541 : unsigned fw_size;
4542 0 : u32 *fw = NULL;
4543 : size_t mec_hpd_size;
4544 :
4545 0 : const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4546 :
4547 0 : bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4548 :
4549 : /* take ownership of the relevant compute queues */
4550 0 : amdgpu_gfx_compute_queue_acquire(adev);
4551 0 : mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4552 :
4553 0 : if (mec_hpd_size) {
4554 0 : r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4555 : AMDGPU_GEM_DOMAIN_GTT,
4556 : &adev->gfx.mec.hpd_eop_obj,
4557 : &adev->gfx.mec.hpd_eop_gpu_addr,
4558 : (void **)&hpd);
4559 0 : if (r) {
4560 0 : dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4561 0 : gfx_v10_0_mec_fini(adev);
4562 0 : return r;
4563 : }
4564 :
4565 0 : memset(hpd, 0, mec_hpd_size);
4566 :
4567 0 : amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4568 0 : amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4569 : }
4570 :
4571 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4572 0 : mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4573 :
4574 0 : fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4575 0 : le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4576 0 : fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4577 :
4578 0 : r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4579 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4580 : &adev->gfx.mec.mec_fw_obj,
4581 : &adev->gfx.mec.mec_fw_gpu_addr,
4582 : (void **)&fw);
4583 0 : if (r) {
4584 0 : dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4585 0 : gfx_v10_0_mec_fini(adev);
4586 0 : return r;
4587 : }
4588 :
4589 0 : memcpy(fw, fw_data, fw_size);
4590 :
4591 0 : amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4592 0 : amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4593 : }
4594 :
4595 : return 0;
4596 : }
4597 :
4598 0 : static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4599 : {
4600 0 : WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4601 : (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4602 : (address << SQ_IND_INDEX__INDEX__SHIFT));
4603 0 : return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4604 : }
4605 :
4606 0 : static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4607 : uint32_t thread, uint32_t regno,
4608 : uint32_t num, uint32_t *out)
4609 : {
4610 0 : WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4611 : (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4612 : (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4613 : (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4614 : (SQ_IND_INDEX__AUTO_INCR_MASK));
4615 0 : while (num--)
4616 0 : *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4617 0 : }
4618 :
4619 0 : static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4620 : {
4621 : /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4622 : * field when performing a select_se_sh so it should be
4623 : * zero here */
4624 0 : WARN_ON(simd != 0);
4625 :
4626 : /* type 2 wave data */
4627 0 : dst[(*no_fields)++] = 2;
4628 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4629 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4630 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4631 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4632 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4633 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4634 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4635 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4636 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4637 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4638 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4639 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4640 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4641 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4642 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4643 0 : dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4644 0 : }
4645 :
4646 0 : static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4647 : uint32_t wave, uint32_t start,
4648 : uint32_t size, uint32_t *dst)
4649 : {
4650 0 : WARN_ON(simd != 0);
4651 :
4652 0 : wave_read_regs(
4653 : adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4654 : dst);
4655 0 : }
4656 :
4657 0 : static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4658 : uint32_t wave, uint32_t thread,
4659 : uint32_t start, uint32_t size,
4660 : uint32_t *dst)
4661 : {
4662 0 : wave_read_regs(
4663 : adev, wave, thread,
4664 : start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4665 0 : }
4666 :
4667 0 : static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4668 : u32 me, u32 pipe, u32 q, u32 vm)
4669 : {
4670 0 : nv_grbm_select(adev, me, pipe, q, vm);
4671 0 : }
4672 :
4673 0 : static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4674 : bool enable)
4675 : {
4676 : uint32_t data, def;
4677 :
4678 0 : data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4679 :
4680 0 : if (enable)
4681 0 : data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4682 : else
4683 0 : data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4684 :
4685 0 : if (data != def)
4686 0 : WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4687 0 : }
4688 :
4689 : static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4690 : .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4691 : .select_se_sh = &gfx_v10_0_select_se_sh,
4692 : .read_wave_data = &gfx_v10_0_read_wave_data,
4693 : .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4694 : .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4695 : .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4696 : .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4697 : .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4698 : };
4699 :
4700 0 : static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4701 : {
4702 : u32 gb_addr_config;
4703 :
4704 0 : adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4705 :
4706 0 : switch (adev->ip_versions[GC_HWIP][0]) {
4707 : case IP_VERSION(10, 1, 10):
4708 : case IP_VERSION(10, 1, 1):
4709 : case IP_VERSION(10, 1, 2):
4710 0 : adev->gfx.config.max_hw_contexts = 8;
4711 0 : adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4712 0 : adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4713 0 : adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4714 0 : adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4715 0 : gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4716 : break;
4717 : case IP_VERSION(10, 3, 0):
4718 : case IP_VERSION(10, 3, 2):
4719 : case IP_VERSION(10, 3, 1):
4720 : case IP_VERSION(10, 3, 4):
4721 : case IP_VERSION(10, 3, 5):
4722 : case IP_VERSION(10, 3, 6):
4723 : case IP_VERSION(10, 3, 3):
4724 : case IP_VERSION(10, 3, 7):
4725 0 : adev->gfx.config.max_hw_contexts = 8;
4726 0 : adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4727 0 : adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4728 0 : adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4729 0 : adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4730 0 : gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4731 0 : adev->gfx.config.gb_addr_config_fields.num_pkrs =
4732 0 : 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4733 0 : break;
4734 : case IP_VERSION(10, 1, 3):
4735 : case IP_VERSION(10, 1, 4):
4736 0 : adev->gfx.config.max_hw_contexts = 8;
4737 0 : adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4738 0 : adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4739 0 : adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4740 0 : adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4741 0 : gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4742 0 : break;
4743 : default:
4744 0 : BUG();
4745 : break;
4746 : }
4747 :
4748 0 : adev->gfx.config.gb_addr_config = gb_addr_config;
4749 :
4750 0 : adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4751 0 : REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4752 : GB_ADDR_CONFIG, NUM_PIPES);
4753 :
4754 0 : adev->gfx.config.max_tile_pipes =
4755 0 : adev->gfx.config.gb_addr_config_fields.num_pipes;
4756 :
4757 0 : adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4758 0 : REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4759 : GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4760 0 : adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4761 0 : REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4762 : GB_ADDR_CONFIG, NUM_RB_PER_SE);
4763 0 : adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4764 0 : REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4765 : GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4766 0 : adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4767 0 : REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4768 : GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4769 0 : }
4770 :
4771 0 : static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4772 : int me, int pipe, int queue)
4773 : {
4774 : struct amdgpu_ring *ring;
4775 : unsigned int irq_type;
4776 : unsigned int hw_prio;
4777 :
4778 0 : ring = &adev->gfx.gfx_ring[ring_id];
4779 :
4780 0 : ring->me = me;
4781 0 : ring->pipe = pipe;
4782 0 : ring->queue = queue;
4783 :
4784 0 : ring->ring_obj = NULL;
4785 0 : ring->use_doorbell = true;
4786 :
4787 0 : if (!ring_id)
4788 0 : ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4789 : else
4790 0 : ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4791 0 : sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4792 :
4793 0 : irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4794 0 : hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4795 0 : AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4796 0 : return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4797 : hw_prio, NULL);
4798 : }
4799 :
4800 0 : static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4801 : int mec, int pipe, int queue)
4802 : {
4803 : unsigned irq_type;
4804 : struct amdgpu_ring *ring;
4805 : unsigned int hw_prio;
4806 :
4807 0 : ring = &adev->gfx.compute_ring[ring_id];
4808 :
4809 : /* mec0 is me1 */
4810 0 : ring->me = mec + 1;
4811 0 : ring->pipe = pipe;
4812 0 : ring->queue = queue;
4813 :
4814 0 : ring->ring_obj = NULL;
4815 0 : ring->use_doorbell = true;
4816 0 : ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4817 0 : ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4818 0 : + (ring_id * GFX10_MEC_HPD_SIZE);
4819 0 : sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4820 :
4821 0 : irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4822 0 : + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4823 0 : + ring->pipe;
4824 0 : hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4825 0 : AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4826 : /* type-2 packets are deprecated on MEC, use type-3 instead */
4827 0 : return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4828 : hw_prio, NULL);
4829 : }
4830 :
4831 0 : static int gfx_v10_0_sw_init(void *handle)
4832 : {
4833 0 : int i, j, k, r, ring_id = 0;
4834 : struct amdgpu_kiq *kiq;
4835 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4836 :
4837 0 : switch (adev->ip_versions[GC_HWIP][0]) {
4838 : case IP_VERSION(10, 1, 10):
4839 : case IP_VERSION(10, 1, 1):
4840 : case IP_VERSION(10, 1, 2):
4841 : case IP_VERSION(10, 1, 3):
4842 : case IP_VERSION(10, 1, 4):
4843 0 : adev->gfx.me.num_me = 1;
4844 0 : adev->gfx.me.num_pipe_per_me = 1;
4845 0 : adev->gfx.me.num_queue_per_pipe = 1;
4846 0 : adev->gfx.mec.num_mec = 2;
4847 0 : adev->gfx.mec.num_pipe_per_mec = 4;
4848 0 : adev->gfx.mec.num_queue_per_pipe = 8;
4849 0 : break;
4850 : case IP_VERSION(10, 3, 0):
4851 : case IP_VERSION(10, 3, 2):
4852 : case IP_VERSION(10, 3, 1):
4853 : case IP_VERSION(10, 3, 4):
4854 : case IP_VERSION(10, 3, 5):
4855 : case IP_VERSION(10, 3, 6):
4856 : case IP_VERSION(10, 3, 3):
4857 : case IP_VERSION(10, 3, 7):
4858 0 : adev->gfx.me.num_me = 1;
4859 0 : adev->gfx.me.num_pipe_per_me = 1;
4860 0 : adev->gfx.me.num_queue_per_pipe = 1;
4861 0 : adev->gfx.mec.num_mec = 2;
4862 0 : adev->gfx.mec.num_pipe_per_mec = 4;
4863 0 : adev->gfx.mec.num_queue_per_pipe = 4;
4864 0 : break;
4865 : default:
4866 0 : adev->gfx.me.num_me = 1;
4867 0 : adev->gfx.me.num_pipe_per_me = 1;
4868 0 : adev->gfx.me.num_queue_per_pipe = 1;
4869 0 : adev->gfx.mec.num_mec = 1;
4870 0 : adev->gfx.mec.num_pipe_per_mec = 4;
4871 0 : adev->gfx.mec.num_queue_per_pipe = 8;
4872 0 : break;
4873 : }
4874 :
4875 : /* KIQ event */
4876 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4877 : GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4878 : &adev->gfx.kiq.irq);
4879 0 : if (r)
4880 : return r;
4881 :
4882 : /* EOP Event */
4883 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4884 : GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4885 : &adev->gfx.eop_irq);
4886 0 : if (r)
4887 : return r;
4888 :
4889 : /* Privileged reg */
4890 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4891 : &adev->gfx.priv_reg_irq);
4892 0 : if (r)
4893 : return r;
4894 :
4895 : /* Privileged inst */
4896 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4897 : &adev->gfx.priv_inst_irq);
4898 0 : if (r)
4899 : return r;
4900 :
4901 0 : adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4902 :
4903 0 : r = gfx_v10_0_me_init(adev);
4904 0 : if (r)
4905 : return r;
4906 :
4907 0 : if (adev->gfx.rlc.funcs) {
4908 0 : if (adev->gfx.rlc.funcs->init) {
4909 0 : r = adev->gfx.rlc.funcs->init(adev);
4910 0 : if (r) {
4911 0 : dev_err(adev->dev, "Failed to init rlc BOs!\n");
4912 0 : return r;
4913 : }
4914 : }
4915 : }
4916 :
4917 0 : r = gfx_v10_0_mec_init(adev);
4918 0 : if (r) {
4919 0 : DRM_ERROR("Failed to init MEC BOs!\n");
4920 0 : return r;
4921 : }
4922 :
4923 : /* set up the gfx ring */
4924 0 : for (i = 0; i < adev->gfx.me.num_me; i++) {
4925 0 : for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4926 0 : for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4927 0 : if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4928 0 : continue;
4929 :
4930 0 : r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4931 : i, k, j);
4932 0 : if (r)
4933 : return r;
4934 0 : ring_id++;
4935 : }
4936 : }
4937 : }
4938 :
4939 : ring_id = 0;
4940 : /* set up the compute queues - allocate horizontally across pipes */
4941 0 : for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4942 0 : for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4943 0 : for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4944 0 : if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4945 : j))
4946 0 : continue;
4947 :
4948 0 : r = gfx_v10_0_compute_ring_init(adev, ring_id,
4949 : i, k, j);
4950 0 : if (r)
4951 : return r;
4952 :
4953 0 : ring_id++;
4954 : }
4955 : }
4956 : }
4957 :
4958 0 : if (!adev->enable_mes_kiq) {
4959 0 : r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4960 0 : if (r) {
4961 0 : DRM_ERROR("Failed to init KIQ BOs!\n");
4962 0 : return r;
4963 : }
4964 :
4965 0 : kiq = &adev->gfx.kiq;
4966 0 : r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4967 0 : if (r)
4968 : return r;
4969 : }
4970 :
4971 0 : r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4972 0 : if (r)
4973 : return r;
4974 :
4975 : /* allocate visible FB for rlc auto-loading fw */
4976 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4977 0 : r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4978 0 : if (r)
4979 : return r;
4980 : }
4981 :
4982 0 : adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4983 :
4984 0 : gfx_v10_0_gpu_early_init(adev);
4985 :
4986 0 : return 0;
4987 : }
4988 :
4989 : static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4990 : {
4991 0 : amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4992 0 : &adev->gfx.pfp.pfp_fw_gpu_addr,
4993 0 : (void **)&adev->gfx.pfp.pfp_fw_ptr);
4994 : }
4995 :
4996 : static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4997 : {
4998 0 : amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4999 0 : &adev->gfx.ce.ce_fw_gpu_addr,
5000 0 : (void **)&adev->gfx.ce.ce_fw_ptr);
5001 : }
5002 :
5003 : static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
5004 : {
5005 0 : amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
5006 0 : &adev->gfx.me.me_fw_gpu_addr,
5007 0 : (void **)&adev->gfx.me.me_fw_ptr);
5008 : }
5009 :
5010 0 : static int gfx_v10_0_sw_fini(void *handle)
5011 : {
5012 : int i;
5013 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5014 :
5015 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5016 0 : amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
5017 0 : for (i = 0; i < adev->gfx.num_compute_rings; i++)
5018 0 : amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
5019 :
5020 0 : amdgpu_gfx_mqd_sw_fini(adev);
5021 :
5022 0 : if (!adev->enable_mes_kiq) {
5023 0 : amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
5024 0 : amdgpu_gfx_kiq_fini(adev);
5025 : }
5026 :
5027 0 : gfx_v10_0_pfp_fini(adev);
5028 0 : gfx_v10_0_ce_fini(adev);
5029 0 : gfx_v10_0_me_fini(adev);
5030 0 : gfx_v10_0_rlc_fini(adev);
5031 0 : gfx_v10_0_mec_fini(adev);
5032 :
5033 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
5034 0 : gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
5035 :
5036 0 : gfx_v10_0_free_microcode(adev);
5037 :
5038 0 : return 0;
5039 : }
5040 :
5041 0 : static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5042 : u32 sh_num, u32 instance)
5043 : {
5044 : u32 data;
5045 :
5046 0 : if (instance == 0xffffffff)
5047 : data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
5048 : INSTANCE_BROADCAST_WRITES, 1);
5049 : else
5050 0 : data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
5051 : instance);
5052 :
5053 0 : if (se_num == 0xffffffff)
5054 0 : data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
5055 : 1);
5056 : else
5057 0 : data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5058 :
5059 0 : if (sh_num == 0xffffffff)
5060 0 : data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5061 : 1);
5062 : else
5063 0 : data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5064 :
5065 0 : WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5066 0 : }
5067 :
5068 0 : static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5069 : {
5070 : u32 data, mask;
5071 :
5072 0 : data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5073 0 : data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5074 :
5075 0 : data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5076 0 : data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5077 :
5078 0 : mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5079 0 : adev->gfx.config.max_sh_per_se);
5080 :
5081 0 : return (~data) & mask;
5082 : }
5083 :
5084 0 : static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5085 : {
5086 : int i, j;
5087 : u32 data;
5088 0 : u32 active_rbs = 0;
5089 : u32 bitmap;
5090 0 : u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5091 0 : adev->gfx.config.max_sh_per_se;
5092 :
5093 0 : mutex_lock(&adev->grbm_idx_mutex);
5094 0 : for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5095 0 : for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5096 0 : bitmap = i * adev->gfx.config.max_sh_per_se + j;
5097 0 : if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
5098 0 : (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
5099 0 : (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
5100 0 : ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5101 0 : continue;
5102 0 : gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5103 0 : data = gfx_v10_0_get_rb_active_bitmap(adev);
5104 0 : active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5105 : rb_bitmap_width_per_sh);
5106 : }
5107 : }
5108 0 : gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5109 0 : mutex_unlock(&adev->grbm_idx_mutex);
5110 :
5111 0 : adev->gfx.config.backend_enable_mask = active_rbs;
5112 0 : adev->gfx.config.num_rbs = hweight32(active_rbs);
5113 0 : }
5114 :
5115 0 : static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5116 : {
5117 : uint32_t num_sc;
5118 : uint32_t enabled_rb_per_sh;
5119 : uint32_t active_rb_bitmap;
5120 : uint32_t num_rb_per_sc;
5121 : uint32_t num_packer_per_sc;
5122 : uint32_t pa_sc_tile_steering_override;
5123 :
5124 : /* for ASICs that integrates GFX v10.3
5125 : * pa_sc_tile_steering_override should be set to 0 */
5126 0 : if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
5127 : return 0;
5128 :
5129 : /* init num_sc */
5130 0 : num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5131 0 : adev->gfx.config.num_sc_per_sh;
5132 : /* init num_rb_per_sc */
5133 0 : active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5134 0 : enabled_rb_per_sh = hweight32(active_rb_bitmap);
5135 0 : num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5136 : /* init num_packer_per_sc */
5137 0 : num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5138 :
5139 0 : pa_sc_tile_steering_override = 0;
5140 0 : pa_sc_tile_steering_override |=
5141 0 : (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5142 : PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5143 0 : pa_sc_tile_steering_override |=
5144 0 : (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5145 : PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5146 0 : pa_sc_tile_steering_override |=
5147 0 : (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5148 : PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5149 :
5150 0 : return pa_sc_tile_steering_override;
5151 : }
5152 :
5153 : #define DEFAULT_SH_MEM_BASES (0x6000)
5154 :
5155 0 : static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5156 : {
5157 : int i;
5158 : uint32_t sh_mem_bases;
5159 :
5160 : /*
5161 : * Configure apertures:
5162 : * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
5163 : * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
5164 : * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
5165 : */
5166 0 : sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5167 :
5168 0 : mutex_lock(&adev->srbm_mutex);
5169 0 : for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5170 0 : nv_grbm_select(adev, 0, 0, 0, i);
5171 : /* CP and shaders */
5172 0 : WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5173 0 : WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5174 : }
5175 0 : nv_grbm_select(adev, 0, 0, 0, 0);
5176 0 : mutex_unlock(&adev->srbm_mutex);
5177 :
5178 : /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5179 : access. These should be enabled by FW for target VMIDs. */
5180 0 : for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5181 0 : WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5182 0 : WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5183 0 : WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5184 0 : WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5185 : }
5186 0 : }
5187 :
5188 0 : static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5189 : {
5190 : int vmid;
5191 :
5192 : /*
5193 : * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5194 : * access. Compute VMIDs should be enabled by FW for target VMIDs,
5195 : * the driver can enable them for graphics. VMID0 should maintain
5196 : * access so that HWS firmware can save/restore entries.
5197 : */
5198 0 : for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5199 0 : WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5200 0 : WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5201 0 : WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5202 0 : WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5203 : }
5204 0 : }
5205 :
5206 :
5207 0 : static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5208 : {
5209 : int i, j, k;
5210 0 : int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5211 0 : u32 tmp, wgp_active_bitmap = 0;
5212 0 : u32 gcrd_targets_disable_tcp = 0;
5213 0 : u32 utcl_invreq_disable = 0;
5214 : /*
5215 : * GCRD_TARGETS_DISABLE field contains
5216 : * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5217 : * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5218 : */
5219 0 : u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5220 0 : 2 * max_wgp_per_sh + /* TCP */
5221 0 : max_wgp_per_sh + /* SQC */
5222 : 4); /* GL1C */
5223 : /*
5224 : * UTCL1_UTCL0_INVREQ_DISABLE field contains
5225 : * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5226 : * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5227 : */
5228 0 : u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5229 : 2 * max_wgp_per_sh + /* TCP */
5230 0 : 2 * max_wgp_per_sh + /* SQC */
5231 0 : 4 + /* RMI */
5232 : 1); /* SQG */
5233 :
5234 0 : mutex_lock(&adev->grbm_idx_mutex);
5235 0 : for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5236 0 : for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5237 0 : gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5238 0 : wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5239 : /*
5240 : * Set corresponding TCP bits for the inactive WGPs in
5241 : * GCRD_SA_TARGETS_DISABLE
5242 : */
5243 0 : gcrd_targets_disable_tcp = 0;
5244 : /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5245 0 : utcl_invreq_disable = 0;
5246 :
5247 0 : for (k = 0; k < max_wgp_per_sh; k++) {
5248 0 : if (!(wgp_active_bitmap & (1 << k))) {
5249 0 : gcrd_targets_disable_tcp |= 3 << (2 * k);
5250 0 : gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5251 0 : utcl_invreq_disable |= (3 << (2 * k)) |
5252 0 : (3 << (2 * (max_wgp_per_sh + k)));
5253 : }
5254 : }
5255 :
5256 0 : tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5257 : /* only override TCP & SQC bits */
5258 0 : tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5259 0 : tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5260 0 : WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5261 :
5262 0 : tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5263 : /* only override TCP & SQC bits */
5264 0 : tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5265 0 : tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5266 0 : WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5267 : }
5268 : }
5269 :
5270 0 : gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5271 0 : mutex_unlock(&adev->grbm_idx_mutex);
5272 0 : }
5273 :
5274 0 : static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5275 : {
5276 : /* TCCs are global (not instanced). */
5277 : uint32_t tcc_disable;
5278 :
5279 0 : if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
5280 0 : tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5281 0 : RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5282 : } else {
5283 0 : tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5284 0 : RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5285 : }
5286 :
5287 0 : adev->gfx.config.tcc_disabled_mask =
5288 0 : REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5289 0 : (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5290 0 : }
5291 :
5292 0 : static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5293 : {
5294 : u32 tmp;
5295 : int i;
5296 :
5297 0 : WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5298 :
5299 0 : gfx_v10_0_setup_rb(adev);
5300 0 : gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5301 0 : gfx_v10_0_get_tcc_info(adev);
5302 0 : adev->gfx.config.pa_sc_tile_steering_override =
5303 0 : gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5304 :
5305 : /* XXX SH_MEM regs */
5306 : /* where to put LDS, scratch, GPUVM in FSA64 space */
5307 0 : mutex_lock(&adev->srbm_mutex);
5308 0 : for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5309 0 : nv_grbm_select(adev, 0, 0, 0, i);
5310 : /* CP and shaders */
5311 0 : WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5312 0 : if (i != 0) {
5313 0 : tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5314 : (adev->gmc.private_aperture_start >> 48));
5315 0 : tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5316 : (adev->gmc.shared_aperture_start >> 48));
5317 0 : WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5318 : }
5319 : }
5320 0 : nv_grbm_select(adev, 0, 0, 0, 0);
5321 :
5322 0 : mutex_unlock(&adev->srbm_mutex);
5323 :
5324 0 : gfx_v10_0_init_compute_vmid(adev);
5325 0 : gfx_v10_0_init_gds_vmid(adev);
5326 :
5327 0 : }
5328 :
5329 0 : static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5330 : bool enable)
5331 : {
5332 : u32 tmp;
5333 :
5334 0 : if (amdgpu_sriov_vf(adev))
5335 : return;
5336 :
5337 0 : tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5338 :
5339 0 : tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5340 : enable ? 1 : 0);
5341 0 : tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5342 : enable ? 1 : 0);
5343 0 : tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5344 : enable ? 1 : 0);
5345 0 : tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5346 : enable ? 1 : 0);
5347 :
5348 0 : WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5349 : }
5350 :
5351 0 : static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5352 : {
5353 0 : adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5354 :
5355 : /* csib */
5356 0 : if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5357 0 : WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5358 : adev->gfx.rlc.clear_state_gpu_addr >> 32);
5359 0 : WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5360 : adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5361 0 : WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5362 : } else {
5363 0 : WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5364 : adev->gfx.rlc.clear_state_gpu_addr >> 32);
5365 0 : WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5366 : adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5367 0 : WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5368 : }
5369 0 : return 0;
5370 : }
5371 :
5372 0 : static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5373 : {
5374 0 : u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5375 :
5376 0 : tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5377 0 : WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5378 0 : }
5379 :
5380 0 : static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5381 : {
5382 0 : WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5383 0 : udelay(50);
5384 0 : WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5385 0 : udelay(50);
5386 0 : }
5387 :
5388 0 : static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5389 : bool enable)
5390 : {
5391 : uint32_t rlc_pg_cntl;
5392 :
5393 0 : rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5394 :
5395 0 : if (!enable) {
5396 : /* RLC_PG_CNTL[23] = 0 (default)
5397 : * RLC will wait for handshake acks with SMU
5398 : * GFXOFF will be enabled
5399 : * RLC_PG_CNTL[23] = 1
5400 : * RLC will not issue any message to SMU
5401 : * hence no handshake between SMU & RLC
5402 : * GFXOFF will be disabled
5403 : */
5404 0 : rlc_pg_cntl |= 0x800000;
5405 : } else
5406 0 : rlc_pg_cntl &= ~0x800000;
5407 0 : WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5408 0 : }
5409 :
5410 0 : static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5411 : {
5412 : /* TODO: enable rlc & smu handshake until smu
5413 : * and gfxoff feature works as expected */
5414 0 : if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5415 0 : gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5416 :
5417 0 : WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5418 0 : udelay(50);
5419 0 : }
5420 :
5421 0 : static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5422 : {
5423 : uint32_t tmp;
5424 :
5425 : /* enable Save Restore Machine */
5426 0 : tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5427 0 : tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5428 0 : tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5429 0 : WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5430 0 : }
5431 :
5432 0 : static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5433 : {
5434 : const struct rlc_firmware_header_v2_0 *hdr;
5435 : const __le32 *fw_data;
5436 : unsigned i, fw_size;
5437 :
5438 0 : if (!adev->gfx.rlc_fw)
5439 : return -EINVAL;
5440 :
5441 0 : hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5442 0 : amdgpu_ucode_print_rlc_hdr(&hdr->header);
5443 :
5444 0 : fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5445 0 : le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5446 0 : fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5447 :
5448 0 : WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5449 : RLCG_UCODE_LOADING_START_ADDRESS);
5450 :
5451 0 : for (i = 0; i < fw_size; i++)
5452 0 : WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5453 : le32_to_cpup(fw_data++));
5454 :
5455 0 : WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5456 :
5457 : return 0;
5458 : }
5459 :
5460 0 : static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5461 : {
5462 : int r;
5463 :
5464 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5465 0 : adev->psp.autoload_supported) {
5466 :
5467 0 : r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5468 0 : if (r)
5469 : return r;
5470 :
5471 0 : gfx_v10_0_init_csb(adev);
5472 :
5473 0 : if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5474 0 : gfx_v10_0_rlc_enable_srm(adev);
5475 : } else {
5476 0 : if (amdgpu_sriov_vf(adev)) {
5477 0 : gfx_v10_0_init_csb(adev);
5478 0 : return 0;
5479 : }
5480 :
5481 0 : adev->gfx.rlc.funcs->stop(adev);
5482 :
5483 : /* disable CG */
5484 0 : WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5485 :
5486 : /* disable PG */
5487 0 : WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5488 :
5489 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5490 : /* legacy rlc firmware loading */
5491 0 : r = gfx_v10_0_rlc_load_microcode(adev);
5492 0 : if (r)
5493 : return r;
5494 0 : } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5495 : /* rlc backdoor autoload firmware */
5496 0 : r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5497 0 : if (r)
5498 : return r;
5499 : }
5500 :
5501 0 : gfx_v10_0_init_csb(adev);
5502 :
5503 0 : adev->gfx.rlc.funcs->start(adev);
5504 :
5505 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5506 0 : r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5507 0 : if (r)
5508 : return r;
5509 : }
5510 : }
5511 : return 0;
5512 : }
5513 :
5514 : static struct {
5515 : FIRMWARE_ID id;
5516 : unsigned int offset;
5517 : unsigned int size;
5518 : } rlc_autoload_info[FIRMWARE_ID_MAX];
5519 :
5520 0 : static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5521 : {
5522 : int ret;
5523 : RLC_TABLE_OF_CONTENT *rlc_toc;
5524 :
5525 0 : ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5526 : AMDGPU_GEM_DOMAIN_GTT,
5527 : &adev->gfx.rlc.rlc_toc_bo,
5528 0 : &adev->gfx.rlc.rlc_toc_gpu_addr,
5529 : (void **)&adev->gfx.rlc.rlc_toc_buf);
5530 0 : if (ret) {
5531 0 : dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5532 0 : return ret;
5533 : }
5534 :
5535 : /* Copy toc from psp sos fw to rlc toc buffer */
5536 0 : memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5537 :
5538 0 : rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5539 0 : while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5540 : (rlc_toc->id < FIRMWARE_ID_MAX)) {
5541 0 : if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5542 : (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5543 : /* Offset needs 4KB alignment */
5544 0 : rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5545 : }
5546 :
5547 0 : rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5548 0 : rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5549 0 : rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5550 :
5551 0 : rlc_toc++;
5552 : }
5553 :
5554 : return 0;
5555 : }
5556 :
5557 0 : static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5558 : {
5559 0 : uint32_t total_size = 0;
5560 : FIRMWARE_ID id;
5561 : int ret;
5562 :
5563 0 : ret = gfx_v10_0_parse_rlc_toc(adev);
5564 0 : if (ret) {
5565 0 : dev_err(adev->dev, "failed to parse rlc toc\n");
5566 0 : return 0;
5567 : }
5568 :
5569 0 : for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5570 0 : total_size += rlc_autoload_info[id].size;
5571 :
5572 : /* In case the offset in rlc toc ucode is aligned */
5573 0 : if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5574 0 : total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5575 0 : rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5576 :
5577 : return total_size;
5578 : }
5579 :
5580 0 : static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5581 : {
5582 : int r;
5583 : uint32_t total_size;
5584 :
5585 0 : total_size = gfx_v10_0_calc_toc_total_size(adev);
5586 :
5587 0 : r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5588 : AMDGPU_GEM_DOMAIN_GTT,
5589 : &adev->gfx.rlc.rlc_autoload_bo,
5590 : &adev->gfx.rlc.rlc_autoload_gpu_addr,
5591 : (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5592 0 : if (r) {
5593 0 : dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5594 0 : return r;
5595 : }
5596 :
5597 : return 0;
5598 : }
5599 :
5600 0 : static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5601 : {
5602 0 : amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5603 0 : &adev->gfx.rlc.rlc_toc_gpu_addr,
5604 : (void **)&adev->gfx.rlc.rlc_toc_buf);
5605 0 : amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5606 : &adev->gfx.rlc.rlc_autoload_gpu_addr,
5607 : (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5608 0 : }
5609 :
5610 0 : static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5611 : FIRMWARE_ID id,
5612 : const void *fw_data,
5613 : uint32_t fw_size)
5614 : {
5615 : uint32_t toc_offset;
5616 : uint32_t toc_fw_size;
5617 0 : char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5618 :
5619 0 : if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5620 : return;
5621 :
5622 0 : toc_offset = rlc_autoload_info[id].offset;
5623 0 : toc_fw_size = rlc_autoload_info[id].size;
5624 :
5625 0 : if (fw_size == 0)
5626 0 : fw_size = toc_fw_size;
5627 :
5628 0 : if (fw_size > toc_fw_size)
5629 0 : fw_size = toc_fw_size;
5630 :
5631 0 : memcpy(ptr + toc_offset, fw_data, fw_size);
5632 :
5633 0 : if (fw_size < toc_fw_size)
5634 0 : memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5635 : }
5636 :
5637 : static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5638 : {
5639 : void *data;
5640 : uint32_t size;
5641 :
5642 0 : data = adev->gfx.rlc.rlc_toc_buf;
5643 0 : size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5644 :
5645 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5646 : FIRMWARE_ID_RLC_TOC,
5647 : data, size);
5648 : }
5649 :
5650 0 : static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5651 : {
5652 : const __le32 *fw_data;
5653 : uint32_t fw_size;
5654 : const struct gfx_firmware_header_v1_0 *cp_hdr;
5655 : const struct rlc_firmware_header_v2_0 *rlc_hdr;
5656 :
5657 : /* pfp ucode */
5658 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5659 0 : adev->gfx.pfp_fw->data;
5660 0 : fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5661 0 : le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5662 0 : fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5663 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5664 : FIRMWARE_ID_CP_PFP,
5665 : fw_data, fw_size);
5666 :
5667 : /* ce ucode */
5668 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5669 0 : adev->gfx.ce_fw->data;
5670 0 : fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5671 0 : le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5672 0 : fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5673 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5674 : FIRMWARE_ID_CP_CE,
5675 : fw_data, fw_size);
5676 :
5677 : /* me ucode */
5678 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5679 0 : adev->gfx.me_fw->data;
5680 0 : fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5681 0 : le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5682 0 : fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5683 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5684 : FIRMWARE_ID_CP_ME,
5685 : fw_data, fw_size);
5686 :
5687 : /* rlc ucode */
5688 0 : rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5689 0 : adev->gfx.rlc_fw->data;
5690 0 : fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5691 0 : le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5692 0 : fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5693 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5694 : FIRMWARE_ID_RLC_G_UCODE,
5695 : fw_data, fw_size);
5696 :
5697 : /* mec1 ucode */
5698 0 : cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5699 0 : adev->gfx.mec_fw->data;
5700 0 : fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5701 0 : le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5702 0 : fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5703 0 : cp_hdr->jt_size * 4;
5704 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5705 : FIRMWARE_ID_CP_MEC,
5706 : fw_data, fw_size);
5707 : /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5708 0 : }
5709 :
5710 : /* Temporarily put sdma part here */
5711 0 : static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5712 : {
5713 : const __le32 *fw_data;
5714 : uint32_t fw_size;
5715 : const struct sdma_firmware_header_v1_0 *sdma_hdr;
5716 : int i;
5717 :
5718 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
5719 0 : sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5720 0 : adev->sdma.instance[i].fw->data;
5721 0 : fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5722 0 : le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5723 0 : fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5724 :
5725 0 : if (i == 0) {
5726 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5727 : FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5728 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5729 : FIRMWARE_ID_SDMA0_JT,
5730 0 : (uint32_t *)fw_data +
5731 0 : sdma_hdr->jt_offset,
5732 0 : sdma_hdr->jt_size * 4);
5733 0 : } else if (i == 1) {
5734 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5735 : FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5736 0 : gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5737 : FIRMWARE_ID_SDMA1_JT,
5738 0 : (uint32_t *)fw_data +
5739 0 : sdma_hdr->jt_offset,
5740 0 : sdma_hdr->jt_size * 4);
5741 : }
5742 : }
5743 0 : }
5744 :
5745 0 : static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5746 : {
5747 : uint32_t rlc_g_offset, rlc_g_size, tmp;
5748 : uint64_t gpu_addr;
5749 :
5750 0 : gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5751 0 : gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5752 0 : gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5753 :
5754 0 : rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5755 0 : rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5756 0 : gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5757 :
5758 0 : WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5759 0 : WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5760 0 : WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5761 :
5762 0 : tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5763 0 : if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5764 : RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5765 0 : DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5766 0 : return -EINVAL;
5767 : }
5768 :
5769 0 : tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5770 0 : if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5771 0 : DRM_ERROR("RLC ROM should halt itself\n");
5772 0 : return -EINVAL;
5773 : }
5774 :
5775 : return 0;
5776 : }
5777 :
5778 0 : static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5779 : {
5780 0 : uint32_t usec_timeout = 50000; /* wait for 50ms */
5781 : uint32_t tmp;
5782 : int i;
5783 : uint64_t addr;
5784 :
5785 : /* Trigger an invalidation of the L1 instruction caches */
5786 0 : tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5787 0 : tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5788 0 : WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5789 :
5790 : /* Wait for invalidation complete */
5791 0 : for (i = 0; i < usec_timeout; i++) {
5792 0 : tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5793 0 : if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5794 : INVALIDATE_CACHE_COMPLETE))
5795 : break;
5796 0 : udelay(1);
5797 : }
5798 :
5799 0 : if (i >= usec_timeout) {
5800 0 : dev_err(adev->dev, "failed to invalidate instruction cache\n");
5801 0 : return -EINVAL;
5802 : }
5803 :
5804 : /* Program me ucode address into intruction cache address register */
5805 0 : addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5806 0 : rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5807 0 : WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5808 : lower_32_bits(addr) & 0xFFFFF000);
5809 0 : WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5810 : upper_32_bits(addr));
5811 :
5812 : return 0;
5813 : }
5814 :
5815 0 : static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5816 : {
5817 0 : uint32_t usec_timeout = 50000; /* wait for 50ms */
5818 : uint32_t tmp;
5819 : int i;
5820 : uint64_t addr;
5821 :
5822 : /* Trigger an invalidation of the L1 instruction caches */
5823 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5824 0 : tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5825 0 : WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5826 :
5827 : /* Wait for invalidation complete */
5828 0 : for (i = 0; i < usec_timeout; i++) {
5829 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5830 0 : if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5831 : INVALIDATE_CACHE_COMPLETE))
5832 : break;
5833 0 : udelay(1);
5834 : }
5835 :
5836 0 : if (i >= usec_timeout) {
5837 0 : dev_err(adev->dev, "failed to invalidate instruction cache\n");
5838 0 : return -EINVAL;
5839 : }
5840 :
5841 : /* Program ce ucode address into intruction cache address register */
5842 0 : addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5843 0 : rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5844 0 : WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5845 : lower_32_bits(addr) & 0xFFFFF000);
5846 0 : WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5847 : upper_32_bits(addr));
5848 :
5849 : return 0;
5850 : }
5851 :
5852 0 : static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5853 : {
5854 0 : uint32_t usec_timeout = 50000; /* wait for 50ms */
5855 : uint32_t tmp;
5856 : int i;
5857 : uint64_t addr;
5858 :
5859 : /* Trigger an invalidation of the L1 instruction caches */
5860 0 : tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5861 0 : tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5862 0 : WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5863 :
5864 : /* Wait for invalidation complete */
5865 0 : for (i = 0; i < usec_timeout; i++) {
5866 0 : tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5867 0 : if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5868 : INVALIDATE_CACHE_COMPLETE))
5869 : break;
5870 0 : udelay(1);
5871 : }
5872 :
5873 0 : if (i >= usec_timeout) {
5874 0 : dev_err(adev->dev, "failed to invalidate instruction cache\n");
5875 0 : return -EINVAL;
5876 : }
5877 :
5878 : /* Program pfp ucode address into intruction cache address register */
5879 0 : addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5880 0 : rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5881 0 : WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5882 : lower_32_bits(addr) & 0xFFFFF000);
5883 0 : WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5884 : upper_32_bits(addr));
5885 :
5886 : return 0;
5887 : }
5888 :
5889 0 : static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5890 : {
5891 0 : uint32_t usec_timeout = 50000; /* wait for 50ms */
5892 : uint32_t tmp;
5893 : int i;
5894 : uint64_t addr;
5895 :
5896 : /* Trigger an invalidation of the L1 instruction caches */
5897 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5898 0 : tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5899 0 : WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5900 :
5901 : /* Wait for invalidation complete */
5902 0 : for (i = 0; i < usec_timeout; i++) {
5903 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5904 0 : if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5905 : INVALIDATE_CACHE_COMPLETE))
5906 : break;
5907 0 : udelay(1);
5908 : }
5909 :
5910 0 : if (i >= usec_timeout) {
5911 0 : dev_err(adev->dev, "failed to invalidate instruction cache\n");
5912 0 : return -EINVAL;
5913 : }
5914 :
5915 : /* Program mec1 ucode address into intruction cache address register */
5916 0 : addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5917 0 : rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5918 0 : WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5919 : lower_32_bits(addr) & 0xFFFFF000);
5920 0 : WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5921 : upper_32_bits(addr));
5922 :
5923 : return 0;
5924 : }
5925 :
5926 0 : static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5927 : {
5928 : uint32_t cp_status;
5929 : uint32_t bootload_status;
5930 : int i, r;
5931 :
5932 0 : for (i = 0; i < adev->usec_timeout; i++) {
5933 0 : cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5934 0 : bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5935 0 : if ((cp_status == 0) &&
5936 0 : (REG_GET_FIELD(bootload_status,
5937 : RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5938 : break;
5939 : }
5940 0 : udelay(1);
5941 : }
5942 :
5943 0 : if (i >= adev->usec_timeout) {
5944 0 : dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5945 0 : return -ETIMEDOUT;
5946 : }
5947 :
5948 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5949 0 : r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5950 0 : if (r)
5951 : return r;
5952 :
5953 0 : r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5954 0 : if (r)
5955 : return r;
5956 :
5957 0 : r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5958 0 : if (r)
5959 : return r;
5960 :
5961 0 : r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5962 0 : if (r)
5963 : return r;
5964 : }
5965 :
5966 : return 0;
5967 : }
5968 :
5969 0 : static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5970 : {
5971 : int i;
5972 0 : u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5973 :
5974 0 : tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5975 0 : tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5976 0 : tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5977 :
5978 0 : if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5979 0 : WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5980 : } else {
5981 0 : WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5982 : }
5983 :
5984 0 : if (adev->job_hang && !enable)
5985 : return 0;
5986 :
5987 0 : for (i = 0; i < adev->usec_timeout; i++) {
5988 0 : if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5989 : break;
5990 0 : udelay(1);
5991 : }
5992 :
5993 0 : if (i >= adev->usec_timeout)
5994 0 : DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5995 :
5996 : return 0;
5997 : }
5998 :
5999 0 : static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
6000 : {
6001 : int r;
6002 : const struct gfx_firmware_header_v1_0 *pfp_hdr;
6003 : const __le32 *fw_data;
6004 : unsigned i, fw_size;
6005 : uint32_t tmp;
6006 0 : uint32_t usec_timeout = 50000; /* wait for 50ms */
6007 :
6008 0 : pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
6009 0 : adev->gfx.pfp_fw->data;
6010 :
6011 0 : amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
6012 :
6013 0 : fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
6014 0 : le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
6015 0 : fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
6016 :
6017 0 : r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
6018 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6019 : &adev->gfx.pfp.pfp_fw_obj,
6020 0 : &adev->gfx.pfp.pfp_fw_gpu_addr,
6021 0 : (void **)&adev->gfx.pfp.pfp_fw_ptr);
6022 0 : if (r) {
6023 0 : dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6024 0 : gfx_v10_0_pfp_fini(adev);
6025 0 : return r;
6026 : }
6027 :
6028 0 : memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6029 :
6030 0 : amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6031 0 : amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6032 :
6033 : /* Trigger an invalidation of the L1 instruction caches */
6034 0 : tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6035 0 : tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6036 0 : WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6037 :
6038 : /* Wait for invalidation complete */
6039 0 : for (i = 0; i < usec_timeout; i++) {
6040 0 : tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6041 0 : if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6042 : INVALIDATE_CACHE_COMPLETE))
6043 : break;
6044 0 : udelay(1);
6045 : }
6046 :
6047 0 : if (i >= usec_timeout) {
6048 0 : dev_err(adev->dev, "failed to invalidate instruction cache\n");
6049 0 : return -EINVAL;
6050 : }
6051 :
6052 0 : if (amdgpu_emu_mode == 1)
6053 0 : adev->hdp.funcs->flush_hdp(adev, NULL);
6054 :
6055 0 : tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6056 0 : tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6057 0 : tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6058 0 : tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6059 0 : tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6060 0 : WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6061 0 : WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6062 : adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6063 0 : WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6064 : upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6065 :
6066 0 : WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6067 :
6068 0 : for (i = 0; i < pfp_hdr->jt_size; i++)
6069 0 : WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6070 : le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6071 :
6072 0 : WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6073 :
6074 : return 0;
6075 : }
6076 :
6077 0 : static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6078 : {
6079 : int r;
6080 : const struct gfx_firmware_header_v1_0 *ce_hdr;
6081 : const __le32 *fw_data;
6082 : unsigned i, fw_size;
6083 : uint32_t tmp;
6084 0 : uint32_t usec_timeout = 50000; /* wait for 50ms */
6085 :
6086 0 : ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6087 0 : adev->gfx.ce_fw->data;
6088 :
6089 0 : amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6090 :
6091 0 : fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6092 0 : le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6093 0 : fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6094 :
6095 0 : r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6096 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6097 : &adev->gfx.ce.ce_fw_obj,
6098 0 : &adev->gfx.ce.ce_fw_gpu_addr,
6099 0 : (void **)&adev->gfx.ce.ce_fw_ptr);
6100 0 : if (r) {
6101 0 : dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6102 0 : gfx_v10_0_ce_fini(adev);
6103 0 : return r;
6104 : }
6105 :
6106 0 : memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6107 :
6108 0 : amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6109 0 : amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6110 :
6111 : /* Trigger an invalidation of the L1 instruction caches */
6112 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6113 0 : tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6114 0 : WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6115 :
6116 : /* Wait for invalidation complete */
6117 0 : for (i = 0; i < usec_timeout; i++) {
6118 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6119 0 : if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6120 : INVALIDATE_CACHE_COMPLETE))
6121 : break;
6122 0 : udelay(1);
6123 : }
6124 :
6125 0 : if (i >= usec_timeout) {
6126 0 : dev_err(adev->dev, "failed to invalidate instruction cache\n");
6127 0 : return -EINVAL;
6128 : }
6129 :
6130 0 : if (amdgpu_emu_mode == 1)
6131 0 : adev->hdp.funcs->flush_hdp(adev, NULL);
6132 :
6133 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6134 0 : tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6135 0 : tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6136 0 : tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6137 0 : tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6138 0 : WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6139 : adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6140 0 : WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6141 : upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6142 :
6143 0 : WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6144 :
6145 0 : for (i = 0; i < ce_hdr->jt_size; i++)
6146 0 : WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6147 : le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6148 :
6149 0 : WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6150 :
6151 : return 0;
6152 : }
6153 :
6154 0 : static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6155 : {
6156 : int r;
6157 : const struct gfx_firmware_header_v1_0 *me_hdr;
6158 : const __le32 *fw_data;
6159 : unsigned i, fw_size;
6160 : uint32_t tmp;
6161 0 : uint32_t usec_timeout = 50000; /* wait for 50ms */
6162 :
6163 0 : me_hdr = (const struct gfx_firmware_header_v1_0 *)
6164 0 : adev->gfx.me_fw->data;
6165 :
6166 0 : amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6167 :
6168 0 : fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6169 0 : le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6170 0 : fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6171 :
6172 0 : r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6173 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6174 : &adev->gfx.me.me_fw_obj,
6175 0 : &adev->gfx.me.me_fw_gpu_addr,
6176 0 : (void **)&adev->gfx.me.me_fw_ptr);
6177 0 : if (r) {
6178 0 : dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6179 0 : gfx_v10_0_me_fini(adev);
6180 0 : return r;
6181 : }
6182 :
6183 0 : memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6184 :
6185 0 : amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6186 0 : amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6187 :
6188 : /* Trigger an invalidation of the L1 instruction caches */
6189 0 : tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6190 0 : tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6191 0 : WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6192 :
6193 : /* Wait for invalidation complete */
6194 0 : for (i = 0; i < usec_timeout; i++) {
6195 0 : tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6196 0 : if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6197 : INVALIDATE_CACHE_COMPLETE))
6198 : break;
6199 0 : udelay(1);
6200 : }
6201 :
6202 0 : if (i >= usec_timeout) {
6203 0 : dev_err(adev->dev, "failed to invalidate instruction cache\n");
6204 0 : return -EINVAL;
6205 : }
6206 :
6207 0 : if (amdgpu_emu_mode == 1)
6208 0 : adev->hdp.funcs->flush_hdp(adev, NULL);
6209 :
6210 0 : tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6211 0 : tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6212 0 : tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6213 0 : tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6214 0 : tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6215 0 : WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6216 : adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6217 0 : WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6218 : upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6219 :
6220 0 : WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6221 :
6222 0 : for (i = 0; i < me_hdr->jt_size; i++)
6223 0 : WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6224 : le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6225 :
6226 0 : WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6227 :
6228 : return 0;
6229 : }
6230 :
6231 0 : static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6232 : {
6233 : int r;
6234 :
6235 0 : if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6236 : return -EINVAL;
6237 :
6238 0 : gfx_v10_0_cp_gfx_enable(adev, false);
6239 :
6240 0 : r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6241 0 : if (r) {
6242 0 : dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6243 0 : return r;
6244 : }
6245 :
6246 0 : r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6247 0 : if (r) {
6248 0 : dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6249 0 : return r;
6250 : }
6251 :
6252 0 : r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6253 0 : if (r) {
6254 0 : dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6255 0 : return r;
6256 : }
6257 :
6258 : return 0;
6259 : }
6260 :
6261 0 : static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6262 : {
6263 : struct amdgpu_ring *ring;
6264 0 : const struct cs_section_def *sect = NULL;
6265 0 : const struct cs_extent_def *ext = NULL;
6266 : int r, i;
6267 : int ctx_reg_offset;
6268 :
6269 : /* init the CP */
6270 0 : WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6271 : adev->gfx.config.max_hw_contexts - 1);
6272 0 : WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6273 :
6274 0 : gfx_v10_0_cp_gfx_enable(adev, true);
6275 :
6276 0 : ring = &adev->gfx.gfx_ring[0];
6277 0 : r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6278 0 : if (r) {
6279 0 : DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6280 0 : return r;
6281 : }
6282 :
6283 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6284 0 : amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6285 :
6286 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6287 0 : amdgpu_ring_write(ring, 0x80000000);
6288 0 : amdgpu_ring_write(ring, 0x80000000);
6289 :
6290 0 : for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6291 0 : for (ext = sect->section; ext->extent != NULL; ++ext) {
6292 0 : if (sect->id == SECT_CONTEXT) {
6293 0 : amdgpu_ring_write(ring,
6294 0 : PACKET3(PACKET3_SET_CONTEXT_REG,
6295 : ext->reg_count));
6296 0 : amdgpu_ring_write(ring, ext->reg_index -
6297 : PACKET3_SET_CONTEXT_REG_START);
6298 0 : for (i = 0; i < ext->reg_count; i++)
6299 0 : amdgpu_ring_write(ring, ext->extent[i]);
6300 : }
6301 : }
6302 : }
6303 :
6304 0 : ctx_reg_offset =
6305 0 : SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6306 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6307 0 : amdgpu_ring_write(ring, ctx_reg_offset);
6308 0 : amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6309 :
6310 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6311 0 : amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6312 :
6313 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6314 0 : amdgpu_ring_write(ring, 0);
6315 :
6316 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6317 0 : amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6318 0 : amdgpu_ring_write(ring, 0x8000);
6319 0 : amdgpu_ring_write(ring, 0x8000);
6320 :
6321 0 : amdgpu_ring_commit(ring);
6322 :
6323 : /* submit cs packet to copy state 0 to next available state */
6324 0 : if (adev->gfx.num_gfx_rings > 1) {
6325 : /* maximum supported gfx ring is 2 */
6326 0 : ring = &adev->gfx.gfx_ring[1];
6327 0 : r = amdgpu_ring_alloc(ring, 2);
6328 0 : if (r) {
6329 0 : DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6330 0 : return r;
6331 : }
6332 :
6333 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6334 0 : amdgpu_ring_write(ring, 0);
6335 :
6336 0 : amdgpu_ring_commit(ring);
6337 : }
6338 : return 0;
6339 : }
6340 :
6341 0 : static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6342 : CP_PIPE_ID pipe)
6343 : {
6344 : u32 tmp;
6345 :
6346 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6347 0 : tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6348 :
6349 0 : WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6350 0 : }
6351 :
6352 0 : static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6353 : struct amdgpu_ring *ring)
6354 : {
6355 : u32 tmp;
6356 :
6357 0 : if (!amdgpu_async_gfx_ring) {
6358 0 : tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6359 0 : if (ring->use_doorbell) {
6360 0 : tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6361 : DOORBELL_OFFSET, ring->doorbell_index);
6362 0 : tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6363 : DOORBELL_EN, 1);
6364 : } else {
6365 0 : tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6366 : DOORBELL_EN, 0);
6367 : }
6368 0 : WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6369 : }
6370 0 : switch (adev->ip_versions[GC_HWIP][0]) {
6371 : case IP_VERSION(10, 3, 0):
6372 : case IP_VERSION(10, 3, 2):
6373 : case IP_VERSION(10, 3, 1):
6374 : case IP_VERSION(10, 3, 4):
6375 : case IP_VERSION(10, 3, 5):
6376 : case IP_VERSION(10, 3, 6):
6377 : case IP_VERSION(10, 3, 3):
6378 : case IP_VERSION(10, 3, 7):
6379 0 : tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6380 : DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6381 0 : WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6382 :
6383 0 : WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6384 : CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6385 : break;
6386 : default:
6387 0 : tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6388 : DOORBELL_RANGE_LOWER, ring->doorbell_index);
6389 0 : WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6390 :
6391 0 : WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6392 : CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6393 : break;
6394 : }
6395 0 : }
6396 :
6397 0 : static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6398 : {
6399 : struct amdgpu_ring *ring;
6400 : u32 tmp;
6401 : u32 rb_bufsz;
6402 : u64 rb_addr, rptr_addr, wptr_gpu_addr;
6403 : u32 i;
6404 :
6405 : /* Set the write pointer delay */
6406 0 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6407 :
6408 : /* set the RB to use vmid 0 */
6409 0 : WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6410 :
6411 : /* Init gfx ring 0 for pipe 0 */
6412 0 : mutex_lock(&adev->srbm_mutex);
6413 0 : gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6414 :
6415 : /* Set ring buffer size */
6416 0 : ring = &adev->gfx.gfx_ring[0];
6417 0 : rb_bufsz = order_base_2(ring->ring_size / 8);
6418 0 : tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6419 0 : tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6420 : #ifdef __BIG_ENDIAN
6421 : tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6422 : #endif
6423 0 : WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6424 :
6425 : /* Initialize the ring buffer's write pointers */
6426 0 : ring->wptr = 0;
6427 0 : WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6428 0 : WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6429 :
6430 : /* set the wb address wether it's enabled or not */
6431 0 : rptr_addr = ring->rptr_gpu_addr;
6432 0 : WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6433 0 : WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6434 : CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6435 :
6436 0 : wptr_gpu_addr = ring->wptr_gpu_addr;
6437 0 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6438 : lower_32_bits(wptr_gpu_addr));
6439 0 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6440 : upper_32_bits(wptr_gpu_addr));
6441 :
6442 0 : mdelay(1);
6443 0 : WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6444 :
6445 0 : rb_addr = ring->gpu_addr >> 8;
6446 0 : WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6447 0 : WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6448 :
6449 0 : WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6450 :
6451 0 : gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6452 0 : mutex_unlock(&adev->srbm_mutex);
6453 :
6454 : /* Init gfx ring 1 for pipe 1 */
6455 0 : if (adev->gfx.num_gfx_rings > 1) {
6456 0 : mutex_lock(&adev->srbm_mutex);
6457 0 : gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6458 : /* maximum supported gfx ring is 2 */
6459 0 : ring = &adev->gfx.gfx_ring[1];
6460 0 : rb_bufsz = order_base_2(ring->ring_size / 8);
6461 0 : tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6462 0 : tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6463 0 : WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6464 : /* Initialize the ring buffer's write pointers */
6465 0 : ring->wptr = 0;
6466 0 : WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6467 0 : WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6468 : /* Set the wb address wether it's enabled or not */
6469 0 : rptr_addr = ring->rptr_gpu_addr;
6470 0 : WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6471 0 : WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6472 : CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6473 0 : wptr_gpu_addr = ring->wptr_gpu_addr;
6474 0 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6475 : lower_32_bits(wptr_gpu_addr));
6476 0 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6477 : upper_32_bits(wptr_gpu_addr));
6478 :
6479 0 : mdelay(1);
6480 0 : WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6481 :
6482 0 : rb_addr = ring->gpu_addr >> 8;
6483 0 : WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6484 0 : WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6485 0 : WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6486 :
6487 0 : gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6488 0 : mutex_unlock(&adev->srbm_mutex);
6489 : }
6490 : /* Switch to pipe 0 */
6491 0 : mutex_lock(&adev->srbm_mutex);
6492 0 : gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6493 0 : mutex_unlock(&adev->srbm_mutex);
6494 :
6495 : /* start the ring */
6496 0 : gfx_v10_0_cp_gfx_start(adev);
6497 :
6498 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6499 0 : ring = &adev->gfx.gfx_ring[i];
6500 0 : ring->sched.ready = true;
6501 : }
6502 :
6503 0 : return 0;
6504 : }
6505 :
6506 0 : static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6507 : {
6508 0 : if (enable) {
6509 0 : switch (adev->ip_versions[GC_HWIP][0]) {
6510 : case IP_VERSION(10, 3, 0):
6511 : case IP_VERSION(10, 3, 2):
6512 : case IP_VERSION(10, 3, 1):
6513 : case IP_VERSION(10, 3, 4):
6514 : case IP_VERSION(10, 3, 5):
6515 : case IP_VERSION(10, 3, 6):
6516 : case IP_VERSION(10, 3, 3):
6517 : case IP_VERSION(10, 3, 7):
6518 0 : WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6519 : break;
6520 : default:
6521 0 : WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6522 : break;
6523 : }
6524 : } else {
6525 0 : switch (adev->ip_versions[GC_HWIP][0]) {
6526 : case IP_VERSION(10, 3, 0):
6527 : case IP_VERSION(10, 3, 2):
6528 : case IP_VERSION(10, 3, 1):
6529 : case IP_VERSION(10, 3, 4):
6530 : case IP_VERSION(10, 3, 5):
6531 : case IP_VERSION(10, 3, 6):
6532 : case IP_VERSION(10, 3, 3):
6533 : case IP_VERSION(10, 3, 7):
6534 0 : WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6535 : (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6536 : CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6537 : break;
6538 : default:
6539 0 : WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6540 : (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6541 : CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6542 : break;
6543 : }
6544 0 : adev->gfx.kiq.ring.sched.ready = false;
6545 : }
6546 0 : udelay(50);
6547 0 : }
6548 :
6549 0 : static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6550 : {
6551 : const struct gfx_firmware_header_v1_0 *mec_hdr;
6552 : const __le32 *fw_data;
6553 : unsigned i;
6554 : u32 tmp;
6555 0 : u32 usec_timeout = 50000; /* Wait for 50 ms */
6556 :
6557 0 : if (!adev->gfx.mec_fw)
6558 : return -EINVAL;
6559 :
6560 0 : gfx_v10_0_cp_compute_enable(adev, false);
6561 :
6562 0 : mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6563 0 : amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6564 :
6565 0 : fw_data = (const __le32 *)
6566 0 : (adev->gfx.mec_fw->data +
6567 0 : le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6568 :
6569 : /* Trigger an invalidation of the L1 instruction caches */
6570 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6571 0 : tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6572 0 : WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6573 :
6574 : /* Wait for invalidation complete */
6575 0 : for (i = 0; i < usec_timeout; i++) {
6576 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6577 0 : if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6578 : INVALIDATE_CACHE_COMPLETE))
6579 : break;
6580 0 : udelay(1);
6581 : }
6582 :
6583 0 : if (i >= usec_timeout) {
6584 0 : dev_err(adev->dev, "failed to invalidate instruction cache\n");
6585 0 : return -EINVAL;
6586 : }
6587 :
6588 0 : if (amdgpu_emu_mode == 1)
6589 0 : adev->hdp.funcs->flush_hdp(adev, NULL);
6590 :
6591 0 : tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6592 0 : tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6593 0 : tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6594 0 : tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6595 0 : WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6596 :
6597 0 : WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6598 : 0xFFFFF000);
6599 0 : WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6600 : upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6601 :
6602 : /* MEC1 */
6603 0 : WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6604 :
6605 0 : for (i = 0; i < mec_hdr->jt_size; i++)
6606 0 : WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6607 : le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6608 :
6609 0 : WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6610 :
6611 : /*
6612 : * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6613 : * different microcode than MEC1.
6614 : */
6615 :
6616 : return 0;
6617 : }
6618 :
6619 0 : static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6620 : {
6621 : uint32_t tmp;
6622 0 : struct amdgpu_device *adev = ring->adev;
6623 :
6624 : /* tell RLC which is KIQ queue */
6625 0 : switch (adev->ip_versions[GC_HWIP][0]) {
6626 : case IP_VERSION(10, 3, 0):
6627 : case IP_VERSION(10, 3, 2):
6628 : case IP_VERSION(10, 3, 1):
6629 : case IP_VERSION(10, 3, 4):
6630 : case IP_VERSION(10, 3, 5):
6631 : case IP_VERSION(10, 3, 6):
6632 : case IP_VERSION(10, 3, 3):
6633 : case IP_VERSION(10, 3, 7):
6634 0 : tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6635 0 : tmp &= 0xffffff00;
6636 0 : tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6637 0 : WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6638 0 : tmp |= 0x80;
6639 0 : WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6640 : break;
6641 : default:
6642 0 : tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6643 0 : tmp &= 0xffffff00;
6644 0 : tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6645 0 : WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6646 0 : tmp |= 0x80;
6647 0 : WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6648 : break;
6649 : }
6650 0 : }
6651 :
6652 0 : static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6653 : struct v10_gfx_mqd *mqd,
6654 : struct amdgpu_mqd_prop *prop)
6655 : {
6656 0 : bool priority = 0;
6657 : u32 tmp;
6658 :
6659 : /* set up default queue priority level
6660 : * 0x0 = low priority, 0x1 = high priority
6661 : */
6662 0 : if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6663 0 : priority = 1;
6664 :
6665 0 : tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6666 0 : tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6667 0 : mqd->cp_gfx_hqd_queue_priority = tmp;
6668 0 : }
6669 :
6670 0 : static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6671 : struct amdgpu_mqd_prop *prop)
6672 : {
6673 0 : struct v10_gfx_mqd *mqd = m;
6674 : uint64_t hqd_gpu_addr, wb_gpu_addr;
6675 : uint32_t tmp;
6676 : uint32_t rb_bufsz;
6677 :
6678 : /* set up gfx hqd wptr */
6679 0 : mqd->cp_gfx_hqd_wptr = 0;
6680 0 : mqd->cp_gfx_hqd_wptr_hi = 0;
6681 :
6682 : /* set the pointer to the MQD */
6683 0 : mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6684 0 : mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6685 :
6686 : /* set up mqd control */
6687 0 : tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6688 0 : tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6689 0 : tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6690 0 : tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6691 0 : mqd->cp_gfx_mqd_control = tmp;
6692 :
6693 : /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6694 0 : tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6695 0 : tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6696 0 : mqd->cp_gfx_hqd_vmid = 0;
6697 :
6698 : /* set up gfx queue priority */
6699 0 : gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6700 :
6701 : /* set up time quantum */
6702 0 : tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6703 0 : tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6704 0 : mqd->cp_gfx_hqd_quantum = tmp;
6705 :
6706 : /* set up gfx hqd base. this is similar as CP_RB_BASE */
6707 0 : hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6708 0 : mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6709 0 : mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6710 :
6711 : /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6712 0 : wb_gpu_addr = prop->rptr_gpu_addr;
6713 0 : mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6714 0 : mqd->cp_gfx_hqd_rptr_addr_hi =
6715 0 : upper_32_bits(wb_gpu_addr) & 0xffff;
6716 :
6717 : /* set up rb_wptr_poll addr */
6718 0 : wb_gpu_addr = prop->wptr_gpu_addr;
6719 0 : mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6720 0 : mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6721 :
6722 : /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6723 0 : rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6724 0 : tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6725 0 : tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6726 0 : tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6727 : #ifdef __BIG_ENDIAN
6728 : tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6729 : #endif
6730 0 : mqd->cp_gfx_hqd_cntl = tmp;
6731 :
6732 : /* set up cp_doorbell_control */
6733 0 : tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6734 0 : if (prop->use_doorbell) {
6735 0 : tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6736 : DOORBELL_OFFSET, prop->doorbell_index);
6737 0 : tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6738 : DOORBELL_EN, 1);
6739 : } else
6740 0 : tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6741 : DOORBELL_EN, 0);
6742 0 : mqd->cp_rb_doorbell_control = tmp;
6743 :
6744 : /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6745 0 : mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6746 :
6747 : /* active the queue */
6748 0 : mqd->cp_gfx_hqd_active = 1;
6749 :
6750 0 : return 0;
6751 : }
6752 :
6753 : #ifdef BRING_UP_DEBUG
6754 : static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6755 : {
6756 : struct amdgpu_device *adev = ring->adev;
6757 : struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6758 :
6759 : /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6760 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6761 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6762 :
6763 : /* set GFX_MQD_BASE */
6764 : WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6765 : WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6766 :
6767 : /* set GFX_MQD_CONTROL */
6768 : WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6769 :
6770 : /* set GFX_HQD_VMID to 0 */
6771 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6772 :
6773 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6774 : mqd->cp_gfx_hqd_queue_priority);
6775 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6776 :
6777 : /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6778 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6779 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6780 :
6781 : /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6782 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6783 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6784 :
6785 : /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6786 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6787 :
6788 : /* set RB_WPTR_POLL_ADDR */
6789 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6790 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6791 :
6792 : /* set RB_DOORBELL_CONTROL */
6793 : WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6794 :
6795 : /* active the queue */
6796 : WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6797 :
6798 : return 0;
6799 : }
6800 : #endif
6801 :
6802 0 : static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6803 : {
6804 0 : struct amdgpu_device *adev = ring->adev;
6805 0 : struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6806 0 : int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6807 :
6808 0 : if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6809 0 : memset((void *)mqd, 0, sizeof(*mqd));
6810 0 : mutex_lock(&adev->srbm_mutex);
6811 0 : nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6812 0 : amdgpu_ring_init_mqd(ring);
6813 :
6814 : /*
6815 : * if there are 2 gfx rings, set the lower doorbell
6816 : * range of the first ring, otherwise the range of
6817 : * the second ring will override the first ring
6818 : */
6819 0 : if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6820 0 : gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6821 :
6822 : #ifdef BRING_UP_DEBUG
6823 : gfx_v10_0_gfx_queue_init_register(ring);
6824 : #endif
6825 0 : nv_grbm_select(adev, 0, 0, 0, 0);
6826 0 : mutex_unlock(&adev->srbm_mutex);
6827 0 : if (adev->gfx.me.mqd_backup[mqd_idx])
6828 0 : memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6829 0 : } else if (amdgpu_in_reset(adev)) {
6830 : /* reset mqd with the backup copy */
6831 0 : if (adev->gfx.me.mqd_backup[mqd_idx])
6832 0 : memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6833 : /* reset the ring */
6834 0 : ring->wptr = 0;
6835 0 : *ring->wptr_cpu_addr = 0;
6836 : amdgpu_ring_clear_ring(ring);
6837 : #ifdef BRING_UP_DEBUG
6838 : mutex_lock(&adev->srbm_mutex);
6839 : nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6840 : gfx_v10_0_gfx_queue_init_register(ring);
6841 : nv_grbm_select(adev, 0, 0, 0, 0);
6842 : mutex_unlock(&adev->srbm_mutex);
6843 : #endif
6844 : } else {
6845 : amdgpu_ring_clear_ring(ring);
6846 : }
6847 :
6848 0 : return 0;
6849 : }
6850 :
6851 : #ifndef BRING_UP_DEBUG
6852 0 : static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6853 : {
6854 0 : struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6855 0 : struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6856 : int r, i;
6857 :
6858 0 : if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6859 : return -EINVAL;
6860 :
6861 0 : r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6862 0 : adev->gfx.num_gfx_rings);
6863 0 : if (r) {
6864 0 : DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6865 0 : return r;
6866 : }
6867 :
6868 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6869 0 : kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6870 :
6871 0 : return amdgpu_ring_test_helper(kiq_ring);
6872 : }
6873 : #endif
6874 :
6875 0 : static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6876 : {
6877 : int r, i;
6878 : struct amdgpu_ring *ring;
6879 :
6880 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6881 0 : ring = &adev->gfx.gfx_ring[i];
6882 :
6883 0 : r = amdgpu_bo_reserve(ring->mqd_obj, false);
6884 0 : if (unlikely(r != 0))
6885 : goto done;
6886 :
6887 0 : r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6888 0 : if (!r) {
6889 0 : r = gfx_v10_0_gfx_init_queue(ring);
6890 0 : amdgpu_bo_kunmap(ring->mqd_obj);
6891 0 : ring->mqd_ptr = NULL;
6892 : }
6893 0 : amdgpu_bo_unreserve(ring->mqd_obj);
6894 0 : if (r)
6895 : goto done;
6896 : }
6897 : #ifndef BRING_UP_DEBUG
6898 0 : r = gfx_v10_0_kiq_enable_kgq(adev);
6899 0 : if (r)
6900 : goto done;
6901 : #endif
6902 0 : r = gfx_v10_0_cp_gfx_start(adev);
6903 0 : if (r)
6904 : goto done;
6905 :
6906 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6907 0 : ring = &adev->gfx.gfx_ring[i];
6908 0 : ring->sched.ready = true;
6909 : }
6910 : done:
6911 0 : return r;
6912 : }
6913 :
6914 0 : static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6915 : struct amdgpu_mqd_prop *prop)
6916 : {
6917 0 : struct v10_compute_mqd *mqd = m;
6918 : uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6919 : uint32_t tmp;
6920 :
6921 0 : mqd->header = 0xC0310800;
6922 0 : mqd->compute_pipelinestat_enable = 0x00000001;
6923 0 : mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6924 0 : mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6925 0 : mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6926 0 : mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6927 0 : mqd->compute_misc_reserved = 0x00000003;
6928 :
6929 0 : eop_base_addr = prop->eop_gpu_addr >> 8;
6930 0 : mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6931 0 : mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6932 :
6933 : /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6934 0 : tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6935 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6936 : (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6937 :
6938 0 : mqd->cp_hqd_eop_control = tmp;
6939 :
6940 : /* enable doorbell? */
6941 0 : tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6942 :
6943 0 : if (prop->use_doorbell) {
6944 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6945 : DOORBELL_OFFSET, prop->doorbell_index);
6946 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6947 : DOORBELL_EN, 1);
6948 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6949 : DOORBELL_SOURCE, 0);
6950 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6951 : DOORBELL_HIT, 0);
6952 : } else {
6953 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6954 : DOORBELL_EN, 0);
6955 : }
6956 :
6957 0 : mqd->cp_hqd_pq_doorbell_control = tmp;
6958 :
6959 : /* disable the queue if it's active */
6960 0 : mqd->cp_hqd_dequeue_request = 0;
6961 0 : mqd->cp_hqd_pq_rptr = 0;
6962 0 : mqd->cp_hqd_pq_wptr_lo = 0;
6963 0 : mqd->cp_hqd_pq_wptr_hi = 0;
6964 :
6965 : /* set the pointer to the MQD */
6966 0 : mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6967 0 : mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6968 :
6969 : /* set MQD vmid to 0 */
6970 0 : tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6971 0 : tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6972 0 : mqd->cp_mqd_control = tmp;
6973 :
6974 : /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6975 0 : hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6976 0 : mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6977 0 : mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6978 :
6979 : /* set up the HQD, this is similar to CP_RB0_CNTL */
6980 0 : tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6981 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6982 : (order_base_2(prop->queue_size / 4) - 1));
6983 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6984 : (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6985 : #ifdef __BIG_ENDIAN
6986 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6987 : #endif
6988 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6989 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6990 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6991 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6992 0 : mqd->cp_hqd_pq_control = tmp;
6993 :
6994 : /* set the wb address whether it's enabled or not */
6995 0 : wb_gpu_addr = prop->rptr_gpu_addr;
6996 0 : mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6997 0 : mqd->cp_hqd_pq_rptr_report_addr_hi =
6998 0 : upper_32_bits(wb_gpu_addr) & 0xffff;
6999 :
7000 : /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7001 0 : wb_gpu_addr = prop->wptr_gpu_addr;
7002 0 : mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
7003 0 : mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
7004 :
7005 : /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7006 0 : mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
7007 :
7008 : /* set the vmid for the queue */
7009 0 : mqd->cp_hqd_vmid = 0;
7010 :
7011 0 : tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
7012 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
7013 0 : mqd->cp_hqd_persistent_state = tmp;
7014 :
7015 : /* set MIN_IB_AVAIL_SIZE */
7016 0 : tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
7017 0 : tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
7018 0 : mqd->cp_hqd_ib_control = tmp;
7019 :
7020 : /* set static priority for a compute queue/ring */
7021 0 : mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
7022 0 : mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
7023 :
7024 0 : mqd->cp_hqd_active = prop->hqd_active;
7025 :
7026 0 : return 0;
7027 : }
7028 :
7029 0 : static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
7030 : {
7031 0 : struct amdgpu_device *adev = ring->adev;
7032 0 : struct v10_compute_mqd *mqd = ring->mqd_ptr;
7033 : int j;
7034 :
7035 : /* inactivate the queue */
7036 0 : if (amdgpu_sriov_vf(adev))
7037 0 : WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
7038 :
7039 : /* disable wptr polling */
7040 0 : WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
7041 :
7042 : /* disable the queue if it's active */
7043 0 : if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
7044 0 : WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
7045 0 : for (j = 0; j < adev->usec_timeout; j++) {
7046 0 : if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
7047 : break;
7048 0 : udelay(1);
7049 : }
7050 0 : WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
7051 : mqd->cp_hqd_dequeue_request);
7052 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7053 : mqd->cp_hqd_pq_rptr);
7054 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7055 : mqd->cp_hqd_pq_wptr_lo);
7056 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7057 : mqd->cp_hqd_pq_wptr_hi);
7058 : }
7059 :
7060 : /* disable doorbells */
7061 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
7062 :
7063 : /* write the EOP addr */
7064 0 : WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7065 : mqd->cp_hqd_eop_base_addr_lo);
7066 0 : WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7067 : mqd->cp_hqd_eop_base_addr_hi);
7068 :
7069 : /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7070 0 : WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7071 : mqd->cp_hqd_eop_control);
7072 :
7073 : /* set the pointer to the MQD */
7074 0 : WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7075 : mqd->cp_mqd_base_addr_lo);
7076 0 : WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7077 : mqd->cp_mqd_base_addr_hi);
7078 :
7079 : /* set MQD vmid to 0 */
7080 0 : WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7081 : mqd->cp_mqd_control);
7082 :
7083 : /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7084 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7085 : mqd->cp_hqd_pq_base_lo);
7086 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7087 : mqd->cp_hqd_pq_base_hi);
7088 :
7089 : /* set up the HQD, this is similar to CP_RB0_CNTL */
7090 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7091 : mqd->cp_hqd_pq_control);
7092 :
7093 : /* set the wb address whether it's enabled or not */
7094 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7095 : mqd->cp_hqd_pq_rptr_report_addr_lo);
7096 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7097 : mqd->cp_hqd_pq_rptr_report_addr_hi);
7098 :
7099 : /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7100 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7101 : mqd->cp_hqd_pq_wptr_poll_addr_lo);
7102 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7103 : mqd->cp_hqd_pq_wptr_poll_addr_hi);
7104 :
7105 : /* enable the doorbell if requested */
7106 0 : if (ring->use_doorbell) {
7107 0 : WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7108 : (adev->doorbell_index.kiq * 2) << 2);
7109 0 : WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7110 : (adev->doorbell_index.userqueue_end * 2) << 2);
7111 : }
7112 :
7113 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7114 : mqd->cp_hqd_pq_doorbell_control);
7115 :
7116 : /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7117 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7118 : mqd->cp_hqd_pq_wptr_lo);
7119 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7120 : mqd->cp_hqd_pq_wptr_hi);
7121 :
7122 : /* set the vmid for the queue */
7123 0 : WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7124 :
7125 0 : WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7126 : mqd->cp_hqd_persistent_state);
7127 :
7128 : /* activate the queue */
7129 0 : WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7130 : mqd->cp_hqd_active);
7131 :
7132 0 : if (ring->use_doorbell)
7133 0 : WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7134 :
7135 0 : return 0;
7136 : }
7137 :
7138 0 : static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7139 : {
7140 0 : struct amdgpu_device *adev = ring->adev;
7141 0 : struct v10_compute_mqd *mqd = ring->mqd_ptr;
7142 0 : int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7143 :
7144 0 : gfx_v10_0_kiq_setting(ring);
7145 :
7146 0 : if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7147 : /* reset MQD to a clean status */
7148 0 : if (adev->gfx.mec.mqd_backup[mqd_idx])
7149 0 : memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7150 :
7151 : /* reset ring buffer */
7152 0 : ring->wptr = 0;
7153 0 : amdgpu_ring_clear_ring(ring);
7154 :
7155 0 : mutex_lock(&adev->srbm_mutex);
7156 0 : nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7157 0 : gfx_v10_0_kiq_init_register(ring);
7158 0 : nv_grbm_select(adev, 0, 0, 0, 0);
7159 0 : mutex_unlock(&adev->srbm_mutex);
7160 : } else {
7161 0 : memset((void *)mqd, 0, sizeof(*mqd));
7162 0 : mutex_lock(&adev->srbm_mutex);
7163 0 : nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7164 0 : amdgpu_ring_init_mqd(ring);
7165 0 : gfx_v10_0_kiq_init_register(ring);
7166 0 : nv_grbm_select(adev, 0, 0, 0, 0);
7167 0 : mutex_unlock(&adev->srbm_mutex);
7168 :
7169 0 : if (adev->gfx.mec.mqd_backup[mqd_idx])
7170 0 : memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7171 : }
7172 :
7173 0 : return 0;
7174 : }
7175 :
7176 0 : static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7177 : {
7178 0 : struct amdgpu_device *adev = ring->adev;
7179 0 : struct v10_compute_mqd *mqd = ring->mqd_ptr;
7180 0 : int mqd_idx = ring - &adev->gfx.compute_ring[0];
7181 :
7182 0 : if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7183 0 : memset((void *)mqd, 0, sizeof(*mqd));
7184 0 : mutex_lock(&adev->srbm_mutex);
7185 0 : nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7186 0 : amdgpu_ring_init_mqd(ring);
7187 0 : nv_grbm_select(adev, 0, 0, 0, 0);
7188 0 : mutex_unlock(&adev->srbm_mutex);
7189 :
7190 0 : if (adev->gfx.mec.mqd_backup[mqd_idx])
7191 0 : memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7192 0 : } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7193 : /* reset MQD to a clean status */
7194 0 : if (adev->gfx.mec.mqd_backup[mqd_idx])
7195 0 : memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7196 :
7197 : /* reset ring buffer */
7198 0 : ring->wptr = 0;
7199 0 : atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7200 : amdgpu_ring_clear_ring(ring);
7201 : } else {
7202 : amdgpu_ring_clear_ring(ring);
7203 : }
7204 :
7205 0 : return 0;
7206 : }
7207 :
7208 0 : static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7209 : {
7210 : struct amdgpu_ring *ring;
7211 : int r;
7212 :
7213 0 : ring = &adev->gfx.kiq.ring;
7214 :
7215 0 : r = amdgpu_bo_reserve(ring->mqd_obj, false);
7216 0 : if (unlikely(r != 0))
7217 : return r;
7218 :
7219 0 : r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7220 0 : if (unlikely(r != 0))
7221 : return r;
7222 :
7223 0 : gfx_v10_0_kiq_init_queue(ring);
7224 0 : amdgpu_bo_kunmap(ring->mqd_obj);
7225 0 : ring->mqd_ptr = NULL;
7226 0 : amdgpu_bo_unreserve(ring->mqd_obj);
7227 0 : ring->sched.ready = true;
7228 0 : return 0;
7229 : }
7230 :
7231 0 : static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7232 : {
7233 0 : struct amdgpu_ring *ring = NULL;
7234 0 : int r = 0, i;
7235 :
7236 0 : gfx_v10_0_cp_compute_enable(adev, true);
7237 :
7238 0 : for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7239 0 : ring = &adev->gfx.compute_ring[i];
7240 :
7241 0 : r = amdgpu_bo_reserve(ring->mqd_obj, false);
7242 0 : if (unlikely(r != 0))
7243 : goto done;
7244 0 : r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7245 0 : if (!r) {
7246 0 : r = gfx_v10_0_kcq_init_queue(ring);
7247 0 : amdgpu_bo_kunmap(ring->mqd_obj);
7248 0 : ring->mqd_ptr = NULL;
7249 : }
7250 0 : amdgpu_bo_unreserve(ring->mqd_obj);
7251 0 : if (r)
7252 : goto done;
7253 : }
7254 :
7255 0 : r = amdgpu_gfx_enable_kcq(adev);
7256 : done:
7257 0 : return r;
7258 : }
7259 :
7260 0 : static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7261 : {
7262 : int r, i;
7263 : struct amdgpu_ring *ring;
7264 :
7265 0 : if (!(adev->flags & AMD_IS_APU))
7266 0 : gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7267 :
7268 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7269 : /* legacy firmware loading */
7270 0 : r = gfx_v10_0_cp_gfx_load_microcode(adev);
7271 0 : if (r)
7272 : return r;
7273 :
7274 0 : r = gfx_v10_0_cp_compute_load_microcode(adev);
7275 0 : if (r)
7276 : return r;
7277 : }
7278 :
7279 0 : if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
7280 0 : r = amdgpu_mes_kiq_hw_init(adev);
7281 : else
7282 0 : r = gfx_v10_0_kiq_resume(adev);
7283 0 : if (r)
7284 : return r;
7285 :
7286 0 : r = gfx_v10_0_kcq_resume(adev);
7287 0 : if (r)
7288 : return r;
7289 :
7290 0 : if (!amdgpu_async_gfx_ring) {
7291 0 : r = gfx_v10_0_cp_gfx_resume(adev);
7292 0 : if (r)
7293 : return r;
7294 : } else {
7295 0 : r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7296 0 : if (r)
7297 : return r;
7298 : }
7299 :
7300 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7301 0 : ring = &adev->gfx.gfx_ring[i];
7302 0 : r = amdgpu_ring_test_helper(ring);
7303 0 : if (r)
7304 : return r;
7305 : }
7306 :
7307 0 : for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7308 0 : ring = &adev->gfx.compute_ring[i];
7309 0 : r = amdgpu_ring_test_helper(ring);
7310 0 : if (r)
7311 : return r;
7312 : }
7313 :
7314 : return 0;
7315 : }
7316 :
7317 : static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7318 : {
7319 0 : gfx_v10_0_cp_gfx_enable(adev, enable);
7320 0 : gfx_v10_0_cp_compute_enable(adev, enable);
7321 : }
7322 :
7323 0 : static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7324 : {
7325 0 : uint32_t data, pattern = 0xDEADBEEF;
7326 :
7327 : /* check if mmVGT_ESGS_RING_SIZE_UMD
7328 : * has been remapped to mmVGT_ESGS_RING_SIZE */
7329 0 : switch (adev->ip_versions[GC_HWIP][0]) {
7330 : case IP_VERSION(10, 3, 0):
7331 : case IP_VERSION(10, 3, 2):
7332 : case IP_VERSION(10, 3, 4):
7333 : case IP_VERSION(10, 3, 5):
7334 0 : data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7335 0 : WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7336 0 : WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7337 :
7338 0 : if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7339 0 : WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7340 : return true;
7341 : } else {
7342 0 : WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7343 : return false;
7344 : }
7345 : break;
7346 : case IP_VERSION(10, 3, 1):
7347 : case IP_VERSION(10, 3, 3):
7348 : case IP_VERSION(10, 3, 6):
7349 : case IP_VERSION(10, 3, 7):
7350 : return true;
7351 : default:
7352 0 : data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7353 0 : WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7354 0 : WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7355 :
7356 0 : if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7357 0 : WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7358 : return true;
7359 : } else {
7360 0 : WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7361 : return false;
7362 : }
7363 : break;
7364 : }
7365 : }
7366 :
7367 0 : static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7368 : {
7369 : uint32_t data;
7370 :
7371 0 : if (amdgpu_sriov_vf(adev))
7372 : return;
7373 :
7374 : /* initialize cam_index to 0
7375 : * index will auto-inc after each data writting */
7376 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7377 :
7378 0 : switch (adev->ip_versions[GC_HWIP][0]) {
7379 : case IP_VERSION(10, 3, 0):
7380 : case IP_VERSION(10, 3, 2):
7381 : case IP_VERSION(10, 3, 1):
7382 : case IP_VERSION(10, 3, 4):
7383 : case IP_VERSION(10, 3, 5):
7384 : case IP_VERSION(10, 3, 6):
7385 : case IP_VERSION(10, 3, 3):
7386 : case IP_VERSION(10, 3, 7):
7387 : /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7388 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7389 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7390 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7391 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7392 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7393 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7394 :
7395 : /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7396 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7397 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7398 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7399 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7400 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7401 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7402 :
7403 : /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7404 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7405 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7406 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7407 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7408 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7409 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7410 :
7411 : /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7412 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7413 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7414 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7415 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7416 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7417 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7418 :
7419 : /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7420 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7421 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7422 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7423 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7424 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7425 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7426 :
7427 : /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7428 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7429 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7430 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7431 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7432 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7433 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7434 :
7435 : /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7436 0 : data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7437 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7438 0 : (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7439 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7440 0 : break;
7441 : default:
7442 : /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7443 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7444 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7445 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7446 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7447 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7448 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7449 :
7450 : /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7451 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7452 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7453 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7454 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7455 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7456 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7457 :
7458 : /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7459 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7460 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7461 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7462 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7463 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7464 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7465 :
7466 : /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7467 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7468 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7469 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7470 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7471 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7472 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7473 :
7474 : /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7475 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7476 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7477 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7478 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7479 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7480 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7481 :
7482 : /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7483 0 : data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7484 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7485 0 : (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7486 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7487 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7488 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7489 :
7490 : /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7491 0 : data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7492 : GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7493 0 : (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7494 : GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7495 0 : break;
7496 : }
7497 :
7498 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7499 0 : WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7500 : }
7501 :
7502 0 : static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7503 : {
7504 : uint32_t data;
7505 0 : data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7506 0 : data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7507 0 : WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7508 :
7509 0 : data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7510 0 : data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7511 0 : WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7512 0 : }
7513 :
7514 0 : static int gfx_v10_0_hw_init(void *handle)
7515 : {
7516 : int r;
7517 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7518 :
7519 0 : if (!amdgpu_emu_mode)
7520 0 : gfx_v10_0_init_golden_registers(adev);
7521 :
7522 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7523 : /**
7524 : * For gfx 10, rlc firmware loading relies on smu firmware is
7525 : * loaded firstly, so in direct type, it has to load smc ucode
7526 : * here before rlc.
7527 : */
7528 0 : if (!(adev->flags & AMD_IS_APU)) {
7529 0 : r = amdgpu_pm_load_smu_firmware(adev, NULL);
7530 0 : if (r)
7531 : return r;
7532 : }
7533 0 : gfx_v10_0_disable_gpa_mode(adev);
7534 : }
7535 :
7536 : /* if GRBM CAM not remapped, set up the remapping */
7537 0 : if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7538 0 : gfx_v10_0_setup_grbm_cam_remapping(adev);
7539 :
7540 0 : gfx_v10_0_constants_init(adev);
7541 :
7542 0 : r = gfx_v10_0_rlc_resume(adev);
7543 0 : if (r)
7544 : return r;
7545 :
7546 : /*
7547 : * init golden registers and rlc resume may override some registers,
7548 : * reconfig them here
7549 : */
7550 0 : if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
7551 0 : adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
7552 : adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7553 0 : gfx_v10_0_tcp_harvest(adev);
7554 :
7555 0 : r = gfx_v10_0_cp_resume(adev);
7556 0 : if (r)
7557 : return r;
7558 :
7559 0 : if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7560 0 : gfx_v10_3_program_pbb_mode(adev);
7561 :
7562 0 : if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
7563 0 : gfx_v10_3_set_power_brake_sequence(adev);
7564 :
7565 : return r;
7566 : }
7567 :
7568 : #ifndef BRING_UP_DEBUG
7569 0 : static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7570 : {
7571 0 : struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7572 0 : struct amdgpu_ring *kiq_ring = &kiq->ring;
7573 : int i;
7574 :
7575 0 : if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7576 : return -EINVAL;
7577 :
7578 0 : if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7579 0 : adev->gfx.num_gfx_rings))
7580 : return -ENOMEM;
7581 :
7582 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7583 0 : kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7584 : PREEMPT_QUEUES, 0, 0);
7585 0 : if (!adev->job_hang)
7586 0 : return amdgpu_ring_test_helper(kiq_ring);
7587 : else
7588 : return 0;
7589 : }
7590 : #endif
7591 :
7592 0 : static int gfx_v10_0_hw_fini(void *handle)
7593 : {
7594 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7595 : int r;
7596 : uint32_t tmp;
7597 :
7598 0 : amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7599 0 : amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7600 :
7601 0 : if (!adev->no_hw_access) {
7602 : #ifndef BRING_UP_DEBUG
7603 0 : if (amdgpu_async_gfx_ring) {
7604 0 : r = gfx_v10_0_kiq_disable_kgq(adev);
7605 0 : if (r)
7606 0 : DRM_ERROR("KGQ disable failed\n");
7607 : }
7608 : #endif
7609 0 : if (amdgpu_gfx_disable_kcq(adev))
7610 0 : DRM_ERROR("KCQ disable failed\n");
7611 : }
7612 :
7613 0 : if (amdgpu_sriov_vf(adev)) {
7614 0 : gfx_v10_0_cp_gfx_enable(adev, false);
7615 : /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7616 0 : if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
7617 0 : tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7618 0 : tmp &= 0xffffff00;
7619 0 : WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7620 : } else {
7621 0 : tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7622 0 : tmp &= 0xffffff00;
7623 0 : WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7624 : }
7625 :
7626 : return 0;
7627 : }
7628 0 : gfx_v10_0_cp_enable(adev, false);
7629 0 : gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7630 :
7631 0 : return 0;
7632 : }
7633 :
7634 0 : static int gfx_v10_0_suspend(void *handle)
7635 : {
7636 0 : return gfx_v10_0_hw_fini(handle);
7637 : }
7638 :
7639 0 : static int gfx_v10_0_resume(void *handle)
7640 : {
7641 0 : return gfx_v10_0_hw_init(handle);
7642 : }
7643 :
7644 0 : static bool gfx_v10_0_is_idle(void *handle)
7645 : {
7646 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7647 :
7648 0 : if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7649 : GRBM_STATUS, GUI_ACTIVE))
7650 : return false;
7651 : else
7652 0 : return true;
7653 : }
7654 :
7655 0 : static int gfx_v10_0_wait_for_idle(void *handle)
7656 : {
7657 : unsigned i;
7658 : u32 tmp;
7659 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7660 :
7661 0 : for (i = 0; i < adev->usec_timeout; i++) {
7662 : /* read MC_STATUS */
7663 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7664 : GRBM_STATUS__GUI_ACTIVE_MASK;
7665 :
7666 0 : if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7667 : return 0;
7668 0 : udelay(1);
7669 : }
7670 : return -ETIMEDOUT;
7671 : }
7672 :
7673 0 : static int gfx_v10_0_soft_reset(void *handle)
7674 : {
7675 0 : u32 grbm_soft_reset = 0;
7676 : u32 tmp;
7677 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7678 :
7679 : /* GRBM_STATUS */
7680 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7681 0 : if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7682 : GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7683 : GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7684 : GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7685 : GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7686 0 : grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7687 : GRBM_SOFT_RESET, SOFT_RESET_CP,
7688 : 1);
7689 0 : grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7690 : GRBM_SOFT_RESET, SOFT_RESET_GFX,
7691 : 1);
7692 : }
7693 :
7694 0 : if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7695 0 : grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7696 : GRBM_SOFT_RESET, SOFT_RESET_CP,
7697 : 1);
7698 : }
7699 :
7700 : /* GRBM_STATUS2 */
7701 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7702 0 : switch (adev->ip_versions[GC_HWIP][0]) {
7703 : case IP_VERSION(10, 3, 0):
7704 : case IP_VERSION(10, 3, 2):
7705 : case IP_VERSION(10, 3, 1):
7706 : case IP_VERSION(10, 3, 4):
7707 : case IP_VERSION(10, 3, 5):
7708 : case IP_VERSION(10, 3, 6):
7709 : case IP_VERSION(10, 3, 3):
7710 0 : if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7711 0 : grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7712 : GRBM_SOFT_RESET,
7713 : SOFT_RESET_RLC,
7714 : 1);
7715 : break;
7716 : default:
7717 0 : if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7718 0 : grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7719 : GRBM_SOFT_RESET,
7720 : SOFT_RESET_RLC,
7721 : 1);
7722 : break;
7723 : }
7724 :
7725 0 : if (grbm_soft_reset) {
7726 : /* stop the rlc */
7727 0 : gfx_v10_0_rlc_stop(adev);
7728 :
7729 : /* Disable GFX parsing/prefetching */
7730 0 : gfx_v10_0_cp_gfx_enable(adev, false);
7731 :
7732 : /* Disable MEC parsing/prefetching */
7733 0 : gfx_v10_0_cp_compute_enable(adev, false);
7734 :
7735 : if (grbm_soft_reset) {
7736 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7737 0 : tmp |= grbm_soft_reset;
7738 0 : dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7739 0 : WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7740 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7741 :
7742 0 : udelay(50);
7743 :
7744 0 : tmp &= ~grbm_soft_reset;
7745 0 : WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7746 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7747 : }
7748 :
7749 : /* Wait a little for things to settle down */
7750 : udelay(50);
7751 : }
7752 0 : return 0;
7753 : }
7754 :
7755 0 : static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7756 : {
7757 : uint64_t clock, clock_lo, clock_hi, hi_check;
7758 :
7759 0 : switch (adev->ip_versions[GC_HWIP][0]) {
7760 : case IP_VERSION(10, 3, 1):
7761 : case IP_VERSION(10, 3, 3):
7762 : case IP_VERSION(10, 3, 7):
7763 0 : preempt_disable();
7764 0 : clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7765 0 : clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7766 0 : hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7767 : /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7768 : * roughly every 42 seconds.
7769 : */
7770 0 : if (hi_check != clock_hi) {
7771 0 : clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7772 : clock_hi = hi_check;
7773 : }
7774 0 : preempt_enable();
7775 0 : clock = clock_lo | (clock_hi << 32ULL);
7776 0 : break;
7777 : case IP_VERSION(10, 3, 6):
7778 0 : preempt_disable();
7779 0 : clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7780 0 : clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7781 0 : hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7782 : /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7783 : * roughly every 42 seconds.
7784 : */
7785 0 : if (hi_check != clock_hi) {
7786 0 : clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7787 : clock_hi = hi_check;
7788 : }
7789 0 : preempt_enable();
7790 0 : clock = clock_lo | (clock_hi << 32ULL);
7791 0 : break;
7792 : default:
7793 0 : preempt_disable();
7794 0 : clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7795 0 : clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7796 0 : hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7797 : /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7798 : * roughly every 42 seconds.
7799 : */
7800 0 : if (hi_check != clock_hi) {
7801 0 : clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7802 : clock_hi = hi_check;
7803 : }
7804 0 : preempt_enable();
7805 0 : clock = clock_lo | (clock_hi << 32ULL);
7806 0 : break;
7807 : }
7808 0 : return clock;
7809 : }
7810 :
7811 0 : static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7812 : uint32_t vmid,
7813 : uint32_t gds_base, uint32_t gds_size,
7814 : uint32_t gws_base, uint32_t gws_size,
7815 : uint32_t oa_base, uint32_t oa_size)
7816 : {
7817 0 : struct amdgpu_device *adev = ring->adev;
7818 :
7819 : /* GDS Base */
7820 0 : gfx_v10_0_write_data_to_reg(ring, 0, false,
7821 0 : SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7822 : gds_base);
7823 :
7824 : /* GDS Size */
7825 0 : gfx_v10_0_write_data_to_reg(ring, 0, false,
7826 0 : SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7827 : gds_size);
7828 :
7829 : /* GWS */
7830 0 : gfx_v10_0_write_data_to_reg(ring, 0, false,
7831 0 : SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7832 0 : gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7833 :
7834 : /* OA */
7835 0 : gfx_v10_0_write_data_to_reg(ring, 0, false,
7836 0 : SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7837 0 : (1 << (oa_size + oa_base)) - (1 << oa_base));
7838 0 : }
7839 :
7840 0 : static int gfx_v10_0_early_init(void *handle)
7841 : {
7842 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7843 :
7844 0 : switch (adev->ip_versions[GC_HWIP][0]) {
7845 : case IP_VERSION(10, 1, 10):
7846 : case IP_VERSION(10, 1, 1):
7847 : case IP_VERSION(10, 1, 2):
7848 : case IP_VERSION(10, 1, 3):
7849 : case IP_VERSION(10, 1, 4):
7850 0 : adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7851 0 : break;
7852 : case IP_VERSION(10, 3, 0):
7853 : case IP_VERSION(10, 3, 2):
7854 : case IP_VERSION(10, 3, 1):
7855 : case IP_VERSION(10, 3, 4):
7856 : case IP_VERSION(10, 3, 5):
7857 : case IP_VERSION(10, 3, 6):
7858 : case IP_VERSION(10, 3, 3):
7859 : case IP_VERSION(10, 3, 7):
7860 0 : adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7861 0 : break;
7862 : default:
7863 : break;
7864 : }
7865 :
7866 0 : adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7867 : AMDGPU_MAX_COMPUTE_RINGS);
7868 :
7869 0 : gfx_v10_0_set_kiq_pm4_funcs(adev);
7870 0 : gfx_v10_0_set_ring_funcs(adev);
7871 0 : gfx_v10_0_set_irq_funcs(adev);
7872 0 : gfx_v10_0_set_gds_init(adev);
7873 0 : gfx_v10_0_set_rlc_funcs(adev);
7874 0 : gfx_v10_0_set_mqd_funcs(adev);
7875 :
7876 : /* init rlcg reg access ctrl */
7877 0 : gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7878 :
7879 0 : return 0;
7880 : }
7881 :
7882 0 : static int gfx_v10_0_late_init(void *handle)
7883 : {
7884 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7885 : int r;
7886 :
7887 0 : r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7888 0 : if (r)
7889 : return r;
7890 :
7891 0 : r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7892 0 : if (r)
7893 : return r;
7894 :
7895 0 : return 0;
7896 : }
7897 :
7898 0 : static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7899 : {
7900 : uint32_t rlc_cntl;
7901 :
7902 : /* if RLC is not enabled, do nothing */
7903 0 : rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7904 0 : return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7905 : }
7906 :
7907 0 : static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7908 : {
7909 : uint32_t data;
7910 : unsigned i;
7911 :
7912 0 : data = RLC_SAFE_MODE__CMD_MASK;
7913 0 : data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7914 :
7915 0 : switch (adev->ip_versions[GC_HWIP][0]) {
7916 : case IP_VERSION(10, 3, 0):
7917 : case IP_VERSION(10, 3, 2):
7918 : case IP_VERSION(10, 3, 1):
7919 : case IP_VERSION(10, 3, 4):
7920 : case IP_VERSION(10, 3, 5):
7921 : case IP_VERSION(10, 3, 6):
7922 : case IP_VERSION(10, 3, 3):
7923 : case IP_VERSION(10, 3, 7):
7924 0 : WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7925 :
7926 : /* wait for RLC_SAFE_MODE */
7927 0 : for (i = 0; i < adev->usec_timeout; i++) {
7928 0 : if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7929 : RLC_SAFE_MODE, CMD))
7930 : break;
7931 0 : udelay(1);
7932 : }
7933 : break;
7934 : default:
7935 0 : WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7936 :
7937 : /* wait for RLC_SAFE_MODE */
7938 0 : for (i = 0; i < adev->usec_timeout; i++) {
7939 0 : if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7940 : RLC_SAFE_MODE, CMD))
7941 : break;
7942 0 : udelay(1);
7943 : }
7944 : break;
7945 : }
7946 0 : }
7947 :
7948 0 : static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7949 : {
7950 : uint32_t data;
7951 :
7952 0 : data = RLC_SAFE_MODE__CMD_MASK;
7953 0 : switch (adev->ip_versions[GC_HWIP][0]) {
7954 : case IP_VERSION(10, 3, 0):
7955 : case IP_VERSION(10, 3, 2):
7956 : case IP_VERSION(10, 3, 1):
7957 : case IP_VERSION(10, 3, 4):
7958 : case IP_VERSION(10, 3, 5):
7959 : case IP_VERSION(10, 3, 6):
7960 : case IP_VERSION(10, 3, 3):
7961 : case IP_VERSION(10, 3, 7):
7962 0 : WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7963 : break;
7964 : default:
7965 0 : WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7966 : break;
7967 : }
7968 0 : }
7969 :
7970 0 : static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7971 : bool enable)
7972 : {
7973 : uint32_t data, def;
7974 :
7975 0 : if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7976 : return;
7977 :
7978 : /* It is disabled by HW by default */
7979 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7980 : /* 0 - Disable some blocks' MGCG */
7981 0 : WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7982 0 : WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7983 0 : WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7984 0 : WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7985 :
7986 : /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7987 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7988 0 : data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7989 : RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7990 : RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7991 : RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7992 : RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7993 : RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7994 :
7995 0 : if (def != data)
7996 0 : WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7997 :
7998 : /* MGLS is a global flag to control all MGLS in GFX */
7999 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
8000 : /* 2 - RLC memory Light sleep */
8001 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
8002 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
8003 0 : data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
8004 0 : if (def != data)
8005 0 : WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
8006 : }
8007 : /* 3 - CP memory Light sleep */
8008 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
8009 0 : def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
8010 0 : data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
8011 0 : if (def != data)
8012 0 : WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
8013 : }
8014 : }
8015 0 : } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
8016 : /* 1 - MGCG_OVERRIDE */
8017 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8018 0 : data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
8019 : RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
8020 : RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
8021 : RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
8022 : RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
8023 : RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
8024 0 : if (def != data)
8025 0 : WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8026 :
8027 : /* 2 - disable MGLS in CP */
8028 0 : data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
8029 0 : if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
8030 0 : data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
8031 0 : WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
8032 : }
8033 :
8034 : /* 3 - disable MGLS in RLC */
8035 0 : data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
8036 0 : if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
8037 0 : data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
8038 0 : WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
8039 : }
8040 :
8041 : }
8042 : }
8043 :
8044 0 : static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
8045 : bool enable)
8046 : {
8047 : uint32_t data, def;
8048 :
8049 0 : if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
8050 : return;
8051 :
8052 : /* Enable 3D CGCG/CGLS */
8053 0 : if (enable) {
8054 : /* write cmd to clear cgcg/cgls ov */
8055 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8056 :
8057 : /* unset CGCG override */
8058 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8059 0 : data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
8060 :
8061 : /* update CGCG and CGLS override bits */
8062 0 : if (def != data)
8063 0 : WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8064 :
8065 : /* enable 3Dcgcg FSM(0x0000363f) */
8066 0 : def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8067 0 : data = 0;
8068 :
8069 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8070 0 : data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8071 : RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8072 :
8073 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8074 0 : data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8075 : RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8076 :
8077 0 : if (def != data)
8078 0 : WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8079 :
8080 : /* set IDLE_POLL_COUNT(0x00900100) */
8081 0 : def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8082 0 : data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8083 : (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8084 0 : if (def != data)
8085 0 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8086 : } else {
8087 : /* Disable CGCG/CGLS */
8088 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8089 :
8090 : /* disable cgcg, cgls should be disabled */
8091 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8092 0 : data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8093 :
8094 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8095 0 : data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8096 :
8097 : /* disable cgcg and cgls in FSM */
8098 0 : if (def != data)
8099 0 : WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8100 : }
8101 : }
8102 :
8103 0 : static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8104 : bool enable)
8105 : {
8106 : uint32_t def, data;
8107 :
8108 0 : if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8109 : return;
8110 :
8111 0 : if (enable) {
8112 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8113 :
8114 : /* unset CGCG override */
8115 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8116 0 : data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8117 :
8118 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8119 0 : data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8120 :
8121 : /* update CGCG and CGLS override bits */
8122 0 : if (def != data)
8123 0 : WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8124 :
8125 : /* enable cgcg FSM(0x0000363F) */
8126 0 : def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8127 0 : data = 0;
8128 :
8129 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8130 0 : data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8131 : RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8132 :
8133 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8134 0 : data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8135 : RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8136 :
8137 0 : if (def != data)
8138 0 : WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8139 :
8140 : /* set IDLE_POLL_COUNT(0x00900100) */
8141 0 : def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8142 0 : data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8143 : (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8144 0 : if (def != data)
8145 0 : WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8146 : } else {
8147 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8148 :
8149 : /* reset CGCG/CGLS bits */
8150 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8151 0 : data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8152 :
8153 0 : if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8154 0 : data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8155 :
8156 : /* disable cgcg and cgls in FSM */
8157 0 : if (def != data)
8158 0 : WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8159 : }
8160 : }
8161 :
8162 0 : static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8163 : bool enable)
8164 : {
8165 : uint32_t def, data;
8166 :
8167 0 : if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8168 : return;
8169 :
8170 0 : if (enable) {
8171 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8172 : /* unset FGCG override */
8173 0 : data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8174 : /* update FGCG override bits */
8175 0 : if (def != data)
8176 0 : WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8177 :
8178 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8179 : /* unset RLC SRAM CLK GATER override */
8180 0 : data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8181 : /* update RLC SRAM CLK GATER override bits */
8182 0 : if (def != data)
8183 0 : WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8184 : } else {
8185 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8186 : /* reset FGCG bits */
8187 0 : data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8188 : /* disable FGCG*/
8189 0 : if (def != data)
8190 0 : WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8191 :
8192 0 : def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8193 : /* reset RLC SRAM CLK GATER bits */
8194 0 : data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8195 : /* disable RLC SRAM CLK*/
8196 0 : if (def != data)
8197 0 : WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8198 : }
8199 : }
8200 :
8201 0 : static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8202 : {
8203 0 : uint32_t reg_data = 0;
8204 0 : uint32_t reg_idx = 0;
8205 : uint32_t i;
8206 :
8207 0 : const uint32_t tcp_ctrl_regs[] = {
8208 : mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8209 : mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8210 : mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8211 : mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8212 : mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8213 : mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8214 : mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8215 : mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8216 : mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8217 : mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8218 : mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8219 : mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8220 : mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8221 : mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8222 : mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8223 : mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8224 : mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8225 : mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8226 : mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8227 : mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8228 : mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8229 : mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8230 : mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8231 : mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8232 : };
8233 :
8234 0 : const uint32_t tcp_ctrl_regs_nv12[] = {
8235 : mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8236 : mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8237 : mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8238 : mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8239 : mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8240 : mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8241 : mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8242 : mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8243 : mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8244 : mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8245 : mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8246 : mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8247 : mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8248 : mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8249 : mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8250 : mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8251 : mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8252 : mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8253 : mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8254 : mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8255 : };
8256 :
8257 0 : const uint32_t sm_ctlr_regs[] = {
8258 : mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8259 : mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8260 : mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8261 : mmCGTS_SA1_QUAD1_SM_CTRL_REG
8262 : };
8263 :
8264 0 : if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
8265 0 : for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8266 0 : reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8267 0 : tcp_ctrl_regs_nv12[i];
8268 0 : reg_data = RREG32(reg_idx);
8269 0 : reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8270 0 : WREG32(reg_idx, reg_data);
8271 : }
8272 : } else {
8273 0 : for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8274 0 : reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8275 0 : tcp_ctrl_regs[i];
8276 0 : reg_data = RREG32(reg_idx);
8277 0 : reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8278 0 : WREG32(reg_idx, reg_data);
8279 : }
8280 : }
8281 :
8282 0 : for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8283 0 : reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8284 0 : sm_ctlr_regs[i];
8285 0 : reg_data = RREG32(reg_idx);
8286 0 : reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8287 0 : reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8288 0 : WREG32(reg_idx, reg_data);
8289 : }
8290 0 : }
8291 :
8292 0 : static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8293 : bool enable)
8294 : {
8295 0 : amdgpu_gfx_rlc_enter_safe_mode(adev);
8296 :
8297 0 : if (enable) {
8298 : /* enable FGCG firstly*/
8299 0 : gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8300 : /* CGCG/CGLS should be enabled after MGCG/MGLS
8301 : * === MGCG + MGLS ===
8302 : */
8303 0 : gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8304 : /* === CGCG /CGLS for GFX 3D Only === */
8305 0 : gfx_v10_0_update_3d_clock_gating(adev, enable);
8306 : /* === CGCG + CGLS === */
8307 0 : gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8308 :
8309 0 : if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
8310 0 : (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
8311 : (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
8312 0 : gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8313 : } else {
8314 : /* CGCG/CGLS should be disabled before MGCG/MGLS
8315 : * === CGCG + CGLS ===
8316 : */
8317 0 : gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8318 : /* === CGCG /CGLS for GFX 3D Only === */
8319 0 : gfx_v10_0_update_3d_clock_gating(adev, enable);
8320 : /* === MGCG + MGLS === */
8321 0 : gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8322 : /* disable fgcg at last*/
8323 0 : gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8324 : }
8325 :
8326 0 : if (adev->cg_flags &
8327 : (AMD_CG_SUPPORT_GFX_MGCG |
8328 : AMD_CG_SUPPORT_GFX_CGLS |
8329 : AMD_CG_SUPPORT_GFX_CGCG |
8330 : AMD_CG_SUPPORT_GFX_3D_CGCG |
8331 : AMD_CG_SUPPORT_GFX_3D_CGLS))
8332 0 : gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8333 :
8334 0 : amdgpu_gfx_rlc_exit_safe_mode(adev);
8335 :
8336 0 : return 0;
8337 : }
8338 :
8339 0 : static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8340 : {
8341 : u32 reg, data;
8342 :
8343 0 : amdgpu_gfx_off_ctrl(adev, false);
8344 :
8345 : /* not for *_SOC15 */
8346 0 : reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8347 0 : if (amdgpu_sriov_is_pp_one_vf(adev))
8348 0 : data = RREG32_NO_KIQ(reg);
8349 : else
8350 0 : data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8351 :
8352 0 : data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8353 0 : data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8354 :
8355 0 : if (amdgpu_sriov_is_pp_one_vf(adev))
8356 0 : WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8357 : else
8358 0 : WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8359 :
8360 0 : amdgpu_gfx_off_ctrl(adev, true);
8361 0 : }
8362 :
8363 : static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8364 : uint32_t offset,
8365 : struct soc15_reg_rlcg *entries, int arr_size)
8366 : {
8367 : int i;
8368 : uint32_t reg;
8369 :
8370 : if (!entries)
8371 : return false;
8372 :
8373 : for (i = 0; i < arr_size; i++) {
8374 : const struct soc15_reg_rlcg *entry;
8375 :
8376 : entry = &entries[i];
8377 : reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8378 : if (offset == reg)
8379 : return true;
8380 : }
8381 :
8382 : return false;
8383 : }
8384 :
8385 0 : static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8386 : {
8387 0 : return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8388 : }
8389 :
8390 0 : static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8391 : {
8392 0 : u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8393 :
8394 0 : if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8395 0 : data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8396 : else
8397 0 : data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8398 :
8399 0 : WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8400 :
8401 : /*
8402 : * CGPG enablement required and the register to program the hysteresis value
8403 : * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8404 : * in refclk count. Note that RLC FW is modified to take 16 bits from
8405 : * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8406 : *
8407 : * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8408 : * of CGPG enablement starting point.
8409 : * Power/performance team will optimize it and might give a new value later.
8410 : */
8411 0 : if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8412 0 : switch (adev->ip_versions[GC_HWIP][0]) {
8413 : case IP_VERSION(10, 3, 1):
8414 : case IP_VERSION(10, 3, 3):
8415 : case IP_VERSION(10, 3, 6):
8416 : case IP_VERSION(10, 3, 7):
8417 0 : data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8418 0 : WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8419 : break;
8420 : default:
8421 : break;
8422 : }
8423 : }
8424 0 : }
8425 :
8426 0 : static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8427 : {
8428 0 : amdgpu_gfx_rlc_enter_safe_mode(adev);
8429 :
8430 0 : gfx_v10_cntl_power_gating(adev, enable);
8431 :
8432 0 : amdgpu_gfx_rlc_exit_safe_mode(adev);
8433 0 : }
8434 :
8435 : static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8436 : .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8437 : .set_safe_mode = gfx_v10_0_set_safe_mode,
8438 : .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8439 : .init = gfx_v10_0_rlc_init,
8440 : .get_csb_size = gfx_v10_0_get_csb_size,
8441 : .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8442 : .resume = gfx_v10_0_rlc_resume,
8443 : .stop = gfx_v10_0_rlc_stop,
8444 : .reset = gfx_v10_0_rlc_reset,
8445 : .start = gfx_v10_0_rlc_start,
8446 : .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8447 : };
8448 :
8449 : static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8450 : .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8451 : .set_safe_mode = gfx_v10_0_set_safe_mode,
8452 : .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8453 : .init = gfx_v10_0_rlc_init,
8454 : .get_csb_size = gfx_v10_0_get_csb_size,
8455 : .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8456 : .resume = gfx_v10_0_rlc_resume,
8457 : .stop = gfx_v10_0_rlc_stop,
8458 : .reset = gfx_v10_0_rlc_reset,
8459 : .start = gfx_v10_0_rlc_start,
8460 : .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8461 : .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8462 : };
8463 :
8464 0 : static int gfx_v10_0_set_powergating_state(void *handle,
8465 : enum amd_powergating_state state)
8466 : {
8467 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8468 0 : bool enable = (state == AMD_PG_STATE_GATE);
8469 :
8470 0 : if (amdgpu_sriov_vf(adev))
8471 : return 0;
8472 :
8473 0 : switch (adev->ip_versions[GC_HWIP][0]) {
8474 : case IP_VERSION(10, 1, 10):
8475 : case IP_VERSION(10, 1, 1):
8476 : case IP_VERSION(10, 1, 2):
8477 : case IP_VERSION(10, 3, 0):
8478 : case IP_VERSION(10, 3, 2):
8479 : case IP_VERSION(10, 3, 4):
8480 : case IP_VERSION(10, 3, 5):
8481 0 : amdgpu_gfx_off_ctrl(adev, enable);
8482 0 : break;
8483 : case IP_VERSION(10, 3, 1):
8484 : case IP_VERSION(10, 3, 3):
8485 : case IP_VERSION(10, 3, 6):
8486 : case IP_VERSION(10, 3, 7):
8487 0 : gfx_v10_cntl_pg(adev, enable);
8488 0 : amdgpu_gfx_off_ctrl(adev, enable);
8489 0 : break;
8490 : default:
8491 : break;
8492 : }
8493 : return 0;
8494 : }
8495 :
8496 0 : static int gfx_v10_0_set_clockgating_state(void *handle,
8497 : enum amd_clockgating_state state)
8498 : {
8499 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8500 :
8501 0 : if (amdgpu_sriov_vf(adev))
8502 : return 0;
8503 :
8504 0 : switch (adev->ip_versions[GC_HWIP][0]) {
8505 : case IP_VERSION(10, 1, 10):
8506 : case IP_VERSION(10, 1, 1):
8507 : case IP_VERSION(10, 1, 2):
8508 : case IP_VERSION(10, 3, 0):
8509 : case IP_VERSION(10, 3, 2):
8510 : case IP_VERSION(10, 3, 1):
8511 : case IP_VERSION(10, 3, 4):
8512 : case IP_VERSION(10, 3, 5):
8513 : case IP_VERSION(10, 3, 6):
8514 : case IP_VERSION(10, 3, 3):
8515 : case IP_VERSION(10, 3, 7):
8516 0 : gfx_v10_0_update_gfx_clock_gating(adev,
8517 : state == AMD_CG_STATE_GATE);
8518 0 : break;
8519 : default:
8520 : break;
8521 : }
8522 : return 0;
8523 : }
8524 :
8525 0 : static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8526 : {
8527 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8528 : int data;
8529 :
8530 : /* AMD_CG_SUPPORT_GFX_FGCG */
8531 0 : data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8532 0 : if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8533 0 : *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8534 :
8535 : /* AMD_CG_SUPPORT_GFX_MGCG */
8536 0 : data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8537 0 : if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8538 0 : *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8539 :
8540 : /* AMD_CG_SUPPORT_GFX_CGCG */
8541 0 : data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8542 0 : if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8543 0 : *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8544 :
8545 : /* AMD_CG_SUPPORT_GFX_CGLS */
8546 0 : if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8547 0 : *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8548 :
8549 : /* AMD_CG_SUPPORT_GFX_RLC_LS */
8550 0 : data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8551 0 : if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8552 0 : *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8553 :
8554 : /* AMD_CG_SUPPORT_GFX_CP_LS */
8555 0 : data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8556 0 : if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8557 0 : *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8558 :
8559 : /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8560 0 : data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8561 0 : if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8562 0 : *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8563 :
8564 : /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8565 0 : if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8566 0 : *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8567 0 : }
8568 :
8569 0 : static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8570 : {
8571 : /* gfx10 is 32bit rptr*/
8572 0 : return *(uint32_t *)ring->rptr_cpu_addr;
8573 : }
8574 :
8575 0 : static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8576 : {
8577 0 : struct amdgpu_device *adev = ring->adev;
8578 : u64 wptr;
8579 :
8580 : /* XXX check if swapping is necessary on BE */
8581 0 : if (ring->use_doorbell) {
8582 0 : wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8583 : } else {
8584 0 : wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8585 0 : wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8586 : }
8587 :
8588 0 : return wptr;
8589 : }
8590 :
8591 0 : static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8592 : {
8593 0 : struct amdgpu_device *adev = ring->adev;
8594 : uint32_t *wptr_saved;
8595 : uint32_t *is_queue_unmap;
8596 : uint64_t aggregated_db_index;
8597 0 : uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
8598 : uint64_t wptr_tmp;
8599 :
8600 0 : if (ring->is_mes_queue) {
8601 0 : wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8602 0 : is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8603 : sizeof(uint32_t));
8604 0 : aggregated_db_index =
8605 0 : amdgpu_mes_get_aggregated_doorbell_index(adev,
8606 : AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8607 :
8608 0 : wptr_tmp = ring->wptr & ring->buf_mask;
8609 0 : atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8610 0 : *wptr_saved = wptr_tmp;
8611 : /* assume doorbell always being used by mes mapped queue */
8612 0 : if (*is_queue_unmap) {
8613 0 : WDOORBELL64(aggregated_db_index, wptr_tmp);
8614 0 : WDOORBELL64(ring->doorbell_index, wptr_tmp);
8615 : } else {
8616 0 : WDOORBELL64(ring->doorbell_index, wptr_tmp);
8617 :
8618 0 : if (*is_queue_unmap)
8619 0 : WDOORBELL64(aggregated_db_index, wptr_tmp);
8620 : }
8621 : } else {
8622 0 : if (ring->use_doorbell) {
8623 : /* XXX check if swapping is necessary on BE */
8624 0 : atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8625 0 : ring->wptr);
8626 0 : WDOORBELL64(ring->doorbell_index, ring->wptr);
8627 : } else {
8628 0 : WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8629 : lower_32_bits(ring->wptr));
8630 0 : WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8631 : upper_32_bits(ring->wptr));
8632 : }
8633 : }
8634 0 : }
8635 :
8636 0 : static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8637 : {
8638 : /* gfx10 hardware is 32bit rptr */
8639 0 : return *(uint32_t *)ring->rptr_cpu_addr;
8640 : }
8641 :
8642 0 : static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8643 : {
8644 : u64 wptr;
8645 :
8646 : /* XXX check if swapping is necessary on BE */
8647 0 : if (ring->use_doorbell)
8648 0 : wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8649 : else
8650 0 : BUG();
8651 0 : return wptr;
8652 : }
8653 :
8654 0 : static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8655 : {
8656 0 : struct amdgpu_device *adev = ring->adev;
8657 : uint32_t *wptr_saved;
8658 : uint32_t *is_queue_unmap;
8659 : uint64_t aggregated_db_index;
8660 0 : uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
8661 : uint64_t wptr_tmp;
8662 :
8663 0 : if (ring->is_mes_queue) {
8664 0 : wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8665 0 : is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8666 : sizeof(uint32_t));
8667 0 : aggregated_db_index =
8668 0 : amdgpu_mes_get_aggregated_doorbell_index(adev,
8669 : AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8670 :
8671 0 : wptr_tmp = ring->wptr & ring->buf_mask;
8672 0 : atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8673 0 : *wptr_saved = wptr_tmp;
8674 : /* assume doorbell always used by mes mapped queue */
8675 0 : if (*is_queue_unmap) {
8676 0 : WDOORBELL64(aggregated_db_index, wptr_tmp);
8677 0 : WDOORBELL64(ring->doorbell_index, wptr_tmp);
8678 : } else {
8679 0 : WDOORBELL64(ring->doorbell_index, wptr_tmp);
8680 :
8681 0 : if (*is_queue_unmap)
8682 0 : WDOORBELL64(aggregated_db_index, wptr_tmp);
8683 : }
8684 : } else {
8685 : /* XXX check if swapping is necessary on BE */
8686 0 : if (ring->use_doorbell) {
8687 0 : atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8688 0 : ring->wptr);
8689 0 : WDOORBELL64(ring->doorbell_index, ring->wptr);
8690 : } else {
8691 0 : BUG(); /* only DOORBELL method supported on gfx10 now */
8692 : }
8693 : }
8694 0 : }
8695 :
8696 0 : static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8697 : {
8698 0 : struct amdgpu_device *adev = ring->adev;
8699 : u32 ref_and_mask, reg_mem_engine;
8700 0 : const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8701 :
8702 0 : if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8703 0 : switch (ring->me) {
8704 : case 1:
8705 0 : ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8706 0 : break;
8707 : case 2:
8708 0 : ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8709 0 : break;
8710 : default:
8711 : return;
8712 : }
8713 : reg_mem_engine = 0;
8714 : } else {
8715 0 : ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8716 0 : reg_mem_engine = 1; /* pfp */
8717 : }
8718 :
8719 0 : gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8720 0 : adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8721 0 : adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8722 : ref_and_mask, ref_and_mask, 0x20);
8723 : }
8724 :
8725 0 : static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8726 : struct amdgpu_job *job,
8727 : struct amdgpu_ib *ib,
8728 : uint32_t flags)
8729 : {
8730 0 : unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8731 0 : u32 header, control = 0;
8732 :
8733 0 : if (ib->flags & AMDGPU_IB_FLAG_CE)
8734 : header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8735 : else
8736 0 : header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8737 :
8738 0 : control |= ib->length_dw | (vmid << 24);
8739 :
8740 0 : if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8741 0 : control |= INDIRECT_BUFFER_PRE_ENB(1);
8742 :
8743 0 : if (flags & AMDGPU_IB_PREEMPTED)
8744 0 : control |= INDIRECT_BUFFER_PRE_RESUME(1);
8745 :
8746 0 : if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8747 0 : gfx_v10_0_ring_emit_de_meta(ring,
8748 0 : (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8749 : }
8750 :
8751 0 : if (ring->is_mes_queue)
8752 : /* inherit vmid from mqd */
8753 0 : control |= 0x400000;
8754 :
8755 0 : amdgpu_ring_write(ring, header);
8756 0 : BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8757 0 : amdgpu_ring_write(ring,
8758 : #ifdef __BIG_ENDIAN
8759 : (2 << 0) |
8760 : #endif
8761 : lower_32_bits(ib->gpu_addr));
8762 0 : amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8763 0 : amdgpu_ring_write(ring, control);
8764 0 : }
8765 :
8766 0 : static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8767 : struct amdgpu_job *job,
8768 : struct amdgpu_ib *ib,
8769 : uint32_t flags)
8770 : {
8771 0 : unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8772 0 : u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8773 :
8774 0 : if (ring->is_mes_queue)
8775 : /* inherit vmid from mqd */
8776 0 : control |= 0x40000000;
8777 :
8778 : /* Currently, there is a high possibility to get wave ID mismatch
8779 : * between ME and GDS, leading to a hw deadlock, because ME generates
8780 : * different wave IDs than the GDS expects. This situation happens
8781 : * randomly when at least 5 compute pipes use GDS ordered append.
8782 : * The wave IDs generated by ME are also wrong after suspend/resume.
8783 : * Those are probably bugs somewhere else in the kernel driver.
8784 : *
8785 : * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8786 : * GDS to 0 for this ring (me/pipe).
8787 : */
8788 0 : if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8789 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8790 0 : amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8791 0 : amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8792 : }
8793 :
8794 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8795 0 : BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8796 0 : amdgpu_ring_write(ring,
8797 : #ifdef __BIG_ENDIAN
8798 : (2 << 0) |
8799 : #endif
8800 : lower_32_bits(ib->gpu_addr));
8801 0 : amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8802 0 : amdgpu_ring_write(ring, control);
8803 0 : }
8804 :
8805 0 : static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8806 : u64 seq, unsigned flags)
8807 : {
8808 0 : bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8809 0 : bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8810 :
8811 : /* RELEASE_MEM - flush caches, send int */
8812 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8813 0 : amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8814 : PACKET3_RELEASE_MEM_GCR_GL2_WB |
8815 : PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8816 : PACKET3_RELEASE_MEM_GCR_GLM_WB |
8817 : PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8818 : PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8819 : PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8820 0 : amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8821 0 : PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8822 :
8823 : /*
8824 : * the address should be Qword aligned if 64bit write, Dword
8825 : * aligned if only send 32bit data low (discard data high)
8826 : */
8827 0 : if (write64bit)
8828 0 : BUG_ON(addr & 0x7);
8829 : else
8830 0 : BUG_ON(addr & 0x3);
8831 0 : amdgpu_ring_write(ring, lower_32_bits(addr));
8832 0 : amdgpu_ring_write(ring, upper_32_bits(addr));
8833 0 : amdgpu_ring_write(ring, lower_32_bits(seq));
8834 0 : amdgpu_ring_write(ring, upper_32_bits(seq));
8835 0 : amdgpu_ring_write(ring, ring->is_mes_queue ?
8836 0 : (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8837 0 : }
8838 :
8839 0 : static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8840 : {
8841 0 : int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8842 0 : uint32_t seq = ring->fence_drv.sync_seq;
8843 0 : uint64_t addr = ring->fence_drv.gpu_addr;
8844 :
8845 0 : gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8846 0 : upper_32_bits(addr), seq, 0xffffffff, 4);
8847 0 : }
8848 :
8849 0 : static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8850 : uint16_t pasid, uint32_t flush_type,
8851 : bool all_hub, uint8_t dst_sel)
8852 : {
8853 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8854 0 : amdgpu_ring_write(ring,
8855 0 : PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8856 0 : PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8857 0 : PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8858 0 : PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8859 0 : }
8860 :
8861 0 : static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8862 : unsigned vmid, uint64_t pd_addr)
8863 : {
8864 0 : if (ring->is_mes_queue)
8865 : gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8866 : else
8867 0 : amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8868 :
8869 : /* compute doesn't have PFP */
8870 0 : if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8871 : /* sync PFP to ME, otherwise we might get invalid PFP reads */
8872 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8873 0 : amdgpu_ring_write(ring, 0x0);
8874 : }
8875 0 : }
8876 :
8877 0 : static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8878 : u64 seq, unsigned int flags)
8879 : {
8880 0 : struct amdgpu_device *adev = ring->adev;
8881 :
8882 : /* we only allocate 32bit for each seq wb address */
8883 0 : BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8884 :
8885 : /* write fence seq to the "addr" */
8886 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8887 0 : amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8888 : WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8889 0 : amdgpu_ring_write(ring, lower_32_bits(addr));
8890 0 : amdgpu_ring_write(ring, upper_32_bits(addr));
8891 0 : amdgpu_ring_write(ring, lower_32_bits(seq));
8892 :
8893 0 : if (flags & AMDGPU_FENCE_FLAG_INT) {
8894 : /* set register to trigger INT */
8895 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8896 0 : amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8897 : WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8898 0 : amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8899 0 : amdgpu_ring_write(ring, 0);
8900 0 : amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8901 : }
8902 0 : }
8903 :
8904 0 : static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8905 : {
8906 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8907 0 : amdgpu_ring_write(ring, 0);
8908 0 : }
8909 :
8910 0 : static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8911 : uint32_t flags)
8912 : {
8913 0 : uint32_t dw2 = 0;
8914 :
8915 0 : if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8916 0 : gfx_v10_0_ring_emit_ce_meta(ring,
8917 0 : (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8918 :
8919 0 : dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8920 0 : if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8921 : /* set load_global_config & load_global_uconfig */
8922 0 : dw2 |= 0x8001;
8923 : /* set load_cs_sh_regs */
8924 0 : dw2 |= 0x01000000;
8925 : /* set load_per_context_state & load_gfx_sh_regs for GFX */
8926 0 : dw2 |= 0x10002;
8927 :
8928 : /* set load_ce_ram if preamble presented */
8929 0 : if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8930 0 : dw2 |= 0x10000000;
8931 : } else {
8932 : /* still load_ce_ram if this is the first time preamble presented
8933 : * although there is no context switch happens.
8934 : */
8935 0 : if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8936 0 : dw2 |= 0x10000000;
8937 : }
8938 :
8939 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8940 0 : amdgpu_ring_write(ring, dw2);
8941 0 : amdgpu_ring_write(ring, 0);
8942 0 : }
8943 :
8944 0 : static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8945 : {
8946 : unsigned ret;
8947 :
8948 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8949 0 : amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8950 0 : amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8951 0 : amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8952 0 : ret = ring->wptr & ring->buf_mask;
8953 0 : amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8954 :
8955 0 : return ret;
8956 : }
8957 :
8958 0 : static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8959 : {
8960 : unsigned cur;
8961 0 : BUG_ON(offset > ring->buf_mask);
8962 0 : BUG_ON(ring->ring[offset] != 0x55aa55aa);
8963 :
8964 0 : cur = (ring->wptr - 1) & ring->buf_mask;
8965 0 : if (likely(cur > offset))
8966 0 : ring->ring[offset] = cur - offset;
8967 : else
8968 0 : ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8969 0 : }
8970 :
8971 0 : static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8972 : {
8973 0 : int i, r = 0;
8974 0 : struct amdgpu_device *adev = ring->adev;
8975 0 : struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8976 0 : struct amdgpu_ring *kiq_ring = &kiq->ring;
8977 : unsigned long flags;
8978 :
8979 0 : if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8980 : return -EINVAL;
8981 :
8982 0 : spin_lock_irqsave(&kiq->ring_lock, flags);
8983 :
8984 0 : if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8985 0 : spin_unlock_irqrestore(&kiq->ring_lock, flags);
8986 0 : return -ENOMEM;
8987 : }
8988 :
8989 : /* assert preemption condition */
8990 0 : amdgpu_ring_set_preempt_cond_exec(ring, false);
8991 :
8992 : /* assert IB preemption, emit the trailing fence */
8993 0 : kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8994 : ring->trail_fence_gpu_addr,
8995 0 : ++ring->trail_seq);
8996 0 : amdgpu_ring_commit(kiq_ring);
8997 :
8998 0 : spin_unlock_irqrestore(&kiq->ring_lock, flags);
8999 :
9000 : /* poll the trailing fence */
9001 0 : for (i = 0; i < adev->usec_timeout; i++) {
9002 0 : if (ring->trail_seq ==
9003 0 : le32_to_cpu(*(ring->trail_fence_cpu_addr)))
9004 : break;
9005 0 : udelay(1);
9006 : }
9007 :
9008 0 : if (i >= adev->usec_timeout) {
9009 0 : r = -EINVAL;
9010 0 : DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
9011 : }
9012 :
9013 : /* deassert preemption condition */
9014 0 : amdgpu_ring_set_preempt_cond_exec(ring, true);
9015 0 : return r;
9016 : }
9017 :
9018 0 : static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
9019 : {
9020 0 : struct amdgpu_device *adev = ring->adev;
9021 0 : struct v10_ce_ib_state ce_payload = {0};
9022 : uint64_t offset, ce_payload_gpu_addr;
9023 : void *ce_payload_cpu_addr;
9024 : int cnt;
9025 :
9026 0 : cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
9027 :
9028 0 : if (ring->is_mes_queue) {
9029 0 : offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9030 : gfx[0].gfx_meta_data) +
9031 : offsetof(struct v10_gfx_meta_data, ce_payload);
9032 0 : ce_payload_gpu_addr =
9033 0 : amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9034 : ce_payload_cpu_addr =
9035 0 : amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
9036 : } else {
9037 0 : offset = offsetof(struct v10_gfx_meta_data, ce_payload);
9038 0 : ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
9039 0 : ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
9040 : }
9041 :
9042 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
9043 0 : amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
9044 : WRITE_DATA_DST_SEL(8) |
9045 : WR_CONFIRM) |
9046 : WRITE_DATA_CACHE_POLICY(0));
9047 0 : amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
9048 0 : amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
9049 :
9050 0 : if (resume)
9051 0 : amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
9052 : sizeof(ce_payload) >> 2);
9053 : else
9054 0 : amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
9055 : sizeof(ce_payload) >> 2);
9056 0 : }
9057 :
9058 0 : static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
9059 : {
9060 0 : struct amdgpu_device *adev = ring->adev;
9061 0 : struct v10_de_ib_state de_payload = {0};
9062 : uint64_t offset, gds_addr, de_payload_gpu_addr;
9063 : void *de_payload_cpu_addr;
9064 : int cnt;
9065 :
9066 0 : if (ring->is_mes_queue) {
9067 0 : offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9068 : gfx[0].gfx_meta_data) +
9069 : offsetof(struct v10_gfx_meta_data, de_payload);
9070 0 : de_payload_gpu_addr =
9071 0 : amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9072 0 : de_payload_cpu_addr =
9073 0 : amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
9074 :
9075 0 : offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9076 : gfx[0].gds_backup) +
9077 : offsetof(struct v10_gfx_meta_data, de_payload);
9078 0 : gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9079 : } else {
9080 0 : offset = offsetof(struct v10_gfx_meta_data, de_payload);
9081 0 : de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
9082 0 : de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
9083 :
9084 0 : gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
9085 : AMDGPU_CSA_SIZE - adev->gds.gds_size,
9086 : PAGE_SIZE);
9087 : }
9088 :
9089 0 : de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
9090 0 : de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
9091 :
9092 0 : cnt = (sizeof(de_payload) >> 2) + 4 - 2;
9093 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
9094 0 : amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
9095 : WRITE_DATA_DST_SEL(8) |
9096 : WR_CONFIRM) |
9097 : WRITE_DATA_CACHE_POLICY(0));
9098 0 : amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
9099 0 : amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
9100 :
9101 0 : if (resume)
9102 0 : amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
9103 : sizeof(de_payload) >> 2);
9104 : else
9105 0 : amdgpu_ring_write_multiple(ring, (void *)&de_payload,
9106 : sizeof(de_payload) >> 2);
9107 0 : }
9108 :
9109 0 : static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
9110 : bool secure)
9111 : {
9112 0 : uint32_t v = secure ? FRAME_TMZ : 0;
9113 :
9114 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
9115 0 : amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
9116 0 : }
9117 :
9118 0 : static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
9119 : uint32_t reg_val_offs)
9120 : {
9121 0 : struct amdgpu_device *adev = ring->adev;
9122 :
9123 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
9124 0 : amdgpu_ring_write(ring, 0 | /* src: register*/
9125 : (5 << 8) | /* dst: memory */
9126 : (1 << 20)); /* write confirm */
9127 0 : amdgpu_ring_write(ring, reg);
9128 0 : amdgpu_ring_write(ring, 0);
9129 0 : amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
9130 : reg_val_offs * 4));
9131 0 : amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
9132 : reg_val_offs * 4));
9133 0 : }
9134 :
9135 0 : static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
9136 : uint32_t val)
9137 : {
9138 0 : uint32_t cmd = 0;
9139 :
9140 0 : switch (ring->funcs->type) {
9141 : case AMDGPU_RING_TYPE_GFX:
9142 : cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
9143 : break;
9144 : case AMDGPU_RING_TYPE_KIQ:
9145 0 : cmd = (1 << 16); /* no inc addr */
9146 0 : break;
9147 : default:
9148 0 : cmd = WR_CONFIRM;
9149 0 : break;
9150 : }
9151 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
9152 0 : amdgpu_ring_write(ring, cmd);
9153 0 : amdgpu_ring_write(ring, reg);
9154 0 : amdgpu_ring_write(ring, 0);
9155 0 : amdgpu_ring_write(ring, val);
9156 0 : }
9157 :
9158 0 : static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
9159 : uint32_t val, uint32_t mask)
9160 : {
9161 0 : gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
9162 0 : }
9163 :
9164 0 : static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
9165 : uint32_t reg0, uint32_t reg1,
9166 : uint32_t ref, uint32_t mask)
9167 : {
9168 0 : int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9169 0 : struct amdgpu_device *adev = ring->adev;
9170 0 : bool fw_version_ok = false;
9171 :
9172 0 : fw_version_ok = adev->gfx.cp_fw_write_wait;
9173 :
9174 0 : if (fw_version_ok)
9175 0 : gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9176 : ref, mask, 0x20);
9177 : else
9178 0 : amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9179 : ref, mask);
9180 0 : }
9181 :
9182 0 : static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9183 : unsigned vmid)
9184 : {
9185 0 : struct amdgpu_device *adev = ring->adev;
9186 0 : uint32_t value = 0;
9187 :
9188 0 : value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9189 0 : value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9190 0 : value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9191 0 : value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9192 0 : WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9193 0 : }
9194 :
9195 : static void
9196 0 : gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9197 : uint32_t me, uint32_t pipe,
9198 : enum amdgpu_interrupt_state state)
9199 : {
9200 : uint32_t cp_int_cntl, cp_int_cntl_reg;
9201 :
9202 0 : if (!me) {
9203 0 : switch (pipe) {
9204 : case 0:
9205 0 : cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9206 0 : break;
9207 : case 1:
9208 0 : cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9209 0 : break;
9210 : default:
9211 0 : DRM_DEBUG("invalid pipe %d\n", pipe);
9212 0 : return;
9213 : }
9214 : } else {
9215 0 : DRM_DEBUG("invalid me %d\n", me);
9216 0 : return;
9217 : }
9218 :
9219 0 : switch (state) {
9220 : case AMDGPU_IRQ_STATE_DISABLE:
9221 0 : cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9222 0 : cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9223 : TIME_STAMP_INT_ENABLE, 0);
9224 0 : WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9225 : break;
9226 : case AMDGPU_IRQ_STATE_ENABLE:
9227 0 : cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9228 0 : cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9229 : TIME_STAMP_INT_ENABLE, 1);
9230 0 : WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9231 : break;
9232 : default:
9233 : break;
9234 : }
9235 : }
9236 :
9237 0 : static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9238 : int me, int pipe,
9239 : enum amdgpu_interrupt_state state)
9240 : {
9241 : u32 mec_int_cntl, mec_int_cntl_reg;
9242 :
9243 : /*
9244 : * amdgpu controls only the first MEC. That's why this function only
9245 : * handles the setting of interrupts for this specific MEC. All other
9246 : * pipes' interrupts are set by amdkfd.
9247 : */
9248 :
9249 0 : if (me == 1) {
9250 0 : switch (pipe) {
9251 : case 0:
9252 0 : mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9253 0 : break;
9254 : case 1:
9255 0 : mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9256 0 : break;
9257 : case 2:
9258 0 : mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9259 0 : break;
9260 : case 3:
9261 0 : mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9262 0 : break;
9263 : default:
9264 0 : DRM_DEBUG("invalid pipe %d\n", pipe);
9265 0 : return;
9266 : }
9267 : } else {
9268 0 : DRM_DEBUG("invalid me %d\n", me);
9269 0 : return;
9270 : }
9271 :
9272 0 : switch (state) {
9273 : case AMDGPU_IRQ_STATE_DISABLE:
9274 0 : mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9275 0 : mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9276 : TIME_STAMP_INT_ENABLE, 0);
9277 0 : WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9278 : break;
9279 : case AMDGPU_IRQ_STATE_ENABLE:
9280 0 : mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9281 0 : mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9282 : TIME_STAMP_INT_ENABLE, 1);
9283 0 : WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9284 : break;
9285 : default:
9286 : break;
9287 : }
9288 : }
9289 :
9290 0 : static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9291 : struct amdgpu_irq_src *src,
9292 : unsigned type,
9293 : enum amdgpu_interrupt_state state)
9294 : {
9295 0 : switch (type) {
9296 : case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9297 0 : gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9298 0 : break;
9299 : case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9300 0 : gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9301 0 : break;
9302 : case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9303 0 : gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9304 0 : break;
9305 : case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9306 0 : gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9307 0 : break;
9308 : case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9309 0 : gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9310 0 : break;
9311 : case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9312 0 : gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9313 0 : break;
9314 : case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9315 : gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9316 : break;
9317 : case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9318 : gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9319 : break;
9320 : case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9321 : gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9322 : break;
9323 : case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9324 : gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9325 : break;
9326 : default:
9327 : break;
9328 : }
9329 0 : return 0;
9330 : }
9331 :
9332 0 : static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9333 : struct amdgpu_irq_src *source,
9334 : struct amdgpu_iv_entry *entry)
9335 : {
9336 : int i;
9337 : u8 me_id, pipe_id, queue_id;
9338 : struct amdgpu_ring *ring;
9339 0 : uint32_t mes_queue_id = entry->src_data[0];
9340 :
9341 0 : DRM_DEBUG("IH: CP EOP\n");
9342 :
9343 0 : if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
9344 : struct amdgpu_mes_queue *queue;
9345 :
9346 0 : mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
9347 :
9348 0 : spin_lock(&adev->mes.queue_id_lock);
9349 0 : queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
9350 0 : if (queue) {
9351 0 : DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
9352 0 : amdgpu_fence_process(queue->ring);
9353 : }
9354 0 : spin_unlock(&adev->mes.queue_id_lock);
9355 : } else {
9356 0 : me_id = (entry->ring_id & 0x0c) >> 2;
9357 0 : pipe_id = (entry->ring_id & 0x03) >> 0;
9358 0 : queue_id = (entry->ring_id & 0x70) >> 4;
9359 :
9360 0 : switch (me_id) {
9361 : case 0:
9362 0 : if (pipe_id == 0)
9363 0 : amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9364 : else
9365 0 : amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9366 : break;
9367 : case 1:
9368 : case 2:
9369 0 : for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9370 0 : ring = &adev->gfx.compute_ring[i];
9371 : /* Per-queue interrupt is supported for MEC starting from VI.
9372 : * The interrupt can only be enabled/disabled per pipe instead
9373 : * of per queue.
9374 : */
9375 0 : if ((ring->me == me_id) &&
9376 0 : (ring->pipe == pipe_id) &&
9377 0 : (ring->queue == queue_id))
9378 0 : amdgpu_fence_process(ring);
9379 : }
9380 : break;
9381 : }
9382 : }
9383 :
9384 0 : return 0;
9385 : }
9386 :
9387 0 : static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9388 : struct amdgpu_irq_src *source,
9389 : unsigned type,
9390 : enum amdgpu_interrupt_state state)
9391 : {
9392 0 : switch (state) {
9393 : case AMDGPU_IRQ_STATE_DISABLE:
9394 : case AMDGPU_IRQ_STATE_ENABLE:
9395 0 : WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9396 : PRIV_REG_INT_ENABLE,
9397 : state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9398 : break;
9399 : default:
9400 : break;
9401 : }
9402 :
9403 0 : return 0;
9404 : }
9405 :
9406 0 : static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9407 : struct amdgpu_irq_src *source,
9408 : unsigned type,
9409 : enum amdgpu_interrupt_state state)
9410 : {
9411 0 : switch (state) {
9412 : case AMDGPU_IRQ_STATE_DISABLE:
9413 : case AMDGPU_IRQ_STATE_ENABLE:
9414 0 : WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9415 : PRIV_INSTR_INT_ENABLE,
9416 : state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9417 : break;
9418 : default:
9419 : break;
9420 : }
9421 :
9422 0 : return 0;
9423 : }
9424 :
9425 0 : static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9426 : struct amdgpu_iv_entry *entry)
9427 : {
9428 : u8 me_id, pipe_id, queue_id;
9429 : struct amdgpu_ring *ring;
9430 : int i;
9431 :
9432 0 : me_id = (entry->ring_id & 0x0c) >> 2;
9433 0 : pipe_id = (entry->ring_id & 0x03) >> 0;
9434 0 : queue_id = (entry->ring_id & 0x70) >> 4;
9435 :
9436 0 : switch (me_id) {
9437 : case 0:
9438 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9439 0 : ring = &adev->gfx.gfx_ring[i];
9440 : /* we only enabled 1 gfx queue per pipe for now */
9441 0 : if (ring->me == me_id && ring->pipe == pipe_id)
9442 0 : drm_sched_fault(&ring->sched);
9443 : }
9444 : break;
9445 : case 1:
9446 : case 2:
9447 0 : for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9448 0 : ring = &adev->gfx.compute_ring[i];
9449 0 : if (ring->me == me_id && ring->pipe == pipe_id &&
9450 0 : ring->queue == queue_id)
9451 0 : drm_sched_fault(&ring->sched);
9452 : }
9453 : break;
9454 : default:
9455 0 : BUG();
9456 : }
9457 0 : }
9458 :
9459 0 : static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9460 : struct amdgpu_irq_src *source,
9461 : struct amdgpu_iv_entry *entry)
9462 : {
9463 0 : DRM_ERROR("Illegal register access in command stream\n");
9464 0 : gfx_v10_0_handle_priv_fault(adev, entry);
9465 0 : return 0;
9466 : }
9467 :
9468 0 : static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9469 : struct amdgpu_irq_src *source,
9470 : struct amdgpu_iv_entry *entry)
9471 : {
9472 0 : DRM_ERROR("Illegal instruction in command stream\n");
9473 0 : gfx_v10_0_handle_priv_fault(adev, entry);
9474 0 : return 0;
9475 : }
9476 :
9477 0 : static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9478 : struct amdgpu_irq_src *src,
9479 : unsigned int type,
9480 : enum amdgpu_interrupt_state state)
9481 : {
9482 : uint32_t tmp, target;
9483 0 : struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9484 :
9485 0 : if (ring->me == 1)
9486 0 : target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9487 : else
9488 0 : target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9489 0 : target += ring->pipe;
9490 :
9491 0 : switch (type) {
9492 : case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9493 0 : if (state == AMDGPU_IRQ_STATE_DISABLE) {
9494 0 : tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9495 0 : tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9496 : GENERIC2_INT_ENABLE, 0);
9497 0 : WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9498 :
9499 0 : tmp = RREG32_SOC15_IP(GC, target);
9500 0 : tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9501 : GENERIC2_INT_ENABLE, 0);
9502 0 : WREG32_SOC15_IP(GC, target, tmp);
9503 : } else {
9504 0 : tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9505 0 : tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9506 : GENERIC2_INT_ENABLE, 1);
9507 0 : WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9508 :
9509 0 : tmp = RREG32_SOC15_IP(GC, target);
9510 0 : tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9511 : GENERIC2_INT_ENABLE, 1);
9512 0 : WREG32_SOC15_IP(GC, target, tmp);
9513 : }
9514 : break;
9515 : default:
9516 0 : BUG(); /* kiq only support GENERIC2_INT now */
9517 : break;
9518 : }
9519 0 : return 0;
9520 : }
9521 :
9522 0 : static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9523 : struct amdgpu_irq_src *source,
9524 : struct amdgpu_iv_entry *entry)
9525 : {
9526 : u8 me_id, pipe_id, queue_id;
9527 0 : struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9528 :
9529 0 : me_id = (entry->ring_id & 0x0c) >> 2;
9530 0 : pipe_id = (entry->ring_id & 0x03) >> 0;
9531 0 : queue_id = (entry->ring_id & 0x70) >> 4;
9532 0 : DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9533 : me_id, pipe_id, queue_id);
9534 :
9535 0 : amdgpu_fence_process(ring);
9536 0 : return 0;
9537 : }
9538 :
9539 0 : static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9540 : {
9541 0 : const unsigned int gcr_cntl =
9542 : PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9543 : PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9544 : PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9545 : PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9546 : PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9547 : PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9548 : PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9549 : PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9550 :
9551 : /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9552 0 : amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9553 0 : amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9554 0 : amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
9555 0 : amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
9556 0 : amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9557 0 : amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
9558 0 : amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9559 0 : amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9560 0 : }
9561 :
9562 : static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9563 : .name = "gfx_v10_0",
9564 : .early_init = gfx_v10_0_early_init,
9565 : .late_init = gfx_v10_0_late_init,
9566 : .sw_init = gfx_v10_0_sw_init,
9567 : .sw_fini = gfx_v10_0_sw_fini,
9568 : .hw_init = gfx_v10_0_hw_init,
9569 : .hw_fini = gfx_v10_0_hw_fini,
9570 : .suspend = gfx_v10_0_suspend,
9571 : .resume = gfx_v10_0_resume,
9572 : .is_idle = gfx_v10_0_is_idle,
9573 : .wait_for_idle = gfx_v10_0_wait_for_idle,
9574 : .soft_reset = gfx_v10_0_soft_reset,
9575 : .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9576 : .set_powergating_state = gfx_v10_0_set_powergating_state,
9577 : .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9578 : };
9579 :
9580 : static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9581 : .type = AMDGPU_RING_TYPE_GFX,
9582 : .align_mask = 0xff,
9583 : .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9584 : .support_64bit_ptrs = true,
9585 : .secure_submission_supported = true,
9586 : .vmhub = AMDGPU_GFXHUB_0,
9587 : .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9588 : .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9589 : .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9590 : .emit_frame_size = /* totally 242 maximum if 16 IBs */
9591 : 5 + /* COND_EXEC */
9592 : 7 + /* PIPELINE_SYNC */
9593 : SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9594 : SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9595 : 2 + /* VM_FLUSH */
9596 : 8 + /* FENCE for VM_FLUSH */
9597 : 20 + /* GDS switch */
9598 : 4 + /* double SWITCH_BUFFER,
9599 : * the first COND_EXEC jump to the place
9600 : * just prior to this double SWITCH_BUFFER
9601 : */
9602 : 5 + /* COND_EXEC */
9603 : 7 + /* HDP_flush */
9604 : 4 + /* VGT_flush */
9605 : 14 + /* CE_META */
9606 : 31 + /* DE_META */
9607 : 3 + /* CNTX_CTRL */
9608 : 5 + /* HDP_INVL */
9609 : 8 + 8 + /* FENCE x2 */
9610 : 2 + /* SWITCH_BUFFER */
9611 : 8, /* gfx_v10_0_emit_mem_sync */
9612 : .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9613 : .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9614 : .emit_fence = gfx_v10_0_ring_emit_fence,
9615 : .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9616 : .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9617 : .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9618 : .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9619 : .test_ring = gfx_v10_0_ring_test_ring,
9620 : .test_ib = gfx_v10_0_ring_test_ib,
9621 : .insert_nop = amdgpu_ring_insert_nop,
9622 : .pad_ib = amdgpu_ring_generic_pad_ib,
9623 : .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9624 : .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9625 : .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9626 : .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9627 : .preempt_ib = gfx_v10_0_ring_preempt_ib,
9628 : .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9629 : .emit_wreg = gfx_v10_0_ring_emit_wreg,
9630 : .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9631 : .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9632 : .soft_recovery = gfx_v10_0_ring_soft_recovery,
9633 : .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9634 : };
9635 :
9636 : static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9637 : .type = AMDGPU_RING_TYPE_COMPUTE,
9638 : .align_mask = 0xff,
9639 : .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9640 : .support_64bit_ptrs = true,
9641 : .vmhub = AMDGPU_GFXHUB_0,
9642 : .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9643 : .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9644 : .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9645 : .emit_frame_size =
9646 : 20 + /* gfx_v10_0_ring_emit_gds_switch */
9647 : 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9648 : 5 + /* hdp invalidate */
9649 : 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9650 : SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9651 : SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9652 : 2 + /* gfx_v10_0_ring_emit_vm_flush */
9653 : 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9654 : 8, /* gfx_v10_0_emit_mem_sync */
9655 : .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9656 : .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9657 : .emit_fence = gfx_v10_0_ring_emit_fence,
9658 : .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9659 : .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9660 : .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9661 : .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9662 : .test_ring = gfx_v10_0_ring_test_ring,
9663 : .test_ib = gfx_v10_0_ring_test_ib,
9664 : .insert_nop = amdgpu_ring_insert_nop,
9665 : .pad_ib = amdgpu_ring_generic_pad_ib,
9666 : .emit_wreg = gfx_v10_0_ring_emit_wreg,
9667 : .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9668 : .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9669 : .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9670 : };
9671 :
9672 : static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9673 : .type = AMDGPU_RING_TYPE_KIQ,
9674 : .align_mask = 0xff,
9675 : .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9676 : .support_64bit_ptrs = true,
9677 : .vmhub = AMDGPU_GFXHUB_0,
9678 : .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9679 : .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9680 : .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9681 : .emit_frame_size =
9682 : 20 + /* gfx_v10_0_ring_emit_gds_switch */
9683 : 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9684 : 5 + /*hdp invalidate */
9685 : 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9686 : SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9687 : SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9688 : 2 + /* gfx_v10_0_ring_emit_vm_flush */
9689 : 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9690 : .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9691 : .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9692 : .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9693 : .test_ring = gfx_v10_0_ring_test_ring,
9694 : .test_ib = gfx_v10_0_ring_test_ib,
9695 : .insert_nop = amdgpu_ring_insert_nop,
9696 : .pad_ib = amdgpu_ring_generic_pad_ib,
9697 : .emit_rreg = gfx_v10_0_ring_emit_rreg,
9698 : .emit_wreg = gfx_v10_0_ring_emit_wreg,
9699 : .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9700 : .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9701 : };
9702 :
9703 : static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9704 : {
9705 : int i;
9706 :
9707 0 : adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9708 :
9709 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9710 0 : adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9711 :
9712 0 : for (i = 0; i < adev->gfx.num_compute_rings; i++)
9713 0 : adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9714 : }
9715 :
9716 : static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9717 : .set = gfx_v10_0_set_eop_interrupt_state,
9718 : .process = gfx_v10_0_eop_irq,
9719 : };
9720 :
9721 : static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9722 : .set = gfx_v10_0_set_priv_reg_fault_state,
9723 : .process = gfx_v10_0_priv_reg_irq,
9724 : };
9725 :
9726 : static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9727 : .set = gfx_v10_0_set_priv_inst_fault_state,
9728 : .process = gfx_v10_0_priv_inst_irq,
9729 : };
9730 :
9731 : static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9732 : .set = gfx_v10_0_kiq_set_interrupt_state,
9733 : .process = gfx_v10_0_kiq_irq,
9734 : };
9735 :
9736 : static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9737 : {
9738 0 : adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9739 0 : adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9740 :
9741 0 : adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9742 0 : adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9743 :
9744 0 : adev->gfx.priv_reg_irq.num_types = 1;
9745 0 : adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9746 :
9747 0 : adev->gfx.priv_inst_irq.num_types = 1;
9748 0 : adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9749 : }
9750 :
9751 : static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9752 : {
9753 0 : switch (adev->ip_versions[GC_HWIP][0]) {
9754 : case IP_VERSION(10, 1, 10):
9755 : case IP_VERSION(10, 1, 1):
9756 : case IP_VERSION(10, 1, 3):
9757 : case IP_VERSION(10, 1, 4):
9758 : case IP_VERSION(10, 3, 2):
9759 : case IP_VERSION(10, 3, 1):
9760 : case IP_VERSION(10, 3, 4):
9761 : case IP_VERSION(10, 3, 5):
9762 : case IP_VERSION(10, 3, 6):
9763 : case IP_VERSION(10, 3, 3):
9764 : case IP_VERSION(10, 3, 7):
9765 0 : adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9766 : break;
9767 : case IP_VERSION(10, 1, 2):
9768 : case IP_VERSION(10, 3, 0):
9769 0 : adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9770 : break;
9771 : default:
9772 : break;
9773 : }
9774 : }
9775 :
9776 : static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9777 : {
9778 0 : unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9779 0 : adev->gfx.config.max_sh_per_se *
9780 0 : adev->gfx.config.max_shader_engines;
9781 :
9782 0 : adev->gds.gds_size = 0x10000;
9783 0 : adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9784 0 : adev->gds.gws_size = 64;
9785 0 : adev->gds.oa_size = 16;
9786 : }
9787 :
9788 : static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9789 : {
9790 : /* set gfx eng mqd */
9791 0 : adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9792 : sizeof(struct v10_gfx_mqd);
9793 0 : adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9794 : gfx_v10_0_gfx_mqd_init;
9795 : /* set compute eng mqd */
9796 0 : adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9797 : sizeof(struct v10_compute_mqd);
9798 0 : adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9799 : gfx_v10_0_compute_mqd_init;
9800 : }
9801 :
9802 0 : static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9803 : u32 bitmap)
9804 : {
9805 : u32 data;
9806 :
9807 0 : if (!bitmap)
9808 : return;
9809 :
9810 0 : data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9811 0 : data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9812 :
9813 0 : WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9814 : }
9815 :
9816 0 : static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9817 : {
9818 0 : u32 disabled_mask =
9819 0 : ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9820 0 : u32 efuse_setting = 0;
9821 0 : u32 vbios_setting = 0;
9822 :
9823 0 : efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9824 0 : efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9825 0 : efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9826 :
9827 0 : vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9828 0 : vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9829 0 : vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9830 :
9831 0 : disabled_mask |= efuse_setting | vbios_setting;
9832 :
9833 0 : return (~disabled_mask);
9834 : }
9835 :
9836 0 : static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9837 : {
9838 : u32 wgp_idx, wgp_active_bitmap;
9839 : u32 cu_bitmap_per_wgp, cu_active_bitmap;
9840 :
9841 0 : wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9842 0 : cu_active_bitmap = 0;
9843 :
9844 0 : for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9845 : /* if there is one WGP enabled, it means 2 CUs will be enabled */
9846 0 : cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9847 0 : if (wgp_active_bitmap & (1 << wgp_idx))
9848 0 : cu_active_bitmap |= cu_bitmap_per_wgp;
9849 : }
9850 :
9851 0 : return cu_active_bitmap;
9852 : }
9853 :
9854 0 : static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9855 : struct amdgpu_cu_info *cu_info)
9856 : {
9857 0 : int i, j, k, counter, active_cu_number = 0;
9858 0 : u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9859 : unsigned disable_masks[4 * 2];
9860 :
9861 0 : if (!adev || !cu_info)
9862 : return -EINVAL;
9863 :
9864 0 : amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9865 :
9866 0 : mutex_lock(&adev->grbm_idx_mutex);
9867 0 : for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9868 0 : for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9869 0 : bitmap = i * adev->gfx.config.max_sh_per_se + j;
9870 0 : if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9871 0 : (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9872 0 : (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
9873 0 : (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9874 0 : ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9875 0 : continue;
9876 0 : mask = 1;
9877 0 : ao_bitmap = 0;
9878 0 : counter = 0;
9879 0 : gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9880 0 : if (i < 4 && j < 2)
9881 0 : gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9882 0 : adev, disable_masks[i * 2 + j]);
9883 0 : bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9884 0 : cu_info->bitmap[i][j] = bitmap;
9885 :
9886 0 : for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9887 0 : if (bitmap & mask) {
9888 0 : if (counter < adev->gfx.config.max_cu_per_sh)
9889 0 : ao_bitmap |= mask;
9890 0 : counter++;
9891 : }
9892 0 : mask <<= 1;
9893 : }
9894 0 : active_cu_number += counter;
9895 0 : if (i < 2 && j < 2)
9896 0 : ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9897 0 : cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9898 : }
9899 : }
9900 0 : gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9901 0 : mutex_unlock(&adev->grbm_idx_mutex);
9902 :
9903 0 : cu_info->number = active_cu_number;
9904 0 : cu_info->ao_cu_mask = ao_cu_mask;
9905 0 : cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9906 :
9907 0 : return 0;
9908 : }
9909 :
9910 0 : static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9911 : {
9912 : uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9913 :
9914 0 : efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9915 0 : efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9916 0 : efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9917 :
9918 0 : vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9919 0 : vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9920 0 : vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9921 :
9922 0 : max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9923 0 : adev->gfx.config.max_shader_engines);
9924 0 : disabled_sa = efuse_setting | vbios_setting;
9925 0 : disabled_sa &= max_sa_mask;
9926 :
9927 0 : return disabled_sa;
9928 : }
9929 :
9930 0 : static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9931 : {
9932 : uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9933 : uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9934 :
9935 0 : disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9936 :
9937 0 : max_sa_per_se = adev->gfx.config.max_sh_per_se;
9938 0 : max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9939 0 : max_shader_engines = adev->gfx.config.max_shader_engines;
9940 :
9941 0 : for (se_index = 0; max_shader_engines > se_index; se_index++) {
9942 0 : disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9943 0 : disabled_sa_per_se &= max_sa_per_se_mask;
9944 0 : if (disabled_sa_per_se == max_sa_per_se_mask) {
9945 0 : WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9946 : break;
9947 : }
9948 : }
9949 0 : }
9950 :
9951 0 : static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9952 : {
9953 0 : WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9954 : (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9955 : (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9956 : (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9957 :
9958 0 : WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9959 0 : WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9960 : (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9961 : (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9962 : (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9963 : (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9964 :
9965 0 : WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9966 : (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9967 : (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9968 : (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9969 :
9970 0 : WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9971 :
9972 0 : WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9973 : (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9974 0 : }
9975 :
9976 : const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9977 : {
9978 : .type = AMD_IP_BLOCK_TYPE_GFX,
9979 : .major = 10,
9980 : .minor = 0,
9981 : .rev = 0,
9982 : .funcs = &gfx_v10_0_ip_funcs,
9983 : };
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